JPH08237235A - Digital communication system - Google Patents

Abstract

PURPOSE: To realize bit phase synchronism even if the phase difference of first and second clock signals exceeds one period owing to the phase fluctuation of the first and second clock signals without increasing a signal line. CONSTITUTION: After a D flip flop circuit 32 phase-synchronizes a data signal DA with a clock signal CA, it is transmitted to a board B through a data signal line 37. The clock signal CA is also transmitted to the board B through a clock signal line 38. The data signal DA transmitted to the board B is received by a D flip flop circuit 35 by making it synchronize with the phase of the clock signal CA. The data signal DB is reloaded from the clock signal CB to the clock signal CA and is transmitted to a board A through a data signal line 39. The data signal DA transmitted to the board A is phase synchronized with the clock signal outputted from a delay circuit 33 and it is received by a D flip flop circuit 34.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital communication system for mutually transmitting digital data signals between two communication points.

[0002]

2. Description of the Related Art Generally, a digital exchange is composed of a plurality of racks. Each rack is composed of a plurality of boards. Therefore, when configuring a digital exchange, a digital communication system for transmitting digital data signals between racks or boards is required.

When a digital data signal is transmitted between racks or between boards, when the data transmission speed becomes high, effects such as accumulation of jitter and deterioration of waveform appear. In order to deal with this problem, conventionally, the techniques described in the following documents have been considered.

References: 1991 IEICE Transactions
B-1, Vol.j74-B-1, No.4, pp. 304-312, the technology described in this document is that the bit phase synchronization circuit is provided at the input / output end of each rack or each board. It is designed to solve problems.

FIG. 2 is a block diagram showing the configuration of a digital communication system using the technique described in this document. In the figure, a digital communication system for transmitting a data signal between two boards is shown as a representative.

In the illustrated system, the data signal DA is transmitted from the board A to the board B, and the data signal DB is transmitted from the board B to the board A. Boards A and B are provided with clock signals C from clock supply source 11 respectively.
A and CB are supplied.

When the data signal DA is transmitted from the board A to the board B, the data signal DA is phase-synchronized bit by bit with the clock signal CA by the D flip-flop circuit (FF) 12 and then transmitted to the board B. To be done.
The data signal DA transmitted to the board B is received by the bit phase synchronization circuit 14 in bit phase synchronization with the transmission operation.

Similarly, when the data signal DB is transmitted from the board B to the board A, the data signal DB is phase-synchronized bit by bit with the clock signal CB by the D flip-flop circuit 15 and then transmitted to the board A. To be done.
The data signal DB transmitted to the board A is received by the bit phase synchronization circuit 13 in bit phase synchronization with the transmission operation.

The bit phase synchronization circuit 14 includes a D flip-flop circuit 141, a multi-phase clock generation circuit 142, and
It has a phase comparison circuit 143 and an optimum phase selection circuit 144.

In such a structure, the multi-phase clock generation circuit 142 delays the clock signal CB to generate a plurality of clock signals having different phases. Phase comparison circuit 1
43 detects an edge (change point) of the data signal DA,
The phases of this detection output and the clock signal CB are compared.
The optimum phase selection circuit 143, based on the comparison result,
A clock signal having an optimum phase for latching the data signal DA is selected from the multi-phase clock signals. D
The flip-flop circuit 141 latches the data signal DA according to this clock signal.

The bit phase synchronization circuit 13 also includes a D flip-flop circuit 131, a multi-phase clock generation circuit 132, and
It has a phase comparison circuit 133 and an optimum phase selection circuit 134, compares the phases of the data signal DB and the clock signal CA, and latches the data signal DB at the optimum phase based on the comparison result. .

[0012]

However, in the above configuration, when the phase difference between the clock signals CA and CB causes the phase difference between them to exceed one cycle of the clock signals CA and CB, a missing bit or a remainder occurs. The bit phase synchronization circuits 13 and 14 cannot select the clock signal having the optimum phase.

As a result, in the conventional digital communication system, when the phase difference between the clock signals CA and CB causes the phase difference between the clock signals CA and CB to exceed one cycle, the data signals DA and DB are transmitted. However, there was a problem that it was not possible to receive in phase synchronization with the bit.

FIG. 3 is a timing chart showing this situation.

In the figure, (a) shows a clock signal CA.
6B shows a data signal DA (denoted as DA1 in the figure) input to the D flip-flop circuit 141, and FIG. 6C shows a multiphase clock generated by the multiphase clock generation circuit 142. Signals are shown, and (d) shows a data signal DA (denoted as DA2 in the figure) output from the D flip-flop circuit 141.

In addition, in (b), a numeral indicates a bit number. Further, in (c), the arrow indicates the phase selected by the optimum phase selection circuit 144. That is, it indicates the latch phase of the data signal DA.

The figure shows the case where the phase of the clock signal CA fluctuates and the bits with bit numbers 6 and 10 are missing from the data signal DA2 output from the D flip-flop circuit 141.

Although detailed description is omitted, such a problem also occurs in the bit phase synchronization circuit 13.

This problem can be solved by using the digital communication system having the configuration shown in FIG.

The system shown in the figure transmits not only the data signal DA or DB but also the clock signal CA or CB from the transmitting side board A or B.

In FIG. 4, reference numeral 21 is a clock supply source for supplying the clock signals CA and CB.
Reference numeral 25 is a D flip-flop circuit for transmitting the data signals DA and DB, respectively, and 24 and 23 are D flip-flop circuits for receiving the data signals DA and DB, respectively.

According to this structure, the data signal DA
Is transmitted and received by the same clock signal CA, the phases of the clock signals CA and CB fluctuate, and even if the phase difference between the two exceeds one cycle, the data signal DA is bit-phase synchronized with the transmission operation. Can be received.
The same applies to the data signal DB.

However, in the case of such a configuration, 2
Since two clock signals CA and CB must be transmitted in addition to one data signal DA and DB, a new problem arises that the number of signal lines between the boards A and B is significantly increased.

[0024]

The present invention includes first and second aspects.
In a digital communication system in which digital data signals are mutually transmitted between two communication points, the first data signal is transmitted when the first data signal is transmitted from the first communication point to the second communication point. When transmitting the second data signal from the second communication point to the first communication point together with the first clock signal for transmission, the second data signal is converted into the second data signal. In this configuration, the synchronized second clock signal is transferred onto the first clock signal for transmission.

[0025]

When the first data signal is transmitted from the first communication point to the second communication point, the first data signal is phase-synchronized with the first clock signal for each bit, and the data signal line is connected. Is transmitted to the second communication point via. Along with this, the first clock signal is also transmitted to the second communication point via the clock signal line. The first data signal transmitted to the second communication point is received in phase synchronization with the first clock signal sent from the first communication point.

When transmitting the second data signal from the second communication point to the first communication point, this data signal is transferred from the second clock signal synchronized with this data signal to the first clock signal. To be After this, this data signal is
The signal is transmitted to the first communication point via the data signal line, and is received in phase synchronization with the third clock signal generated from the first clock signal.

[0027]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, two boards A,
A case where a digital data signal is transmitted between B is shown as a representative.

The illustrated digital communication system includes a clock supply source 31 and a D flip-flop circuit (FF) 3.
2, 34 and 35, a delay circuit 33, an elastic store circuit (ES) 36, data signal lines 37 and 39,
It has a clock signal line 38.

The D flip-flop circuits 32 and 34 and the delay circuit 33 are provided on the board A. D flip-flop circuit 35 and elastic store circuit 36
Are provided on board B.

The clock supply source 31 is a clock signal C.
Output A and CB. The clock signals CA and CB are
Used as a reference clock signal on boards A and B, respectively. The frequencies and phases of these clock signals CA and CB are
In principle, the same value is set if the delay variation of the element is ignored.

The D flip-flop circuit 32 is a board B
It has a function of transmitting the data signal DA for transmitting to each other in synchronization with the clock signal CA for each bit. The data signal line 37 has a function of transmitting the data signal DA transmitted from the D flip-flop circuit 32 to the board B. The clock signal line 38 has a function of transmitting the clock signal CA to the board B.

The D flip-flop circuit 35 transmits the data signal DA transmitted via the data signal line 37 to the clock signal C transmitted via the clock signal line 38.
It has a function of receiving in phase synchronization with A.

The elastic store circuit 36 transfers the data signal DB for transmission to the board A to the data signal D.
From the clock signal CB synchronized with B to the clock signal line 38
It has a function of transmitting the clock signal CA transferred over the clock signal CA.

The elastic store circuit 35 has an internal memory, and writes the data signal DB to the internal memory according to the clock signal CB and reads it according to the clock signal CA, so that the data signal DB is changed from the clock signal CB to the clock signal CA. It is designed to be transferred to.

The elastic store circuit 36 is
Usually, it has two functions of a bit synchronization function and a frame synchronization function. Here, only the bit synchronization function is used.

The data signal line 39 receives the data signal DB transmitted by the elastic store circuit 36 from the board A.
It has the function of transmitting to.

Delay circuit 33 delays clock signal CA to generate a clock signal for receiving data signal DB. The delay time of the delay circuit 34 is
It is set to twice the delay time of the clock signal CA between B. This is because the data signal DB sent from the board B is received in phase synchronization with the clock signal CA sent from the board A to the board B.

The D flip-flop circuit 34 has a function of receiving the data signal DB sent via the data signal line 39 in phase synchronization with the clock signal output from the delay circuit 33.

The operation of the above configuration will be described.

First, the operation of transmitting the data signal DA from the board A to the board B will be described.

The data signal DA is supplied to the D flip-flop circuit 32. The data signal DA supplied to the D flip-flop circuit 32 is sequentially latched bit by bit in the D flip-flop circuit 32 according to the clock signal CA. As a result, the clock signal CA
A data signal DA that is phase-locked with is obtained.

The data signal DA is sent to the data signal line 37.
Is transmitted to the board B via. At the same time,
The clock signal CA is also transmitted to the board B via the clock signal line 38.

The data signal DA transmitted to the board B is
It is supplied to the D flip-flop circuit 35. The data signal DA supplied to the D flip-flop circuit 35 is the clock signal CA sent via the clock signal line 38.
The bits are sequentially latched in the D flip-flop circuit 35 bit by bit in synchronism with. As a result, the data signal DA sent from the board A is received in bit phase synchronization with the sending operation.

Next, the operation of transmitting the data signal DB from the board B to the board A will be described.

The data signal DB is supplied to the elastic store circuit 36. The data signal DB supplied to the elastic store circuit 36 is sequentially written bit by bit in the internal memory according to the clock signal CB synchronized with the data signal DB.

Data signal DB written in the internal memory
Are sequentially read out bit by bit in accordance with the clock signal CA sent via the clock signal line 38. As a result, the data signal DB has been transferred from the clock signal CB to the clock signal CA.

Data signal DB for which the transfer has been completed
Are transmitted to the board A via the data signal line 39.

The data signal DB transmitted to the board A is
It is supplied to the D flip-flop circuit 34. The data signal DB supplied to the D flip-flop circuit 34 is sequentially latched bit by bit in the D flip-flop circuit 34 according to the clock signal output from the delay circuit 33. As a result, the data signal DB is received in bit phase synchronization with the transmission operation.

According to this embodiment described in detail above, the following effects can be obtained.

(1) First, according to this embodiment, when the data signal DA is transmitted from the board A to the board B, the clock signal CA for transmission is also transmitted, and the data signal DB is transmitted from the board B to the board A. Since the data signal DB is transferred from the clock signal CB to the clock signal CA when transmitting, the phase of the two data signals DA and DB transmitted between the boards A and B is changed to the clock signal CA. Can be unified in the phase.

As a result, even if the phase difference between the clock signals CA and CB exceeds one cycle due to the phase fluctuations of the clock signals CA and CB,
The data signals DA and DB can be received in bit phase synchronization with the transmission operation.

Further, since only the clock signal line 38 for transmitting the clock signal CA needs to be provided as the clock signal line, the number of signal lines between the boards A and B can be reduced as compared with the configuration of FIG. .

(2) According to this embodiment, the clock signal CA is delayed by the delay circuit 33 to generate the clock signal for receiving the data signal DB. It can be generated with a simple configuration.

Although one embodiment of the present invention has been described in detail above, the present invention is not limited to the above embodiment.

(1) For example, in the above embodiment, the delay circuit 33 delays the clock signal CA,
The case where the clock signal for receiving the data signal DB is generated has been described.

However, in the present invention, this clock signal may be generated using the bit phase synchronizing circuits 13 and 14 as shown in FIG. That is, by delaying the clock signal CA, a plurality of clock signals having different phases are generated, the phases of the data signal DB and the clock signal CA are compared, and based on the result of this phase comparison, One of them may be selected as the clock signal for reception.

According to this structure, the data signal DB
Since the phase of the clock signal for reception can be determined based on the actual phase of, the case where an unexpected phase variation occurs in the data signal DB can be dealt with.

(2) In the above embodiment, the case where the phases of the data signals DA and DB are unified with the phase of the clock signal CA has been described. However, according to the present invention, the data signal D
The phases of A and DB may be unified with the phase of the clock signal CB.

(3) In the above embodiment, the case where the present invention is applied to a digital communication system for mutually transmitting digital data signals between two boards has been described. However, the present invention can also be applied to a digital communication system that transmits a digital data signal between two racks. Further, not limited to these, it can be applied to general digital communication systems for transmitting digital data signals between two communication points.

(4) In addition to this, it goes without saying that the present invention can be variously modified and implemented without departing from the scope of the invention.

[0061]

As described above in detail, according to the present invention,
When transmitting the first data signal from the first communication point to the second communication point, a first data signal for transmitting the first data signal is transmitted.
Of the second data signal from the second communication point to the first communication point.
Since the second data signal is transferred from the second clock signal to the first clock signal, the first and second data signals are transmitted.
The phase of the data signal can be unified with the phase of the first clock signal.

As a result, bit phase synchronization can be obtained even if the phase difference between the first and second clock signals exceeds one cycle due to the phase fluctuations.

Since only the clock signal line for transmitting the first clock signal needs to be provided as the signal line for transmitting the clock signal, compared with the structure for transmitting the first and second clock signals. The number of signal lines can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a configuration of a conventional digital communication system.

FIG. 3 is a diagram for explaining the problem of FIG.

FIG. 4 is a block diagram showing another example of the configuration of a conventional digital communication system.

[Explanation of symbols]

 31 ... Clock supply source 32, 34, 35 ... D flip-flop circuit 33 ... Delay circuit 36 ... Elastic store circuit 37, 39 ... Data signal line 38 ... Clock signal line

Claims (3)

[Claims] 1. A digital communication system for mutually transmitting a digital data signal between two first and second communication points, wherein the digital communication signal is provided at the first communication point and is transmitted to the second communication point. For transmitting the first data signal for synchronizing with the first clock signal in phase, and the first data signal transmitted by the first data transmitting means for the second communication. A first data signal line for transmitting to a point, a clock signal line for transmitting the first clock signal to the second communication point, and a first data signal line provided at the second communication point, First data receiving means for receiving the first data signal transmitted via the data signal line in phase synchronization with the first clock signal transmitted via the clock signal line, Provided at the second communication point And a second clock signal transmitted from the second clock signal synchronized with the second data signal to the first communication point via the clock signal line. Second transmitting means for transmitting the signal in addition to the signal; and a second data signal line for transmitting the second data signal transmitted by the second transmitting means to the first communication point, A clock that is provided at the first communication point and that generates a third clock signal that is phase-synchronized with the second data signal transmitted from the first clock signal via the second data signal line. A signal generating means, and the signal transmitted through the second data signal line, which is provided at the first communication point and is phase-synchronized with the third clock signal generated by the clock signal generating means. Second day Digital communication system characterized by comprising a second data receiving means for receiving a signal. 2. The clock signal generating means comprises the first
2. The digital communication system according to claim 1, wherein the third clock signal is generated by delaying the clock signal of. 3. The clock signal generating means delays the first clock signal to generate a plurality of clock signals having different phases, and the second data signal line. Phase comparison means for comparing the phases of the second data signal and the first clock signal transmitted by the multi-phase clock generation means based on the phase comparison result of the phase comparison means. 2. The digital communication system according to claim 1, further comprising: a clock selecting unit that selects one of the plurality of clock signals as the third clock signal.