JPH08227579A - Semiconductor storage device - Google Patents

Abstract

PURPOSE: To provide a semiconductor storage device which prevents the disappearance of data and the increase of power consumption. CONSTITUTION: An address generation circuit 1 and an address switching circuit 40 output address signals, A0 to A10, when the refresh cycle time Tref established by the user is less than a specified value, and output address signals, A0 to A11, when Tref is more than the specified value. A row decoder 42 selects one word line WL in response to the signals, A0 to A11, and two word lines WL in response to the signals, A0 to A10. Because two word lines WL are selected to refresh the memory, disappearance of data is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that requires data refresh.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional dynamic random access memory (hereinafter referred to as a memory having a storage capacity of 16 Mbits).
FIG. 3 is a block diagram showing a configuration of a DRAM).

Referring to FIG. 5, this DRAM includes control signal input terminals 30 to 32, 34, an address signal input terminal group 33, a data signal input / output terminal group 35, a ground terminal 36 and a power supply terminal 37. The DRAM also includes a clock generation circuit 38, a row and column address buffer 39,
An address switching circuit 40, an address generation circuit 41, a row decoder 42, a column decoder 43, a memory mat 44, an input buffer 47 and an output buffer 48 are provided, and the memory mat 44 includes a memory array 45 and a sense refresh amplifier + input / output control circuit 46. Including.

Clock generation circuit 38 receives a signal ext. Externally applied via control signal input terminals 30 and 31.
/ RAS, ext. A predetermined operation mode is selected based on / CAS to control the entire DRAM.

Row and column address buffer 39 selectively applies address signals A0 to A11 externally applied through address signal input terminal group 33 to row decoder 42 and column decoder 43 during read and write operations.
The address generation circuit 41 is activated by the refresh instruction signal / CBR output from the clock generation circuit 38, and supplies an address signal for refreshing to the row decoder 42 during the refresh operation. Address switching circuit 40
Is controlled by the refresh instruction signal / CBR,
Row and column address buffer 3 during read and write operations
9 and the row decoder 42 are connected, and the address generation circuit 41 and the row decoder 42 are connected during the refresh operation.

The memory array 45 has a storage capacity of 16 Mbits. 1-bit data is stored in one memory cell. Each memory cell is arranged at a predetermined address determined by a row address and a column address.

Row decoder 42 specifies a row address of memory array 45 in response to an address signal applied from row and column address buffer 39 or address generation circuit 41. The column decoder 43 responds to the address signal supplied from the row and column address buffer 39 by
The column address of the memory array 45 is designated.

Sense refresh amplifier + input / output control circuit 46 connects the memory cell at the address designated by row decoder 42 and column decoder 43 to one end of global signal input / output line pair GIO during the read and write operations. Further, the sense refresh amplifier + input / output control circuit 46 refreshes the data in the memory cell at the row address designated by the row decoder 42 during the refresh operation.

The other end of the global signal input / output line pair GIO is connected to the input buffer 47 and the output buffer 48. Input buffer 47 receives signal ext. Externally applied via control signal input terminal 32 during a write operation. / W
In response, the data input from the data signal input / output terminal group 35 is applied to the selected memory cell via the global signal input / output line pair GIO. Output buffer 48 receives signal ext. In response to / OE, the read data from the selected memory cell is output to data input / output terminal group 35.

FIG. 6 is a diagram showing a chip layout of the DRAM shown in FIG. In FIG. 6, the DRAM is
It includes four memory mats 44.1 to 44.4 each having a storage capacity of 4 Mbits. Memory mat 44.1-
Each of 44.4 includes 16 memory arrays MA1 to MA16 each having a storage capacity of 256 Kbits. The four memory mats 44.1 to 44.4 form the memory mat 44 of FIG.

Row decoders 42.1 to 42.4 are arranged along the longer side of the chip on the side of the central portion of each of memory mats 44.1 to 44.4. Row decoders 42.1-42.4 constitute row decoder 42 of FIG.

Column decoders 43.1 to 43.4 are arranged along the chip short side direction on the chip central portion side of each of memory mats 44.1 to 44.4. The column decoders 43.1 to 43.4 form the column decoder 43 of FIG. The clock generation circuit 38 shown in FIG. 5 and the like are arranged in the peripheral circuit area 49 at the center of the chip.

FIG. 7 shows a memory array MA1 shown in FIG.
6 is a circuit block diagram showing a configuration of No. 6 with some parts omitted. Referring to FIG. 7, memory array MA16 includes a plurality of memory cells MC arranged in rows and columns, a word line WL provided corresponding to each memory cell row, and a word line WL provided corresponding to each memory cell column. Included bit line pair BLP. The memory cell MC includes an access MOS transistor Q and an information storage capacitor C. Word line WL transmits the output of row decoder 42.1 and activates memory cell MC in the selected row. Bit line pair BLP includes bit lines BL and / BL to which complementary signals are transmitted, and inputs / outputs a data signal to / from a selected memory cell MC.

A bit line equalizing circuit 56 for equalizing the bit lines BL, / BL to the bit line potential V _BL (= Vcc / 2) before selecting the memory cell MC is provided at one end of the bit lines BL, / BL. Will be placed. Bit line equalize circuit 56 includes N channel MOS transistors 53 and 54 connected between bit lines BL and / BL and node N51, and an N channel MOS transistor 55 connected between bit lines BL and / BL. including. MOS
The gates of transistors 53 to 55 receive bit line equalize signal BLEQ. Bit line potential V _BL (= Vcc / 2) is applied to node N51. The node N51 is connected to the bit line pair BLP of the adjacent memory array MA15 via the transfer gate 52. Transfer gate 52 includes N channel MOS transistors 50 and 51, and the gates of N channel MOS transistors 50 and 51 both receive signal BLI.

A sense refresh amplifier 61 for amplifying a minute potential difference appearing between bit lines BL and / BL after selecting memory cell MC is arranged between bit lines BL and / BL. Sense refresh amplifier 6
1 denotes N-channel MOS transistors 57 and 5 connected between the bit lines BL and / BL and the node N52, respectively.
8 and P channel MOS transistors 59 and 6 connected between the bit lines BL and / BL and the node N53, respectively.
Including 0 and. The gates of MOS transistors 57 and 59 are both connected to bit line / BL, and the gates of MOS transistors 58 and 60 are both connected to bit line BL. The nodes N52 and N53 are connected to the sense amplifier activation signal / S output from the sense amplifier drive circuit 62, respectively.
Receive E and SE. The sense amplifier drive circuit 62 is included in the clock generation circuit 38 of FIG.

The other ends of the bit lines BL and / BL are connected to the local signal input / output line LIO via the column selection gate 65.
It is connected to one end of L, / LIOL. Column selection gate 65
Includes N channel MOS transistors 63 and 64 connected between bit lines BL and / BL and local signal input / output lines LIOL and / LIOL, respectively. The gates of MOS transistors 63 and 64 are connected to column decoder 43.1 via column select line CSL. The other end of the local signal input / output line pair LIOL is connected to one end of the global signal input / output line pair GIO of FIG. 5 via a block selection switch (not shown). The same applies to the other memory arrays MA1 to MA15.

Next, the operation of the DRAM shown in FIGS. 5 to 7 will be briefly described. In the write operation, the column decoder 4
3 raises the column selection line CSL of the column corresponding to the address signal to the "H" level which is the activation level to make the column selection gate 6
5 is conducted. Further, a block selection switch (not shown) is turned on, and the selected bit line pair BLP is the local signal input / output line pair LIO and the global signal input / output line pair G.
It is connected to the input buffer 47 via IO.

Input buffer 47 receives signal ext. / W in response to the write data from the data signal input / output terminal group 35 via the global signal input / output line pair GIO and the local signal input / output line pair LIO.
Give to P. Write data is given as a potential difference between bit lines BL and / BL. Then, the row decoder 42 raises the word line WL of the row corresponding to the address signal to the "H" level which is the activation level, and turns on the MOS transistor Q of the memory cell MC of the row. The capacitor C of the selected memory cell MC has a bit line pair BL or /
An amount of electric charge according to the potential of BL is stored.

Since the charge of the capacitor C of the memory cell MC gradually flows out, data refresh is performed at a predetermined cycle. FIG. 8 is a time chart showing the refresh operation. Clock generation circuit 38 outputs signal ext. /
Before the fall of RAS, the signal ext. When / CAS is detected to have fallen, a refresh instruction signal / CBR
Is output. Signal ext. In response to the fall of / RAS, signals BLI and BLEQ fall, and MOS transistors 50 and 51 of transfer gate 52 and MOS transistors 53 to 55 of bit line equalize circuit 56 are cut off.

Address generating circuit 41 responds to signal / CBR by generating an address signal Add. Is output. The row decoder 42 receives the address signal Add. The word line WL of the row corresponding to is raised to "H" level. The potentials of the bit lines BL and / BL change by a minute amount according to the charge amount of the capacitor C of the activated memory cell MC.

Then, the sense amplifier drive circuit 62 raises the sense amplifier activation signal SE to "H" level and lowers the sense amplifier activation signal / SE to "L" level to activate the sense refresh amplifier 61. . When the potential of bit line BL is slightly higher than the potential of bit line / BL, the resistance values of MOS transistors 58 and 59 are MO.
As the resistance value of the S transistors 57 and 60 becomes smaller, the potential of the bit line BL is raised to the “H” level and the potential of the bit line / BL is lowered to the “L” level. On the contrary, when the potential of the bit line / BL is slightly higher than the potential of the bit line BL, the MOS transistors 57,
The resistance value of 60 becomes smaller than the resistance values of MOS transistors 58 and 59, and the potential of bit line / BL is raised to the "H" level and the potential of bit line BL is lowered to the "L" level.

Signal ext. When / RAS rises to the inactive level "H" level, the word line WL is lowered to the inactive level "L" level, and the data refresh is completed.

In the read operation, the data in the memory cell MC of the row selected by the row decoder 42 is read to the bit line pair BLP in the same manner as in the refresh operation.
The bit line pair BL of the column selected by the column decoder 43
The data of P is applied to the output buffer 48 via the column selection gate 65, the local signal input / output line pair LIO and the global signal input / output line pair GIO. Output buffer 48
Signal ext. In response to / OE, read data is output to data signal input / output terminal group 35.

By the way, in such a DRAM, the leakage current of the memory cell MC varies between chips, and the cycle in which data refresh is required varies. Therefore, the period required to refresh the data is measured for each chip, and based on the measurement result, each chip is, for example, a 32 ms product or 64 ms product.
It is separated into ms products. 32ms product is a memory cell MC
Each one refers to a chip that needs to refresh data once every 32 ms, and a 64 ms product means a chip that needs to refresh data once every 64 ms per memory cell MC.

The DRAM chip is shipped as a 4K mode product or a 2K mode product according to the needs of the user. The 4K mode product refers to a mode in which only one word line WL is selected in one refresh operation.
The 2K mode product refers to a mode in which two word lines WL are selected in one refresh operation.

The 4K mode is the DR shown in FIGS.
Since the AM has about 4000 word lines WL, it means that the refresh operation is required 4K times if the word lines WL are selected one by one. The 2K mode means that the refresh operation needs to be performed 2K times when selecting two word lines WL each.

Normally, the 32 ms product is set in the 2K mode and shipped as a 2K mode 32 ms product. Also, 64
The ms product is set in the 4K mode and shipped as a 4K mode 64 ms product. The refresh cycle time for performing one refresh operation is 32 ms / 2K = 16 μs in the 2K mode 32 ms product, and the 4K mode 64 ms.
For the product, it is 64 ms / 4K = 16 μs.

FIG. 9 is a circuit block diagram showing a structure of a portion related to the refresh operation of the DRAM shown in FIGS. In the figure, a CBR signal generation circuit 38a
Signal ext. / RAS, ext. A refresh instruction signal / CBR is output in response to / CAS. The CBR signal generation circuit 38a is included in the clock generation circuit 38 of FIG.

Address generation circuit 41 includes a pad 70, a refresh counter 71 and an address switching circuit 72. The pad 70 is bonded to a power line or a ground line (not shown) according to the 4K mode or the 2K mode. The refresh counter 71 uses the signal / C
BR is counted and 12-bit address signals A0 to A1
Outputs 1. The lowest digit of the output of the counter 71 is the signal A.
It becomes 0 and the most significant digit of the output of the counter 71 is the signal A11.
Becomes

The address switching circuit 72 uses the address signal A
Address switching circuit 72a corresponding to 0 to A10 and address switching circuit 72b corresponding to address signal A11 are included. The address switching circuit 72a has address signals A0-A.
Pass 10 as is. Address switching circuit 72b
Is 4K when the pad 70 is bonded to the power line
When the mode is selected, the address signal A11 is passed, the pad 70 is bonded to the ground line, and 2K
When the mode is selected, the passage of the address signal A11 is blocked.

The address switching circuit 40 uses the address signal A
Address switching circuit 40a corresponding to 0 to A10 and address switching circuit 40b corresponding to address signal A11 are included. Address switching circuit 40 applies address signals A0-A11 from row and column address buffer 39 to row decoder 42 during write and read operations, and responds to refresh instructing signal / CBR by address switching circuit 72. .About.A11 or A0 to A10 are applied to the row decoder 42. The row decoder 42 selects one word line WL of the memory array 45 in response to the address signals A0 to A11, and selects two word lines WL of the memory array 45 in response to the address signals A0 to A10. WL
Select

As shown in FIG. 10, the signal A11 indicates that the word lines WL to be selected are the memory arrays MA1 to MA4 and M.
This is a signal for determining which of A5 to MA8 it belongs to. Therefore, in the 4K mode in which the signal A11 is applied, one memory array (for example, MA1) to which the word line WL belongs is determined and one word line WL in the memory array MA1 is selected, but the signal A11 is not applied to the memory array 2K. In the mode, it is not determined which of the two memory arrays (eg MA1 and MA5) the word line WL belongs to, and one word line WL belonging to the memory array MA1 and one word line WL belonging to the memory array MA5.
And are selected at the same time.

[0033]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In M, the refresh cycle time is set to the standard value (16 μ
When the standard value of the long refresh product longer than s) is set, there is a problem that the data disappears when the ability of the chip as the long refresh product is marginal.

On the contrary, the user may set the refresh cycle time unnecessarily shorter than the standard value (16 μs) due to fear of data loss, in which case there is a problem that power consumption becomes large.

Therefore, a main object of the present invention is to provide a semiconductor memory device which can prevent the disappearance of data and the increase of power consumption.

[0036]

A first semiconductor memory device of the present invention is a semiconductor memory device that requires refreshing of data, and includes a memory array including a plurality of memory cells arranged in rows and columns. Of the memory cell selected last time, based on the detection result of the detection means for receiving the refresh instruction signal for instructing It is characterized by further comprising a selection means for selecting a memory cell row different from the row by the number corresponding to the refresh cycle time, and a refresh means for refreshing the data of the memory cell row selected by the selection means.

A second semiconductor memory device of the present invention is a semiconductor memory device that requires refreshing of data, and includes a memory array including a plurality of memory cells arranged in rows and columns, and an instruction for refreshing the data. A refresh instruction signal for comparing the refresh cycle time from the previous input to the current input of the refresh instruction signal with a predetermined time, and the refresh cycle based on the comparison result of the comparing means. In response to the time being shorter than the predetermined time, one memory cell row different from the previously selected memory cell row is selected, and the refresh cycle time is longer than the predetermined time. The selecting means for selecting a plurality of memory cell rows different from the previously selected memory cell row, and the selecting means. It is characterized by comprising a refresh means for refreshing data of the memory cell row selected Te.

Further, the comparing means is reset by the delay means for delaying the refresh instruction signal by a predetermined time and the refresh instruction signal delayed by the delay means, and a predetermined time has elapsed after the reset. Until that time, it outputs a signal of the first level and then outputs a signal of the second level, and a holding means for holding the output level of the time measuring means in response to the refresh instruction signal. The selecting means selects the one memory cell row according to the holding level of the holding means being the first level, and the holding level of the holding means is the second level. Accordingly, the plurality of memory cell rows may be selected.

The selecting means outputs, in response to the refresh instructing signal, a first address signal indicating one memory cell row different from the memory cell row refreshed last time, and the signal generating means. Receiving the first address signal output from the means, and responding to the holding level of the holding means being the second level,
Signal conversion means for converting the first address signal into a second address signal indicating a plurality of memory cell rows different from the previously refreshed memory cell row, and the first or second address output from the signal conversion means Decoding means for receiving a signal and selecting a memory cell row according to the address signal may be included.

[0040]

According to the first semiconductor memory device of the present invention,
The refresh cycle time set by the user is detected by the detecting means, and the number of memory cell rows corresponding to the refresh cycle time is refreshed within one refresh cycle. Therefore, unlike the prior art in which the number of memory cell rows refreshed within one refresh cycle is fixed, data is not lost and power consumption does not increase due to the length of the refresh cycle time.

Further, in the second semiconductor memory device of the present invention, the refresh cycle time set by the user is compared with the predetermined time by the comparing means, and the refresh cycle time is compared with the predetermined time. 1 in 1 refresh cycle due to short
One memory cell row is refreshed, and a plurality of memory cell rows are refreshed within one refresh cycle in response to the refresh cycle time being longer than a predetermined time. Therefore, unlike the prior art in which the number of memory cell rows refreshed within one refresh cycle is fixed, data is not lost and power consumption does not increase due to the length of the refresh cycle time.

Further, the comparing means includes a clocking means which is reset by the delay signal of the refresh instruction signal, and a holding means which holds the output level of the clocking means in response to the refresh instruction signal, and the selecting means is a holding means. If one or more memory cell rows are selected according to the holding level, the comparing means and the selecting means can be easily configured.

The selecting means outputs the first address signal indicating one memory cell row in response to the refresh instruction signal and the first address signal in accordance with the holding level of the holding means. If the signal converting means for converting into the second address signal indicating a plurality of memory cell rows and the decoding means for selecting the memory cell row according to the output of the signal converting means are included, the selecting means can be easily configured. it can.

[0044]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a DRAM according to an embodiment of the present invention.
FIG. 10 is a circuit block diagram showing a configuration of a portion related to the refresh operation of, which is compared with FIG. 9. This D
Regarding the configuration and operation of the other parts of the RAM, the conventional D
The description is omitted because it is the same as the RAM.

Referring to FIG. 1, the address generating circuit 1 of the DRAM differs from the address generating circuit 41 of the conventional DRAM in that a refresh cycle detecting circuit 2 is provided in place of the mode switching pad 70. It is a point. As shown in FIG. 2, refresh cycle detection circuit 2 includes a timer 3, a latch circuit 6 and a delay circuit 7, and timer 3 includes a ring oscillator 4 and a binary counter 5.

The ring oscillator 4 outputs the clock signal CLK having a predetermined cycle (for example, 1 μs) to the input terminal of the binary counter 5. The delay circuit 7 delays the refresh instruction signal / CBR by a predetermined delay time Td and outputs it to the reset terminal of the binary counter 5. Binary counter 5
Is reset by the output of the delay circuit 7, outputs "H" level until the set time Ts elapses after the reset, and then outputs "L" level.

The latch circuit 6 has a refresh instruction signal /
The output Tout of the binary counter 5 is latched in response to CBR. The output S1 of the latch circuit 6 is input to the address switching circuit 72b of FIG. The address switching circuit 72b is
When the signal S1 is at the "H" level, the signal A11 output from the refresh counter 71 is passed,
When 1 is at "L" level, the passage of the signal A11 is blocked.

In FIG. 3, the refresh cycle time Tref set by the user is the set time T of the timer 3.
6 is a time chart showing the operation of the address generation circuit 1 when the sum of s and the delay time Td of the delay circuit 7 is Ts + Td or more.

Signal ext. / RAS, ext. / CAS
In the initial state in which is not yet input, the output Tout of the timer 3 and the output S1 of the latch circuit 6 are both at "L" level, and the 2K mode is selected.

Signal ext. / RAS, ext. / CAS
Refresh instruction signal / C in response to the first input of
When BR falls to the activation level “L” level,
In response to this, the latch circuit 6 latches the output Tout of the timer 3. At this time, since the timer 3 has not been reset yet, the output Tout of the timer 3 remains at the “L” level. Therefore, the output S1 of the latch circuit 6 becomes "L" level and the 2K mode is selected.

After the delay time Td of the delay circuit 7 elapses from the fall of the refresh instruction signal / CBR, the timer 3 is reset and the output Tout of the timer 3 becomes "H" level. The output Tout of the timer 3 becomes the “L” level again after the set time Ts has elapsed.

Then, the signal ext. / RAS, ext.
When the refresh instruction signal / CBR falls to the "L" level in response to the second input of / CAS, the latch circuit 6 latches the output Tout of the timer 3 accordingly. At this time, since the output Tout of the timer 3 has already fallen to the "L" level, the output S1 of the latch circuit 6 remains at the "L" level and the 2K mode is selected again. The same applies thereafter.

FIG. 4 shows the refresh cycle time Tre.
6 is a time chart showing the operation of the address generation circuit 1 when f is less than the sum Ts + Td of the set time Ts and the delay time Td.

Signal ext. / RAS, ext. / CAS
Refresh instruction signal / C in response to the first input of
When BR falls to "L" level, the output S1 of the latch circuit 6 becomes "L" level accordingly, and the delay time Td
The operation is the same as that shown in FIG. 3 until the output Tout of the timer 3 becomes “H” level after the lapse of time.

Then, the signal ext. / RAS, ext.
When the refresh instruction signal / CBR falls to the "L" level in response to the second input of / CAS, the latch circuit 6 latches the output Tout of the timer 3 accordingly. At this time, since the output Tout of the timer 3 has not yet fallen to the "L" level, the output S1 of the latch circuit 6 goes to the "H" level, whereby the 4K mode is selected. The same applies thereafter.

Next, this DRAM is 4K mode 64 ms
The case of a product will be specifically described. 4K mode 6
In the 4 ms product, the delay time Td of the delay circuit 7 is set to 1 μs, for example, and the set time T of the binary counter 5 is set.
s is set to 16 μs which is the standard value of the refresh cycle time Tref of the 4 K mode 64 ms product. However, if the refresh cycle time Tref set by the user is less than 17 μs, it can be sufficiently refreshed even in the 4K mode.

In this case, if the refresh cycle time Tref set by the user is less than 17 μs, the 4K mode is selected and the refresh operation according to the standard is performed. If the refresh cycle time Tref set by the user is 17 μs or more, 2
The K mode is selected, and the refresh ability is improved.

Therefore, in this DRAM, even if the user sets the refresh cycle time Tref longer than the standard value (= 16 μs) in order to gain the writing and reading time, the refresh cycle time Tref is less than 34 μs. For example, the data can be refreshed sufficiently and the data in the memory cell MC is not lost.

Next, this DRAM has a 2K mode of 32 ms.
The case of a product will be specifically described. 2K mode 3
In the 2 ms product, the delay time Td of the delay circuit 7 is set to, for example, 1 μs, and the set time Td of the binary counter 5 is set.
s is 1/2 of the standard value (= 16 μs) of the refresh cycle time Tref of the 2 K mode 32 ms product, which is 8 μs.
Is set to However, if the refresh cycle time Tref set by the user is less than 9 μs, 4
Sufficient refreshing is possible even in K mode.

In this case, 2 if the refresh cycle time Tref set by the user is 9 μs or more.
The K mode is selected, and the standard refresh is performed. If the refresh cycle time Tref set by the user is less than 9 μs, the 4K mode is selected and the power consumption is reduced.

Therefore, in this DRAM, it is possible to prevent an increase in power consumption when the refresh cycle time Tref is set shorter than necessary because the user fears the disappearance of data.

[0062]

As described above, in the first semiconductor memory device of the present invention, the number of memory cell rows corresponding to the refresh cycle time is selected and refreshed. There is no increase in power consumption.

In the second semiconductor memory device of the present invention, one memory cell row is selected and refreshed according to the refresh cycle time being shorter than a predetermined time, and the refresh cycle time is predetermined. A plurality of memory cell rows are selected and refreshed according to the time longer than the given time. Therefore, as in the first semiconductor memory device, the disappearance of data and the increase in power consumption do not occur due to the length of the refresh cycle time.

Further, the comparing means includes a time measuring means which is reset by the delay signal of the refresh instructing signal, and a holding means which holds the output level of the time measuring means in response to the refresh instructing signal, and the selecting means includes the holding means. If one or more memory cell rows are selected according to the holding level, the comparing means and the selecting means can be easily configured.

The selecting means outputs the first address signal indicating one memory cell row in response to the refresh instruction signal, and the first address signal according to the holding level of the holding means. If the signal converting means for converting into the second address signal indicating a plurality of memory cell rows and the decoding means for selecting the memory cell row according to the output of the signal converting means are included, the selecting means can be easily configured. it can.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a configuration of a portion related to a refresh operation of a DRAM according to an embodiment of the present invention.

2 is a circuit block diagram showing a configuration of a refresh cycle detection circuit of the DRAM shown in FIG.

FIG. 3 is a time chart showing the operation of the DRAM shown in FIG.

FIG. 4 is a time chart showing another operation of the DRAM shown in FIG.

FIG. 5 is a circuit block diagram showing a configuration of a conventional DRAM.

FIG. 6 is a diagram showing a chip layout of the DRAM shown in FIG.

7 is a circuit block diagram with a part omitted showing a configuration of a memory array of the DRAM shown in FIG. 6;

FIG. 8 is a time chart showing a refresh operation of the DRAM shown in FIG.

9 is a circuit block diagram showing a configuration of a portion related to a refresh operation of the DRAM shown in FIG.

FIG. 10 is a block diagram for explaining the operation of the circuit shown in FIG.

[Explanation of symbols]

1,43 Address generation circuit, 2 Refresh cycle detection circuit, 3 Timer, 4 Ring oscillator, 5
Binary counter, 6 latch circuits, 7 delay circuits, 30-
32, 34 control signal input terminals, 33 address signal input terminal group, 35 data signal input / output terminal group, 38 clock generating circuit, 38a CBR signal generating circuit, 39 row and column address buffer, 40, 72 address switching circuit, 42 row Decoder, 43 column decoder, 44 memory mat, 45 memory array, 46 sense refresh amplifier + input / output control circuit, 47 input buffer, 4
8 output buffer, 49 peripheral circuit area, 52 transfer gate, 56 bit line equalize circuit, 61 sense refresh amplifier, 62 sense amplifier drive circuit, 65
Column select gate, 70 pads, 71 refresh counter.

Claims (4)

[Claims] 1. A semiconductor memory device requiring data refresh, comprising: a memory array including a plurality of memory cells arranged in rows and columns; a refresh instruction signal for instructing refreshing of the data; A detection unit that detects the refresh cycle time from the input to the current input, based on the detection result of the detection unit, the number of memory cell rows different from the memory cell row selected last time according to the refresh cycle time. 1. A semiconductor memory device comprising: a selecting means for selecting only data and a refreshing means for refreshing data in a memory cell row selected by the selecting means. 2. A semiconductor memory device requiring data refresh, comprising: a memory array including a plurality of memory cells arranged in rows and columns; a refresh instruction signal for instructing refreshing of the data; Comparing means for comparing a refresh cycle time from input to this time with a predetermined time, based on a comparison result of the comparing means, the refresh cycle time is shorter than the predetermined time Accordingly, one memory cell row different from the previously selected memory cell row is selected, and a plurality of memories different from the previously selected memory cell row according to the refresh cycle time being longer than the predetermined time. Selecting means for selecting a cell row, and a memory data row memory cell selected by the selecting means. A semiconductor memory device comprising refreshing means for refreshing. 3. The comparing means is reset by a delay means for delaying the refresh instruction signal by a predetermined time, and a refresh instruction signal delayed by the delay means, and a predetermined time has elapsed after being reset. The first level signal is output until
And a holding means for holding the output level of the time measuring means in response to the refresh instruction signal, wherein the selecting means has a holding level of the holding means.
3. The one memory cell row is selected in response to the second level, and the plurality of memory cell rows are selected in accordance with the holding level of the holding means being the second level. The semiconductor memory device described. 4. The signal generating means, in response to the refresh instructing signal, outputs a first address signal indicating one memory cell row different from the memory cell row refreshed last time, and the signal generating means. A plurality of memory cell rows different from the memory cell row in which the first address signal was refreshed last time, in response to the holding level of the holding means being the second level. A signal converting means for converting into a second address signal indicating a memory cell row, and a decoding for receiving the first or second address signal output from the signal converting means and selecting a memory cell row according to the address signal. The semiconductor memory device according to claim 3, further comprising: