JPH08213531A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH08213531A JPH08213531A JP1568195A JP1568195A JPH08213531A JP H08213531 A JPH08213531 A JP H08213531A JP 1568195 A JP1568195 A JP 1568195A JP 1568195 A JP1568195 A JP 1568195A JP H08213531 A JPH08213531 A JP H08213531A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- substrate
- semiconductor device
- resin
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に係り、特
に、複数の半導体素子を同時に封止する樹脂封止型半導
体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a resin-sealed semiconductor device that simultaneously seals a plurality of semiconductor elements.
【０００２】[0002]
【従来の技術】特開平５−２１８２６２号公報に記載さ
れているように、放熱特性を向上するために半導体素子
を搭載するタブに放熱リードを設け、その放熱リードは
半導体装置の各コーナ部から外部へ突出させ、アウター
リードの形状より大きくした構造になっている。2. Description of the Related Art As described in Japanese Patent Laid-Open No. 5-218262, a heat radiation lead is provided on a tab on which a semiconductor element is mounted in order to improve heat radiation characteristics, and the heat radiation lead is provided from each corner of a semiconductor device. The structure is such that it protrudes to the outside and is larger than the shape of the outer lead.
【０００３】また、特開昭６１−３００６７号公報に記
載されている従来の技術は、リードフレームのタブ上に
配線基板を搭載し、その配線基板に複数の半導体素子を
搭載し、配線基板とインナーリード、半導体素子と配線
基板とをワイヤで接続したものであって、タブあるいは
配線基板の少なくとも一方に外付け用チップ部品を収納
するための貫通孔を形成した構造になっている。In the conventional technique disclosed in Japanese Patent Laid-Open No. 61-30067, a wiring board is mounted on a tab of a lead frame, and a plurality of semiconductor elements are mounted on the wiring board. An inner lead, a semiconductor element, and a wiring board are connected by wires, and a through hole for accommodating an external chip component is formed in at least one of the tab and the wiring board.
【０００４】さらに、特開平２−１５６５５９号公報に
記載されている従来の技術は、半導体素子を搭載するタ
ブの代用品としてインナーリードを長く伸ばし、その上
に配線基板を搭載し、その配線基板の上に半導体素子を
搭載する構造になっている。Further, in the conventional technique disclosed in Japanese Patent Laid-Open No. 2-156559, the inner lead is extended as a substitute for a tab on which a semiconductor element is mounted, a wiring board is mounted on the inner lead, and the wiring board is mounted on the inner lead. It has a structure in which a semiconductor element is mounted on.
【０００５】[0005]
【発明が解決しようとする課題】特開平５−２１８２６
２号公報に記載されている半導体装置は、放熱特性を向
上するために実装時に基板へ電気的に接続するアウター
リードと放熱リードを異なる形状にしているので、製造
過程のリード切断、リード折り曲げ工程の際、ＥＩＡＪ
（日本電子機械工業会）規格の放熱リードなしの同サイ
ズの半導体装置の金型が使用できず、専用に金型を製作
するためにコストがかかるという問題があった。[Patent Document 1] Japanese Unexamined Patent Publication No. 5-21826
In the semiconductor device described in Japanese Patent Laid-Open No. 2 publication, the outer lead and the heat radiating lead, which are electrically connected to the substrate at the time of mounting, have different shapes in order to improve the heat radiating characteristic. At the time of EIAJ
(Electronic Machinery Manufacturers Association of Japan) There is a problem that a mold of a semiconductor device of the same size without a heat dissipation lead of the standard cannot be used, and it is costly to manufacture a mold for exclusive use.
【０００６】また、特開昭６１−３００６７号公報に記
載されている半導体装置は、放熱特性について考慮され
ていないため、放熱特性が劣るという問題があった。Further, the semiconductor device described in Japanese Patent Laid-Open No. 61-30067 has a problem that the heat dissipation characteristic is inferior because the heat dissipation characteristic is not taken into consideration.
【０００７】さらに、特開平２−１５６５５９号公報に
記載されている従来の技術は、タブの代用品としてイン
ナーリードを長くすることによって構成し配線基板を搭
載する構造になっているので、半導体素子は配線基板の
片面にしか搭載できず実装密度を高めることができない
という問題があった。Further, the conventional technique disclosed in Japanese Patent Laid-Open No. 2-156559 has a structure in which an inner lead is formed as a substitute for a tab so as to mount a wiring board on the semiconductor element. However, there is a problem in that the mounting density cannot be increased because it can be mounted on only one surface of the wiring board.
【０００８】本発明の目的は、半導体装置において、放
熱特性を向上できる構造を提供することにある。An object of the present invention is to provide a structure capable of improving heat dissipation characteristics in a semiconductor device.
【０００９】本発明の他の目的は、半導体装置におい
て、製造過程のリード切断、リード折り曲げ工程の際、
ＥＩＡＪ（日本電子機械工業会）規格の放熱リードなし
の同サイズの半導体装置の金型が使用することが可能な
技術を提供することにある。Another object of the present invention is to provide a semiconductor device, which includes a step of cutting a lead and a step of bending a lead in a manufacturing process.
An object of the present invention is to provide a technique that can be used by a mold of a semiconductor device of the same size without a heat dissipation lead of EIAJ (Japan Electronic Machinery Manufacturers Association) standard.
【００１０】本発明の他の目的は、半導体装置におい
て、半導体装置内の配線基板の半導体素子の搭載可能面
積の向上させることが可能な技術を提供することにあ
る。Another object of the present invention is to provide a technique capable of improving a mountable area of a semiconductor element of a wiring board in the semiconductor device in the semiconductor device.
【００１１】[0011]
【課題を解決するための手段】上記目的を達成するため
に、電気的に配線された基板を枠状に形成されたリード
フレームのタブに搭載し、前記基板には半導体素子を搭
載し、インナーリードと基板、基板と半導体素子をそれ
ぞれワイヤにより接続し、樹脂によってモールドされて
いる半導体装置において、タブから半導体装置の各辺の
端へ放熱リードを設け、樹脂の外側に出ている放熱リー
ドの形状はアウターリードと同形状にしたものである。In order to achieve the above object, an electrically wired substrate is mounted on a tab of a lead frame formed in a frame shape, a semiconductor element is mounted on the substrate, and In the semiconductor device in which the lead and the substrate, and the substrate and the semiconductor element are respectively connected by wires, and which is molded with resin, the heat dissipation lead is provided from the tab to the end of each side of the semiconductor device and The shape is the same as the outer lead.
【００１２】また、上記目的を達成するために、電気的
に配線された基板をインナーリードに搭載し、前記基板
には半導体素子を搭載し、インナーリードと基板、基板
と半導体素子をそれぞれワイヤにより接続し樹脂によっ
てモールドされている半導体装置において、前記基板を
搭載するインナーリードは基板の両面に半導体素子など
を搭載できるように必要最小限の長さにしたものであ
る。In order to achieve the above object, an electrically wired substrate is mounted on an inner lead, a semiconductor element is mounted on the substrate, and the inner lead and the substrate, and the substrate and the semiconductor element are respectively connected by wires. In a semiconductor device that is connected and molded with resin, the inner leads for mounting the substrate have a minimum required length so that semiconductor elements and the like can be mounted on both surfaces of the substrate.
【００１３】[0013]
【作用】電気的に配線された基板を枠状に形成されたリ
ードフレームのタブに搭載し、タブから半導体装置の各
辺の端へ放熱リードを設けることにより、半導体素子か
ら発生する熱は、基板、タブ、放熱リードを経て外部へ
逃げやすくなり、もしくは、基板の両面に半導体素子な
どを搭載できる必要最小限の長さにしたインナーリード
に基板を搭載することにより、半導体素子から発生する
熱は、基板、インナーリード、アウターリードの経路で
外部へ逃げやすくなるので放熱特性が向上する。By mounting the electrically wired substrate on the tab of the lead frame formed in a frame shape and providing the heat radiation lead from the tab to the end of each side of the semiconductor device, the heat generated from the semiconductor element is It is easy to escape to the outside through the board, tabs, and heat dissipation leads, or heat generated from the semiconductor element by mounting the board on the inner leads with the minimum required length that allows semiconductor elements to be mounted on both sides of the board. Since it is easy to escape to the outside through the route of the substrate, the inner lead and the outer lead, the heat dissipation characteristics are improved.
【００１４】また、樹脂の外側に出ている放熱リードの
形状はアウターリードと同形状にしたので製造過程のリ
ード切断、リード折り曲げ工程の際、ＥＩＡＪ（日本電
子機械工業会）規格の放熱リードなしの同サイズの半導
体装置の金型が使用することが可能になる。Further, since the shape of the heat radiation lead protruding outside the resin is the same as that of the outer lead, there is no heat radiation lead of EIAJ (Japan Electronic Machinery Manufacturers Association) standard during lead cutting and lead bending processes in the manufacturing process. The same size semiconductor device mold can be used.
【００１５】さらに、タブを枠状、もしくは、インナー
リードを基板を搭載できる必要最小限の長さにしてある
ので基板の両面に半導体素子などを搭載することがで
き、実装密度の向上が図れる。Further, since the tabs are frame-shaped or the inner leads are formed to have the minimum necessary length for mounting the board, semiconductor elements or the like can be mounted on both surfaces of the board, and the mounting density can be improved.
【００１６】[0016]
【実施例】以下、本発明の実施例を図面に基づいて説明
する。Embodiments of the present invention will be described below with reference to the drawings.
【００１７】図１は、本発明の第一の実施例の半導体装
置の平面図を示す。電気的に配線されている基板１は、
枠状に形成されているタブ２に搭載され、基板１には半
導体素子３が搭載されモールド樹脂４で封止されてい
る。また、外部のプリント基板（図示せず）などに接続
するアウターリード５（樹脂の外側）とインナーリード
６（樹脂の内側）があり、半導体素子３と基板１、基板
１とインナーリード５は、ワイヤ７により接続されてい
る。さらに、タブ２には樹脂４外形の各辺の端に向けて
放熱リード８が構成されている。放熱リード８の樹脂４
の外側に出ている形状は、アウターリード６と同形状に
形成されている。そして、放熱リード８の分岐している
部分にはタブを下げるための逃げ孔９が形成されてい
る。FIG. 1 is a plan view of a semiconductor device according to the first embodiment of the present invention. The electrically wired substrate 1 is
It is mounted on a tab 2 formed in a frame shape, a semiconductor element 3 is mounted on a substrate 1, and is sealed with a mold resin 4. Further, there are an outer lead 5 (outer side of the resin) and an inner lead 6 (inner side of the resin) which are connected to an external printed circuit board (not shown) or the like, and the semiconductor element 3 and the board 1, the board 1 and the inner lead 5 are It is connected by a wire 7. Further, on the tab 2, heat dissipation leads 8 are formed toward the ends of each side of the outer shape of the resin 4. Resin 4 for heat dissipation lead 8
The shape of the outer lead 6 is the same as that of the outer lead 6. An escape hole 9 for lowering the tab is formed in the branched portion of the heat dissipation lead 8.
【００１８】図２は、本発明の第１の実施例の半導体装
置の図１のＡ−Ａ矢視断面図を示す。タブ２は、基板１
を半導体装置の断面方向のほぼ中心に設置されるように
インナーリード５の位置より下げた位置に構成され、基
板１の両面には半導体素子３が搭載されている。FIG. 2 is a sectional view of the semiconductor device of the first embodiment of the present invention taken along the line AA of FIG. Tab 2 is substrate 1
Is arranged at a position lower than the position of the inner lead 5 so as to be installed substantially at the center in the cross-sectional direction of the semiconductor device, and the semiconductor element 3 is mounted on both surfaces of the substrate 1.
【００１９】本発明によれば、半導体素子から発生した
熱は、基板、タブ、放熱リードと半導体装置の外に逃げ
やすくなっているので放熱特性が向上する効果がある。
また、この半導体装置は、ゲートがコーナ部にあり、ゲ
ートから離れた位置からワイヤがボンディングされてい
るので樹脂注入時のワイヤ曲がりを低減できる効果があ
る。さらに、樹脂の外側に出ている放熱リードの形状は
アウターリードと相似なので製造過程のリード切断、リ
ード折り曲げ工程の際、ＥＩＡＪ（日本電子機械工業
会）規格の放熱リードなしの同サイズの半導体装置の金
型が使用することができ金型コストを低減できる効果が
ある。さらに、基板の両面に半導体素子などを搭載する
ことができるので実装密度を向上させることができる効
果がある。さらに、基板を半導体装置の断面方向のほぼ
中心に設置されているので樹脂注入時に樹脂は基板上下
をほぼ同時に流れるので成形不良の低減が図れる。According to the present invention, the heat generated from the semiconductor element can easily escape to the outside of the substrate, the tabs, the heat radiation leads and the semiconductor device, so that the heat radiation characteristic is improved.
Further, in this semiconductor device, since the gate is at the corner portion and the wire is bonded from a position away from the gate, there is an effect that the wire bending at the time of resin injection can be reduced. Furthermore, since the shape of the heat dissipation lead exposed on the outside of the resin is similar to that of the outer lead, a semiconductor device of the same size without heat dissipation lead of EIAJ (Japan Electronic Machinery Manufacturers Association) standard at the time of lead cutting and lead bending process in the manufacturing process. The mold can be used and there is an effect that the mold cost can be reduced. Furthermore, since semiconductor elements and the like can be mounted on both sides of the substrate, there is an effect that the mounting density can be improved. Further, since the substrate is installed substantially at the center in the cross-sectional direction of the semiconductor device, the resin flows almost simultaneously at the top and bottom of the substrate when the resin is injected, so that molding defects can be reduced.
【００２０】本発明において、アウターリード２４本分
を放熱リードとして構成している半導体装置で説明した
が、この本数を増加させれば放熱特性はより向上する。In the present invention, the description has been given of the semiconductor device in which the 24 outer leads are constituted as the heat radiation leads. However, if the number of the outer leads is increased, the heat radiation characteristic is further improved.
【００２１】図３は、本発明の第２の実施例の半導体装
置の平面図を示す。電気的に配線されている基板１は、
インナーリード５に搭載され基板１には半導体素子３が
搭載されてモールド樹脂４で封止されている。FIG. 3 is a plan view of a semiconductor device according to the second embodiment of the present invention. The electrically wired substrate 1 is
The semiconductor element 3 is mounted on the inner lead 5 and mounted on the substrate 1 and is sealed with the molding resin 4.
【００２２】図２は、本発明の第２の実施例の半導体装
置の図１のＡ−Ａ矢視断面図を示す。インナーリード５
の基板１が搭載される部分は、基板１を半導体装置の断
面方向のほぼ中心に設置されるようにアウターリード６
の位置より下げた位置に構成され、基板１の両面には半
導体素子３が搭載されている。FIG. 2 is a sectional view of the semiconductor device according to the second embodiment of the present invention taken along the line AA of FIG. Inner lead 5
The portion on which the substrate 1 is mounted has outer leads 6 so that the substrate 1 is placed substantially at the center in the cross-sectional direction of the semiconductor device.
The semiconductor element 3 is mounted on both surfaces of the substrate 1 at a position lower than the position.
【００２３】本発明によれば、半導体素子から発生した
熱は、インナーリード、アウターリードと半導体装置の
外に逃げやすくなっているので第１の実施例に比べ放熱
特性が向上する効果がある。また、樹脂の外側に出てい
る放熱リードの形状はアウターリードと相似なので製造
過程のリード切断、リード折り曲げ工程の際、ＥＩＡＪ
（日本電子機械工業会）規格の放熱リードなしの同サイ
ズの半導体装置の金型が使用することができ金型コスト
を低減できる効果がある。さらに、基板の両面に半導体
素子などを搭載することができるので実装密度を向上さ
せることができる。さらに、基板を半導体装置の断面方
向のほぼ中心に設置されているので樹脂注入時に樹脂は
基板上下をほぼ同時に流れるので成形不良の低減が図れ
る。According to the present invention, the heat generated from the semiconductor element is easily released to the outside of the inner lead, the outer lead and the semiconductor device, so that the heat radiation characteristic is improved as compared with the first embodiment. In addition, the shape of the heat dissipation lead exposed outside the resin is similar to the outer lead, so EIAJ is used during the lead cutting and lead bending process in the manufacturing process.
(Japan Electronic Machinery Manufacturers Association) A mold of a semiconductor device of the same size without a standard heat radiation lead can be used, which has the effect of reducing the mold cost. Further, since semiconductor elements and the like can be mounted on both sides of the substrate, the mounting density can be improved. Further, since the substrate is installed substantially at the center in the cross-sectional direction of the semiconductor device, the resin flows almost simultaneously at the top and bottom of the substrate when the resin is injected, so that molding defects can be reduced.
【００２４】本発明において、基板に搭載されている部
品として半導体素子で説明したが、基板に半導体素子と
チップ部品を混在して搭載しても同じ効果がある。In the present invention, the semiconductor element has been described as the component mounted on the substrate, but the same effect can be obtained even if the semiconductor element and the chip component are mixedly mounted on the substrate.
【００２５】[0025]
【発明の効果】本発明によれば基板を放熱リード付きタ
ブやインナーリードに搭載することにより放熱特性を向
上させることができる。また、外形をＥＩＡＪ（日本電
子機械工業会）規格の放熱リードなしの半導体装置と同
サイズにすることにより金型コストの低減を図れる。さ
らに、基板を断面方向のほぼ中心に設置されているので
樹脂注入時に樹脂は基板上下をほぼ同時に流れ成形不良
の低減が図れる。さらに、基板の両面に半導体素子など
を搭載することができるので実装密度を向上させること
ができる。According to the present invention, the heat radiation characteristic can be improved by mounting the substrate on the tab with the heat radiation lead or the inner lead. Also, the cost of the mold can be reduced by making the outer shape the same size as the semiconductor device without the heat dissipation lead of the EIAJ (Japan Electronic Machinery Manufacturers Association) standard. Further, since the substrate is installed substantially at the center in the cross-sectional direction, the resin flows at the top and bottom of the substrate almost at the same time when the resin is injected, so that defective molding can be reduced. Further, since semiconductor elements and the like can be mounted on both sides of the substrate, the mounting density can be improved.
【図１】本発明の第１の実施例の半導体装置の平面図。FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention.
【図２】図１のＡ−Ａ矢視断面図。FIG. 2 is a sectional view taken along the line AA of FIG.
【図３】本発明の第２の実施例の半導体装置の平面図。FIG. 3 is a plan view of a semiconductor device according to a second embodiment of the present invention.
【図４】図３のＡ−Ａ矢視断面図。FIG. 4 is a sectional view taken along the line AA of FIG. 3;
１…基板、 ２…タブ、 ５…インナーリード、 ６…アウターリード、 ８…放熱リード。 1 ... Board, 2 ... Tab, 5 ... Inner lead, 6 ... Outer lead, 8 ... Heat dissipation lead.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 遠藤 恒雄 東京都小平市上水本町五丁目20番１号株式 会社日立製作所半導体事業部内 (72)発明者 土橋 芳男 東京都小平市上水本町五丁目20番１号株式 会社日立製作所半導体事業部内 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Tsuneo Endo 5-20-1 Kamimizumoto-cho, Kodaira-shi, Tokyo Inside Hitachi Semiconductor Business Division (72) Inventor Yoshio Dobashi 5-chome, Mizumizumoto-cho, Kodaira, Tokyo No. 20 No. 1 Stock Company Hitachi Semiconductor Business Division
Claims (3)
に搭載されている半導体素子と、前記基板が搭載されて
いるタブと、前記基板と電気的にワイヤで接続されたイ
ンナーリードと、前記タブから伸びる放熱リードと前記
ワイヤを樹脂で封止する半導体装置において、前記半導
体装置の各辺の端からアウターリードに平行して設けら
れた放熱リードを有することを特徴とする半導体装置。1. A substrate electrically connected, a semiconductor element mounted on the substrate, a tab on which the substrate is mounted, and an inner lead electrically connected to the substrate by a wire. A semiconductor device in which a heat dissipation lead extending from the tab and the wire are sealed with a resin, the heat dissipation lead being provided in parallel with the outer lead from the end of each side of the semiconductor device.
に搭載されている半導体素子と、前記基板と電気的にワ
イヤで接続されたインナーリードと前記ワイヤを樹脂で
封止する半導体装置において、前記インナーリード上に
接着部材を介して前記基板を設置したことを特徴とする
半導体装置。2. A semiconductor device in which a substrate electrically wired, a semiconductor element mounted on the substrate, inner leads electrically connected to the substrate by a wire, and the wire are sealed with a resin. The semiconductor device according to claim 1, wherein the substrate is placed on the inner lead via an adhesive member.
いない部分の形状を前記アウターリードと同形状にした
半導体装置。3. The semiconductor device according to claim 1, wherein the shape of the portion not sealed with the resin is the same as that of the outer lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1568195A JPH08213531A (en) | 1995-02-02 | 1995-02-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1568195A JPH08213531A (en) | 1995-02-02 | 1995-02-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08213531A true JPH08213531A (en) | 1996-08-20 |
Family
ID=11895502
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1568195A Pending JPH08213531A (en) | 1995-02-02 | 1995-02-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08213531A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7304370B2 (en) | 2004-01-14 | 2007-12-04 | Denso Corporation | Electronic device having wiring substrate and lead frame |
-
1995
- 1995-02-02 JP JP1568195A patent/JPH08213531A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7304370B2 (en) | 2004-01-14 | 2007-12-04 | Denso Corporation | Electronic device having wiring substrate and lead frame |
| US7612434B2 (en) | 2004-01-14 | 2009-11-03 | Denso Corporation | Electronic device having wiring substrate and lead frame |
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