JPH08204768A - Digital signal transmitter and receiver - Google Patents

Abstract

PURPOSE: To prevent rapid quality deterioration owing to deteriorated reception state by applying error correction coding with high correction capability in the order of priority and correcting a bit string with a specific pattern so as to allow a receiver side to specify a signal series without deterioration. CONSTITUTION: Signal series 1, 2, 3 corresponding to low, medium, high band frequency component signals in a digital video signal are subjected to error correction coding by convolution coding circuits 3, 4, 5 whose coding rates are respectively 1/2, 3/4, 7/8 to enhance error immunity capability toward signal series with higher priority. Furthermore, specific bit string insert circuits 6,7 insert a bit string of a specific pattern and a multiplexer 2 provides the output of one series multiplexed digital data. Thus, the receiver side compares a specific pattern with a reception signal pattern to measure a bit error rate thereby specifying and selecting a signal series not deteriorated in a short time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal transmitter and receiver for receiving a digital signal such as a digital video signal and the like, even if the C / N ratio (carrier power to noise power ratio) is deteriorated. The present invention relates to a digital signal transmitting apparatus and a receiving apparatus in which the quality or the received image quality is less likely to deteriorate rapidly.

[0002]

2. Description of the Related Art FIG. 6 is shown in, for example, Yasuda et al., "Theoretical Bit Error Rate Characteristic of Soft-decision Viterbi Decoding" (Technical Report of IEICE, CS 80-126, Vol.80 No.122, 1980). FIG. 1 is a block diagram showing a digital transmission system using a conventional digital signal transmitting device and receiving device, in which FIG.
Reference numeral 01 is an error correction code circuit, 102 is a digital modulation circuit, 103 is a digital demodulation circuit, and 104 is an error correction decoding circuit.

Next, the operation will be described. FIG. 6 shows a transmission system that is provided with an error correction code circuit before modulating a digital signal, and is demodulated and decoded on the receiving side so as to be strong against an error due to noise received on a transmission line or the like. However, the error correction code circuit 101 uses an error correction code having one kind of error correction capability for all input data, and 104 is 10
It is an error correction decoding circuit having one type of error correction decoding capability according to 1.

It should be noted that in the above document, a convolutional encoder is used as the error correction coding circuit and a Viterbi decoder is used as the error correction decoding circuit.

[0005]

Since the conventional digital signal transmitting apparatus and receiving apparatus are configured as described above, when digitally transmitting a video signal or the like, for example, the reception C / N is deteriorated and a certain threshold is given. There is a problem peculiar to the digital transmission system in that the image quality sharply deteriorates when the value exceeds the value. This is shown in FIG.

The present invention has been made to solve the above problems, and provides a digital signal transmitting apparatus and a receiving apparatus in which a received image does not suddenly deteriorate even when the receiving C / N deteriorates. The purpose is to

[0007]

A digital signal transmitting apparatus according to claim 1 of the present invention is a digital signal transmitting apparatus for digitally transmitting a plurality of signal sequences, wherein all or a part of the plurality of signal sequences are provided. On the other hand, a means for performing error correction coding with different correction capabilities, a means for performing error correction coding and then multiplexing, a means for digitally modulating the multiplexed signal sequence, and a method for performing error correction coding and then specifying It has a means for adding a bit string having the pattern.

A digital signal transmitting apparatus according to a second aspect of the present invention is the digital signal transmitting apparatus according to the first aspect, further comprising means for adding a bit string having a specific pattern after multiplexing. I have.

A digital signal receiving apparatus according to a third aspect of the present invention is a digital signal receiving apparatus for receiving a digital signal in which a plurality of signal sequences are multiplexed,
Means for demodulating a digital signal, means for separating a demodulated signal, means for performing error correction decoding with different correction capabilities on all or part of the separated signal sequence, and bit error rate before performing error correction decoding And a means for selecting a signal sequence to be output by utilizing the bit error rate.

Further, a digital signal receiving apparatus according to a fourth aspect of the present invention is the digital signal receiving apparatus according to the third aspect, having means for measuring a bit error rate before separating the demodulated signal. .

[0011]

In the digital signal transmitting apparatus according to the first aspect of the present invention, an error correcting code having a different correction capability is applied to all or part of a plurality of signal sequences, and the digital signal is generated after multiplexing to generate a transmission signal. In order to do so, a transmission signal to which an error correction code having a high priority of the signal sequence and a high error correction capability is applied is generated.

Further, since the bit string having a specific pattern is added after the error correction coding, the bit string having the specific pattern is used on the receiving side before the error correction decoding is performed. Can be measured.

Further, in the digital signal transmitting apparatus according to the second aspect of the present invention, since each signal series is multiplexed and a bit string having a specific pattern is added, the number of specific bit string inserting circuits is reduced and the transmitting apparatus is sufficient. The circuit configuration of can be simplified.

In the digital signal receiving apparatus according to the third aspect of the present invention, after demodulating the received signal and separating the demodulated signal, the bit error rate ( BER) is measured, then error correction decoding with different correction capabilities is performed, and a signal sequence that is not deteriorated is output using the BER, so that the received signal does not deteriorate rapidly even if the received C / N decreases. .

Furthermore, since the bit error rate is measured before the error correction decoding, the degree of deterioration of each signal sequence can be specified in a short time.

Further, in the digital signal receiving apparatus according to the fourth aspect of the present invention, since the bit error rate is measured before the separation, the number of bit error rate measuring circuits is small and the circuit configuration of the receiving apparatus can be simplified.

[0017]

【Example】

Example 1. First Embodiment FIG. 1 is a block diagram showing a transmitting device according to a first embodiment of the present invention. In the figure, the signal sequence 1, the signal sequence 2, and the signal sequence 3 have higher priority in this order. 3 is a convolutional code circuit having a constraint length of 7 and a coding rate of 1/2 as an error correction code circuit for the signal sequence 1, 4 is a constraint length of 7 and a coding rate of 3 /
4 is a convolutional code circuit with a constraint length of 7 and a coding rate of 7/8 (however, the coding rates of 3/4 and 7/8 are puncturing with a coding rate of 1/2). Chad code),
Reference numeral 2 is a multiplexer for time-division multiplexing these three types of signals, and 1 is a QPSK modulation circuit for digital modulation.

Further, 6 and 7 are bit error rates (B
This is a specific bit string insertion circuit for inserting a specific bit string in order to measure ER).

Next, the operation will be described. Signal sequence 1,
The signal series 2 and the signal series 3 have different priorities, and are digital data corresponding to, for example, a low frequency component signal, a middle frequency component signal, and a high frequency signal of a digital video signal. These signal sequences are, in order of priority, the convolutional coding circuit 3 having a coding rate of 1/2 and the coding rate of 3 /
The error correction coding is performed by the convolutional coding circuit 4 of 4 and the convolutional coding circuit 5 of the coding rate 7/8. A convolutional code with a coding rate of 1/2 outputs 2 bits of output data that is error correction coded for 1 bit of input data. Similarly, a convolutional code with a coding rate of 3/4 outputs 4 bits for an input of 3 bits, and a convolutional code with a coding rate of 7/8 outputs 8 bits for an input of 7 bits. The smaller the coding rate, the larger the redundancy for error correction, and the higher the error correction capability. In this way, since the higher priority signal sequence is subjected to convolutional coding with higher error correction capability, the higher priority signal sequence has higher error resilience capability. In order to measure the bit error rate (BER) before error correction decoding on the receiving side, after applying an error correction code, the specific bit string insertion circuits 6 and 7 insert a bit string having a specific pattern. On the receiving side, the BER can be measured by comparing this specific pattern with the pattern obtained from the signal actually received via the transmission path. Then, the multiplexer 2 time-division-multiplexes the error-correction-coded signal sequence as described above. That is, the outputs of the above three encoders are input in parallel to the multiplexer 2, but these signals are rearranged using a memory or the like and output in series. Therefore, the output of the multiplexer 2 is a continuous series of digital data. Then, this multiplexed signal is modulated by the QPSK modulation circuit 1 and output as a transmission wave to the transmission line. Here, the transmission line is, for example, a satellite line or the like, and in general, disturbance such as noise is added to the transmitted wave.

The patterns generated by the specific bit string insertion circuits 6 and 7 may be the same or different.

Further, the bit string pattern generated by the specific bit string inserting circuits 6 and 7 is not limited, but a random sequence having no correlation such as a PN sequence can be considered.

Example 2. FIG. 2 is a block diagram showing a transmitting device according to the second embodiment of the present invention. In the figure, the signal sequence 1, the signal sequence 2, and the signal sequence 3 have higher priority in this order.
3 is a constraint length 7 as an error correction code circuit for the signal sequence 1, a convolutional code circuit with a coding rate of 1/2, 4 is a constraint length 7,
A convolutional code circuit with a coding rate of 3/4, a constraint length 7 and a convolutional code circuit with a coding rate of 7/8 (however, coding rate 3/4,
The 7/8 convolutional code is a punctured code with a coding rate of 1/2), 2 is a multiplexer for time division multiplexing these three types of signals, and 1 is a QPS for digital modulation.
It is a K modulation circuit.

Further, 8 is a bit error rate (BE
A specific pattern insertion circuit for inserting a bit string having a specific pattern in order to measure R).

Next, the operation will be described. Signal sequence 1,
The signal series 2 and the signal series 3 have different priorities, and are digital data corresponding to, for example, a low frequency component signal, a middle frequency component signal, and a high frequency signal of a digital video signal. These signal sequences are, in order of priority, the convolutional coding circuit 3 having a coding rate of 1/2 and the coding rate of 3 /
The error correction coding is performed by the convolutional coding circuit 4 of 4 and the convolutional coding circuit 5 of the coding rate 7/8. A convolutional code with a coding rate of 1/2 outputs 2 bits of output data that is error correction coded for 1 bit of input data. Similarly, a convolutional code with a coding rate of 3/4 outputs 4 bits for an input of 3 bits, and a convolutional code with a coding rate of 7/8 outputs 8 bits for an input of 7 bits. The smaller the coding rate, the larger the redundancy for error correction, and the higher the error correction capability. In this way, since the higher priority signal sequence is subjected to convolutional coding with higher error correction capability, the higher priority signal sequence has higher error resilience capability. Next, the multiplexer 2 time-division-multiplexes the error-correction-coded signal sequence as described above. That is, although the outputs of the above three encoders are input in parallel to the multiplexer 2, these signals are rearranged using a memory or the like and output in series. Therefore, the output of the multiplexer 2 is a continuous series of digital data. After multiplexing, in order to measure the bit error rate (BER) before error correction and decoding on the receiving side, a bit string having a specific pattern is inserted by the specific bit string insertion circuit 8. At the receiving side, this specific pattern is compared with the pattern obtained from the signal actually received via the transmission line, to thereby obtain the BER.
Can be measured. Then, the multiplexed signal is modulated by the QPSK modulation circuit 1 and output to the transmission line as a transmission wave. Here, the transmission line is, for example, a satellite line or the like, and in general, disturbance such as noise is added to the transmitted wave.

The pattern of the bit string generated by the specific bit string inserting circuit in this embodiment is not limited, but a random sequence having no correlation such as a PN sequence can be considered.

Example 3. Third Embodiment FIG. 3 is a block diagram showing a receiving device according to a third embodiment of the present invention. In the figure, 10
Is a QPSK demodulation circuit for digitally demodulating the received signal, 11 is a demultiplexer for separating the multiplexed signal, 12 and 13 are BER measurement circuits for measuring the bit error rate of the separated signal sequence, 14, Reference numerals 15 and 16 respectively denote a Viterbi decoding circuit that decodes a convolutional code having a coding rate of 1/2 and an Viterbi decoding circuit that decodes a convolutional code having a coding rate of 3/4, which are error correction codes performed on the transmission side. , A Viterbi decoding circuit for decoding a convolutional code with a coding rate of 7/8, 1
Reference numerals 7 and 18 are switches for selecting an output signal by using the error rates from the BER measuring circuits 12 and 13, respectively.

Next, the operation will be described. The digital signal in which a plurality of signal sequences are multiplexed is demodulated by the QPSK demodulation circuit 10 after being affected by noise or the like on the transmission line or the like. The demodulated one-series digital signal is separated by the demultiplexer 11. Separated signal sequence 2,
After the error rate of 3 is measured by the error rate measuring circuits 12 and 13, the separated signals are error correction decoded by the Viterbi decoding circuits 14, 15 and 16 having different error correction capabilities. Based on the bit error rates of the signal series 2 and 3 measured by the BER measuring circuit, the switch SW17,
18 is operated to output only the series determined to have no deterioration such as BER of 10 ⁻⁵ or less. For example,
It is assumed that the signal series 1, 2, and 3 have a higher priority in this order, such as a low frequency signal, a middle frequency signal, and a high frequency signal of a video signal. Since signals with higher priority are subjected to error correction decoding with higher correction capability, they are less susceptible to noise.
Therefore, even if the reception C / N is deteriorated, the signal series 1, the signal series 2, and the signal series 3 are not deteriorated at the same time, and the signal series with lower priority are gradually deteriorated. FIG. 4 shows the relationship between the received C / N and the bit error rate for each signal sequence. When a video signal is received, all the signal sequences do not deteriorate rapidly, but the deterioration starts from the high-frequency component signal of low priority, and then gradually deteriorates in the order of the middle-frequency component signal and the low-frequency component signal. Therefore, it is possible to prevent a sharp deterioration of the received image.

Further, since the error rate measuring circuit is provided before the error correcting circuit, the error rate can be measured in a short time and the deterioration degree of each signal sequence can be specified in a short time. The reason for this will be explained. From the correction capability of error correction decoding, the error rate after error correction, which is an index indicating the degree of deterioration of the received signal, can be known from the bit error rate before error correction. And
Since the bit error rate before error correction is larger, the time required to measure the bit error rate can be shorter than the time required to measure the bit error rate after error correction.

Note that it is necessary to previously insert a bit string having a specific pattern for measuring the bit error rate into the signal sequence on the transmitting side. Then, the pattern is also stored on the receiving side, and the BER is measured by comparing this pattern with the pattern of the signal which is actually received through the transmission line and is affected by noise.

On the transmitting side, the coding rates of 1/2 and 3 / are assigned to the signal sequences corresponding to the signal sequences 1, 2, and 3, respectively.
It goes without saying that convolutional codes of 4 and 7/8 are applied.

Example 4. FIG. 5 is a block diagram showing a receiving device according to the fourth embodiment of the present invention. In the figure, 10
Is a QPSK demodulation circuit for digitally demodulating the received signal, 19 is a BER measurement circuit for measuring the bit error rate of the demodulated signal sequence, 11 is a demultiplexer for separating the multiplexed signal, 14, 15, 16 is the coding rate 1 / which is an error correction code applied on the transmission side.
Viterbi decoding circuit for decoding 2 convolutional code, coding rate 3
Viterbi decoding circuit for decoding / 4 convolutional code, Viterbi decoding circuit for decoding convolutional code with coding rate 7/8, 17,
Reference numeral 18 is a switch for selecting a signal sequence to be output using the error rate from each 19 BER measurement circuits.

Next, the operation will be described. The digital signal in which a plurality of signal sequences are multiplexed is demodulated by the QPSK demodulation circuit 10 after being affected by noise or the like on the transmission line or the like. The demodulated one-series digital signal has its error rate measured by an error rate (BER) measuring circuit 19,
It is separated by the demultiplexer 11. The separated signals have different Viterbi decoding circuits 1 having different error correction capabilities.
Error correction decoding is performed by 4, 15, and 16. Then, based on the bit error rate before separation measured by the BER measuring circuit 19, the switches SW17 and SW18 are operated to output only the series judged to have no deterioration such as BER of 10 -5 or less. For example, it is assumed that the signal series 1, 2, and 3 have a higher priority in this order, such as a low frequency signal, a middle frequency signal, and a high frequency signal of a video signal. Since signals with higher priority are subjected to error correction decoding with higher correction capability, they are less susceptible to noise. Therefore, even if the reception C / N is deteriorated, the signal series 1, the signal series 2, and the signal series 3 are not deteriorated at the same time, and the signal series with lower priority are gradually deteriorated. FIG. 4 shows the relationship between the received C / N and the bit error rate for each signal sequence. When a video signal is received, all the signal sequences do not deteriorate rapidly, but the deterioration starts from the high-frequency component signal of low priority, and then gradually deteriorates in the order of the middle-frequency component signal and the low-frequency component signal. Therefore, it is possible to prevent a sharp deterioration of the received image.

Further, since the error rate measuring circuit is provided before the error correcting circuit, the error rate can be measured in a short time and the deterioration degree of each signal sequence can be specified in a short time. The reason for this is explained in the explanation of the above-mentioned third embodiment.

Further, since the error rate measuring circuit is provided before separating the signal series, only one error rate measuring circuit is required, and the circuit configuration of the receiving device can be simplified.

Note that it is necessary to previously insert a bit string having a specific pattern for measuring the bit error rate into the signal sequence on the transmitting side. Then, the pattern is also stored on the receiving side, and the BER is measured by comparing this pattern with the pattern of the signal which is actually received through the transmission line and is affected by noise.

On the transmitting side, the coding rates of 1/2 and 3 / are assigned to the signal sequences corresponding to the signal sequences 1, 2, and 3, respectively.
It goes without saying that convolutional codes of 4 and 7/8 are added.

Further, in the third and fourth embodiments, in order to match the timings of the multiplexer on the transmitting side and the demultiplexer on the receiving side, a synchronization word is added after the multiplexer on the transmitting side and the receiving side detects this. do it. Here, the synchronization word is required to have an error resilience capability equal to or higher than the codeword having the most correction capability among at least three types of error correction coding circuits.

[0038]

Since the present invention is constructed as described above, it has the following effects.

According to the digital signal transmitting apparatus according to the first aspect of the present invention, it is possible to obtain a transmitting apparatus which generates and transmits a coded signal having different error resilience capabilities according to the priority of the signal sequence.

Furthermore, on the receiving side, it is possible to identify a signal sequence that has not deteriorated in a short time.

Further, according to the digital signal transmitter of the second aspect of the present invention, the circuit configuration of the transmitter can be simplified.

Further, according to the digital signal receiving apparatus of the third aspect of the present invention, it is possible to obtain the receiving apparatus in which the received signal does not rapidly deteriorate even if the received C / N deteriorates.

Further, it is possible to specify the signal sequence which is not deteriorated in a short time.

Further, according to the digital signal receiving apparatus of the fourth aspect of the present invention, the circuit configuration of the receiving apparatus can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing a digital signal transmitting apparatus according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a digital signal transmitting apparatus according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a digital signal receiving apparatus in Embodiment 3 of the present invention.

FIG. 4 is a diagram showing a received C / N vs. bit error rate by the digital signal receiving apparatus in Embodiments 3 and 4 of the present invention.

FIG. 5 is a block diagram showing a digital signal receiving apparatus in Embodiment 4 of the present invention.

FIG. 6 is a block diagram showing a conventional digital signal transmitter and receiver.

FIG. 7 is a diagram showing reception C / N vs. transmission efficiency by a conventional digital signal receiving apparatus.

[Explanation of symbols]

1 QPSK modulation circuit, 2 multiplexer, 3 coding rate 1/2, constraint length 7 convolutional coding circuit, 4 coding rate 3/4, constraint length 7 convolutional coding circuit, 5 coding rate 7 /
8, convolutional code circuit with constraint length 7, 6, 7, 8 specific bit string insertion circuit, 10 QPSK demodulation circuit, 11 demultiplexer, 12, 13, 19 bit error rate (BE
R) measurement circuit, 14 coding rate 1/2, Viterbi decoding circuit for convolutional code with constraint length 7, 15 coding rate 3/4, Viterbi decoding circuit for convolutional code with constraint length 7, 16 coding A Viterbi decoding circuit for a convolutional code having a rate of 7/8 and a constraint length of 7,
17, 18 switches, 101 error correction code circuit, 1
02 digital modulation circuit, 103 digital demodulation circuit, 104 error correction decoding circuit.

Claims (4)

[Claims] 1. A digital signal transmitter for digitally transmitting a plurality of signal sequences, wherein a means for performing error correction coding with different correction capabilities on all or a part of the plurality of signal sequences, and an error correction code. Digitalization having means for performing post-multiplexing, means for digitally modulating the multiplexed signal sequence, and means for adding a bit string having a specific pattern after performing error correction coding Signal transmitter. 2. The digital signal transmitting apparatus according to claim 1, further comprising means for adding a bit string having a specific pattern after multiplexing. 3. A digital signal receiving apparatus for receiving a digital signal in which a plurality of signal sequences are multiplexed, wherein the means for demodulating the digital signal, the means for separating the demodulated signal, and the entire signal series after separation. Alternatively, there are provided means for performing error correction decoding with different correction capabilities for a part, means for measuring a bit error rate before performing error correction decoding, and means for selecting a signal sequence to be output using the bit error rate. A digital signal receiving device having. 4. The digital signal receiving apparatus according to claim 3, further comprising means for measuring a bit error rate before separating the demodulated signal.