JPH08181323A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE: To obtain a MOSFET which has no misalignment between gates faced so as to sandwich a channel region, has a small parasitic capacitance and a small characteristic irregularity, and is of double-gate SOI structure. CONSTITUTION: A plurality of towering silicon rectangular parallelepipeds 50 are formed on a substrate 1 via an oxide film 11. A polycrystal silicon film 22 which comes into contact, via a gate oxide film 14, with a channel region 3 as a part on the large-area surface and the large-area rear for every rectangular parallelepiped is patterned by one photoetching process, and gates are formed. A source region and a drain region 4 are derived to respective electrodes S, D composed of aluminum 31 by means of a polycrystal silicon film 21. In gaps between the parallelepipeds 50, the polycrystal silicon film 21 is buried in a gate part (a), and the polycrystal silicon film 22 is buried in a source part (b) and a drain part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a MOS type field effect transistor (Metal Oxide Effect Transistor) having a structure generally called Silicon On Insulator (SOI).
de Semiconductor Field Effect Transistor: MOSF
The present invention relates to a novel semiconductor device having a double gate structure which is fine and can operate at extremely high speed, and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, an MO having this type of SOI structure
Regarding the double gate structure in which another gate is formed directly below a normal gate in an SFET with a channel region sandwiched therebetween, for example, see Solid State Electronics, Vol. 27, No. 8/9 (1984).
Year), pp. 827-828 (Solid-State Electronic
s, Vol.27, Nos.8 / 9, pp.827-828, 1984). Double-gate structure MOS formed on SOI substrate
The FET has the cross-sectional structure shown in FIG. 5 and the planar structure shown in FIG. Here, in FIG. 5, (a), (b),
(c) is a schematic diagram of a cross-sectional structure taken along line AA, line BB, and line CC in FIG. 6. It should be noted that, in the drawings other than FIG. 5, (a), (b) and (c) respectively show sectional structures when cut at the same position and direction. However,
The plan view of FIG. 6 is shown as a layout pattern diagram of the mask pattern.

The conventional double-gate SOI structure MOSFET shown in FIG. 5 is manufactured by the following method. First, a lower gate 23 called a back gate is formed by using a known MOSFET manufacturing method. This is because LOCOS oxidation is performed on a device-side silicon substrate (not shown) by using a nitride film as a mask to form an oxide film 18, and then a portion where the nitride film is removed is gate-oxidized to form a gate oxide film 17, and then polycrystalline silicon is removed. The lower gate 23 can be formed by depositing and patterning. Next, the oxide film 19 is formed by CVD (Chemical Vapor Deposition).
The oxide film 19 is thickly deposited by a method or the like, and the surface of the oxide film 19 is flattened by grinding and polishing.

After this, the oxide film 19 and the oxide film 7 previously formed on the supporting substrate 6 are directly bonded. In this bonding technique, both surfaces to be bonded are made extremely flat, and the surface of the oxide film 19 and the oxide film 7 are opposed to each other in a dust-free atmosphere, and an appropriate pressure is applied to both surfaces. The bonding is performed without using an adhesive. In this case, the oxide film 7 and the oxide film 19 are integrated without a boundary.

Next, a thin SOI layer 5 is formed by grinding and polishing the element side silicon substrate to make it a thin film. Thereafter, the SOI layer 5 is gate-oxidized to form an upper gate oxide film 14, and polycrystalline silicon is further deposited and patterned in accordance with the back gate 23 to form an upper gate 10 called a front gate, It formed a double gate structure. In FIG. 5, reference numeral 4 is a source / drain region, 13 and 15 are oxide films, 16 is a sidewall oxide film, 31 is a metal electrode such as aluminum, and 40 is a contact hole.

[0006]

However, in the above-mentioned conventional MOSFET having the double gate SOI structure, the front gate 10 must be patterned so as to overlap with the back gate 23. Since the conventional photo-etching technique was used for processing these gates, the problem of misalignment was unavoidable. In particular, the source and drain diffusion layers are self-aligned with the front gate 10, but are not self-aligned with the back gate 23. Therefore, the capacitance between the source and the gate and the drain and the gate are increased, and the characteristic variation is increased. And so on.

Further, if the device side silicon substrate to be a channel, that is, the SOI layer 5 is extremely thinned in order to improve the device characteristics such as current driving capability, the effect of the film thickness variation becomes remarkable. And expensive ultra-thin film S
Since it is necessary to use the OI substrate, the increase in product price cannot be avoided. In addition, as the gate width is increased, the occupation area of the transistor is unavoidably increased, and it is necessary to use the photoetching step twice to process the gate. Therefore, compared with a normal single-gate SOI structure MOSFET. The manufacturing process was complicated, and the rise in product prices was unavoidable.

Therefore, an object of the present invention is to provide a semiconductor device having a double gate SOI structure in which parasitic capacitance and characteristic variations are small and a manufacturing method thereof. Another object of the present invention is to provide a semiconductor device having a double gate SOI structure having a larger ratio of the effective gate width to the occupied gate width than that of the conventional one, and having high performance, and a manufacturing method thereof. . Further, another object of the present invention is that the number of manufacturing steps is the same as that of a normal MOSFET manufacturing method, and a double gate SO capable of avoiding an increase in manufacturing cost.
An object is to provide a semiconductor device having an I structure and a manufacturing method thereof.

[0009]

In order to achieve the above object, a semiconductor device according to the present invention, as shown in FIG. 1, has a silicon dioxide film which is a first insulating film on a supporting substrate, that is, a silicon substrate 1. (Hereinafter, simply referred to as an oxide film) 11 has a plurality of silicon rectangular parallelepipeds arranged in parallel, and each silicon rectangular parallelepiped has a front surface and a back surface wider than a bottom surface in contact with the oxide film 11 and a part of an upper surface of the silicon rectangular solid. The gate of polycrystalline silicon 22 is formed continuously with the front and back surfaces via the gate oxide film 14 and with the upper surface via the second insulating film, that is, the oxide film 12, and one of the rectangular parallelepipeds of each silicon. Source lead-out electrodes taken out from the side surface and the front and back surfaces in the vicinity of the side surface, and a drain lead-out electrode taken out from the other side surface and the front and back surfaces in the vicinity of the side surface. Poles are characterized in that they are electrically connected.

In the semiconductor device, it is preferable that the second insulating film, that is, the oxide film 12 is formed thicker than the gate oxide film 14. Further, it is desirable that the electrode material, that is, the polycrystalline silicons 21 and 22 in FIG. 1 are embedded in a part between the adjacent silicon rectangular parallelepipeds arranged in parallel.

Further, it is preferable that the thickness between the front and back surfaces of the adjacent silicon rectangular parallelepipeds arranged in parallel is formed to be less than 1/2 of the effective gate length.

In order to achieve the above object, the method of manufacturing a semiconductor device according to the present invention comprises a first insulating film, a first semiconductor layer having a low impurity concentration, and a second insulating film on a supporting substrate. FIG. 10 shows a step of sequentially forming a laminated layer, that is, a step of forming a laminated substrate in which an oxide film 11, a single crystal silicon layer 2, and an oxide film 12 are sequentially provided on a silicon substrate 1 in FIG. As described above, the step of patterning the multilayer film of the oxide film 12 and the single crystal silicon layer 2 into a standing rectangular parallelepiped to form the active region 3 of the transistor, and the step of covering the rectangular parallelepiped after forming the gate oxide film 14 in this active region A step of depositing a first polycrystalline silicon film having a high impurity concentration, that is, a polycrystalline silicon film 22, and a step of patterning the polycrystalline silicon film 22 into a desired shape to form a gate as shown in FIG. Source to form a thick oxide film 13 on the surface of the polycrystalline silicon film 22 by the density difference oxidation
A step of forming a thin oxide film on the surface of the single-crystal silicon layer 2 having a low impurity concentration to serve as a drain, a step of removing the thin oxide film in the source / drain regions, and a second polycrystalline silicon film having a high impurity concentration 21 and the polycrystalline silicon film 21 is patterned into a desired shape to form a source.
And a step of forming a drain extraction electrode.

In this case, instead of at least one of the steps of depositing the first and second polycrystalline silicon films 21 and 22 having a high impurity concentration, a step of depositing a polycrystalline silicon film having a low impurity concentration, A step of doping the polycrystalline silicon film with impurities to increase the concentration may be added.

Further, on the supporting substrate, the first insulating film, the first semiconductor layer having a low impurity concentration, the second insulating film, that is, FIG.
5, the step of forming the oxide film 11, the single crystal silicon layer 2, and the oxide film 12 on the silicon substrate 1 in this order, and the oxide film 12 and the single crystal silicon layer 2 as shown in FIG. The multilayer film of is patterned into a standing rectangular parallelepiped,
A step of forming an active region 3 of the transistor, a step of depositing a first polycrystalline silicon film having a high impurity concentration so as to cover the rectangular parallelepiped multilayer film, and a step of forming a first polycrystalline silicon film as shown in FIG. That is, the step of patterning the polycrystalline silicon film 21 into a desired shape to form source / drain extraction electrodes, and the polycrystalline silicon film 2 by concentration difference oxidation.
1. A semiconductor consisting of a step of forming a thick oxide film 13 on the surface of 1 and a thin oxide film on the surface of a low impurity concentration single crystal silicon layer 2, and a step of forming a gate so as to cover the thin oxide film. The above object can also be achieved by using a device manufacturing method. In this case, a step of removing the thin oxide film on the surface of the first semiconductor layer having a low impurity concentration, that is, the single crystal silicon layer 2 after the concentration difference oxidation,
A step of performing gate oxidation again may be further added.

Further, instead of depositing the first polycrystalline silicon film 21 having a high impurity concentration, depositing a polycrystalline silicon film having a low impurity concentration, and doping the polycrystalline silicon with impurities. A step of increasing the concentration can be added.

Further, in any of the above manufacturing methods,
A step of patterning a multi-layered film of a second insulating film and a first semiconductor film into an upright rectangular parallelepiped, and then oxidizing the surface of the first semiconductor layer to form an insulating film; The step of removing the insulating film on the substrate surface may be further added.

Further, it is preferable that a large scale integrated circuit is configured to include any one of the semiconductor devices described above. Further, a high-speed large-scale computer including the large-scale integrated circuit can be configured.

[0018]

According to the semiconductor device of the present invention, a gate is provided for a plurality of silicon rectangular parallelepipeds arranged in parallel via the first insulating film on the support substrate, and a part of each silicon rectangular parallelepiped is provided with front and back surfaces. Is a structure in which a continuous gate is provided through the gate insulating film and the upper surface through the second insulating film, and the source and drain electrodes are taken out from the side surface and adjacent adjacent electrodes are connected to each other. A MOSFET having a double-gate SOI structure is formed in which a part of the rectangular parallelepiped is used as a channel region and the channel region is sandwiched. Further, according to the method of manufacturing a semiconductor device of the present invention, the gate insulating film is formed on the front and back surfaces by one-time gate oxidation, so that the gate insulating films on the front and back surfaces are formed equally. Further, the photo-etching step of the gate can be performed only once, and since the electrodes are continuous on the front and back surfaces of the silicon rectangular parallelepiped, there is no misalignment between the front and back gates facing each other on the front and back surfaces. Therefore, there is no increase in capacitance between the source and the gate and between the drain and the gate, and increase in variations in characteristics.

Further, the second element provided on the upper surface of the silicon rectangular parallelepiped.
By making the insulating film thicker than the thickness of the gate insulating film on the front and back surfaces of the gate insulating film, the gate portion in contact with the upper surface of the silicon rectangular parallelepiped does not function as a gate, but functions as a front gate and a back gate on the front and back surfaces. Acts as a connecting wire. Further, by adopting a structure in which the electrode material is embedded in a part between the silicon rectangular parallelepipeds, the parallel silicon rectangular parallelepipeds can be stably supported.

Further, by adopting a structure in which the thickness between the front and back surfaces of adjacent silicon rectangular parallelepipeds arranged in parallel is smaller than 1/2 of the effective gate length, the channel region is completely depleted and the gate length is shortened. Even so, punch-through between the source and drain is suppressed, so that the short channel effect can be eliminated.

As described above, the semiconductor device of the present invention is
By using a part of each of the silicon rectangular parallelepipeds arranged in parallel as a channel region, the effective gate width can be changed by changing the dimension of the channel region and the interval between the channel regions of each silicon rectangular parallelepiped arranged in parallel. Therefore, the height of each silicon rectangular parallelepiped in the direction perpendicular to the substrate, that is, S
The effective gate width can be increased with respect to the occupied gate width by increasing the dimension of the channel region, which is the OI film thickness, and reducing the interval between the respective silicon rectangular parallelepipeds, that is, the repeating interval between the channel regions. Hereinafter, this relationship will be described with reference to FIGS. 7 and 8.

FIG. 7 shows that the dimension of the channel region in the direction perpendicular to the substrate, that is, the SOI film thickness is d, and the repeating interval between the channel regions is p, d = 0.50 μm, p = 0.25 μ.
Occupied gate width W and effective gate width W when m is constant
_It shows the relationship of _eff . The semiconductor device of the double-gate SOI structure according to the present invention has a conventional double-gate SOI structure of MO in most occupied gate width W.
It can be seen that a larger effective gate width W _eff can be secured as compared with the SFET. Here, in FIG. 7, the effective gate width W _eff of the semiconductor device of the present invention changes stepwise with respect to the occupied gate width W because the addition of one channel region requires at least the repetition interval p. This is because the occupied gate width of is required.

In FIG. 8, the occupied gate width W is fixed at W = 5 μm, the repetition interval p between the channel regions is used as a parameter, and S
The relationship between the OI film thickness d and the effective gate width W _eff is shown. It can be seen that the effective gate width W _eff can be increased by increasing the SOI film thickness d or decreasing the repetition interval p.

From this, the use of this structure facilitates miniaturization, and the M of the high performance double gate SOI structure is obtained.
It becomes possible to realize the OSFET. Further, in order to improve the device characteristics such as the current drive capability, it is not necessary to make the thickness of the upper silicon layer of the SOI substrate, that is, the SOI layer 5 extremely thin as in the conventional example. Since the photo-etching process is performed once, the number of manufacturing processes is usually M
This is the same as the method for manufacturing an OS transistor, and an increase in manufacturing price can be avoided.

[0025]

Embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below in detail with reference to the accompanying drawings. In addition, in the accompanying drawings, essential parts are shown in an enlarged manner compared to other parts for easy understanding.
Needless to say, the material, conductivity type, manufacturing conditions, etc. of each part are not limited to those described in the present embodiment.

<First Embodiment> FIG. 1 shows the first embodiment.
2 and FIG. FIG. 1 shows a MOS having a double gate SOI structure showing an embodiment of a semiconductor device according to the present invention.
FIG. 3 is a cross-sectional structural view of a main part of the FET, and FIG. 2 is a layout pattern diagram schematically showing the planar structure thereof. here,
In FIG. 1, (a), (b), and (c) show respective cross-sections of the portions taken along the lines AA, BB, and CC in FIG. 2, respectively. In addition, also in figures other than FIG.
(a), (b) and (c) show sectional structures in the same direction as in FIG.

As shown in FIG. 1, the semiconductor device of the present invention comprises a plurality of thin silicon rectangular parallelepipeds (three thin silicon rectangular parallelepipeds in this embodiment) arranged in parallel with each other with an oxide film 11 on a silicon substrate 1. ) 50 stands up. The silicon rectangular parallelepiped 50 is formed of the single crystal silicon layer 2 shown in the method of manufacturing a semiconductor device described later. As shown in the sectional view of the gate portion in FIG. 1A and the channel direction portion of the silicon rectangular parallelepiped 50 in FIG. 1C, the polycrystalline silicon film 2 for gates on the front and back surfaces of the silicon rectangular parallelepiped 50 is formed.
2, a gate oxide film 14 is provided immediately below 2, and the single crystal silicon layer below the gate oxide film 14 is a channel region.
In this embodiment, the p-type impurity layer 3 is provided. Here, a pair of facing surfaces wider than the bottom surface of the silicon rectangular parallelepiped 50 in contact with the oxide film 11 are called front and back surfaces, and a pair of facing surfaces in the channel direction are called side surfaces. Further, in FIG. 1C, the p-type impurity layer 3 is all under the gate oxide film 14, but the p-type impurity layer 3 may be omitted depending on the required device characteristics such as threshold value of the device, or It may be part of the area. Immediately below the polycrystalline silicon film 22 on the upper surface of the silicon rectangular parallelepiped 50, an oxide film 12 thicker than the gate oxide film 14 is provided. As can be seen from the cross-sectional view of the gate portion of FIG. 1A, the polycrystalline silicon film 22 serving as the gate covers the front and back surfaces and the top surfaces of the plurality of thin silicon rectangular parallelepipeds 50 standing in parallel, and also fills the gap. It is provided and further connected to the gate electrode G made of aluminum 31 on the silicon rectangular parallelepiped 55 which is as thick as the width of the contact hole 40. In addition, a thick silicon rectangular parallelepiped 55
In the case where the above is not provided, aluminum 31 having a thickness that can reach the polycrystalline silicon film 22 on the oxide film 11 through the contact hole provided in the oxide film 15 may be used.

As shown in the sectional view of the source electrode S portion of FIG. 1B and the sectional view of FIG. 1C, the silicon rectangular parallelepiped 50 is provided with the n-type diffusion layers 4 in the source / drain regions. Both side surfaces of the silicon rectangular parallelepiped 50 are connected to the heavily doped polycrystalline silicon film 21 for source extraction and drain extraction, and the sources and drains are connected in parallel. This polycrystalline silicon film 2
Reference numeral 1 denotes a source electrode S and a drain electrode D made of aluminum 31 through a contact hole 40 provided in the oxide film 15.
Respectively connected to. Further, the polycrystalline silicon film 22 for the gate and the polycrystalline silicon film 21 for leading out the source and the drain are insulated via the oxide film 13. The gaps in the vicinity of both side surfaces of the silicon rectangular parallelepipeds 50 arranged in parallel are each filled with the polycrystalline silicon films 21 for source extraction and drain extraction, and the sources and drains of the silicon rectangular parallelepipeds are arranged in parallel. They are connected in parallel.

In the semiconductor device of this embodiment shown in FIGS. 1 and 2 having such a structure, since the silicon layer which becomes the channel is processed into a rectangular parallelepiped and arranged in parallel, the occupied gate width is The ratio of the effective gate width per hit is large, and miniaturization is easy. Since the double gate can be formed by one photoetching process as described later, the process is simple and the processing accuracy is high. It has advantages such as high performance.

In the semiconductor device of this structure, the thickness between the front and back surfaces of the silicon rectangular parallelepiped 50 is 1 / the effective gate length.
If set to about 2, the channel region can be easily completely depleted by the double gate that sandwiches the channel region between the front and back surfaces. Therefore, even if the channel is shortened, punch-through between the source and drain can be suppressed, and the short channel effect can be achieved. Can be removed. Therefore, it is not necessary to introduce a high impurity concentration into the channel region, which has been conventionally provided to suppress the short channel effect, so that the impurity concentration in the channel region can be reduced.
There is also an advantage that the current driving capability is improved.

An example of the method of manufacturing the semiconductor device according to the present invention shown in FIG. 1 will be described below in order in (1) to (6) below with reference to FIGS. Here, FIG.
14 to 14 are sectional views sequentially showing the manufacturing process of the semiconductor device according to the present embodiment, which show the structure before the sectional structure of FIG.

(1) Referring to FIG. 9;
Using the I technique, an SOI substrate having an oxide film 11 on a silicon substrate 1 and a single crystal silicon layer 2 thereon is formed. That is, an oxide film is formed on each of two substrates, that is, a silicon substrate 1 serving as a supporting substrate and a single crystal silicon substrate serving as an element-side substrate, by thermal oxidation, a CVD method, or the like. Grind the surface
After polishing and flattening, the surfaces are cleaned and the oxide films are opposed to each other, and thermocompression bonding is performed to integrate the oxide films into the oxide film 11, and the silicon substrate 1 and the element-side substrate interpose the oxide film 11 therebetween. And glue. By grinding and polishing the element side substrate to form the single crystal silicon layer 2 having a required thickness, S
An OI substrate is formed. SO formed in this way
An oxide film 12 is deposited on the I substrate by a CVD method to form a laminated substrate in which four layers of a silicon substrate 1, an oxide film 11, a single crystal silicon layer 2 and an oxide film 12 are sequentially laminated.
At that time, in order to prevent the deformation of the single crystal silicon layer 2 which will later become the source / drain due to anisotropic dry etching in the subsequent manufacturing process, the film thickness of the uppermost oxide film 12 should be sufficient. Form thick. For example, if the thickness of the single crystal silicon layer 2 is about 500 nm, it is desirable that the film thickness of the oxide film 12 is at least about 100 nm.

(2) Referring to FIG. 10, next, using a photoresist etching technique, after forming a photoresist pattern, the oxide film 12 is first subjected to anisotropic dry etching using this photoresist pattern as a mask, and then the photoresist is further etched. Using the attached oxide film 12 as a mask, anisotropic dry etching is performed by changing the conditions so that silicon can be easily etched, and the single crystal silicon layer 2 is patterned, for example, a thin silicon rectangular parallelepiped 50 having a thickness between the front and back surfaces of about 50 nm. And a thick silicon rectangular parallelepiped 55 to be a connection portion with the gate electrode G later is formed. At this time, the surface of the oxide film 11 is also slightly etched so that the lower surfaces of the silicon cuboids 50 and 55 are completely separated from the adjacent silicon cuboids. Of course, just etching may be performed in accordance with the surface of the oxide film 11 as long as there is no effect on the device characteristics such as leakage or short circuit due to silicon residues between adjacent silicon rectangular parallelepipeds. After that, boron is implanted into the single crystal silicon layer 2 using an ion implantation technique, and then, for example, 8
A heat treatment is performed at 00 to 900 ° C. for about 60 minutes to form a p-type impurity layer 3 which will later become a channel region. At this time,
After patterning the oxide film 12 and the single crystal silicon layer 2, the surface of the substrate is oxidized, and the oxide film on the surface is removed by an amount corresponding to the thickness of the oxide film. The thickness of the gap may be reduced to about 1/2 of the effective gate length so that a short channel can be formed. Next, gate oxidation is performed, and for example, the film thickness is 5n.
m gate oxide film 14 is formed. At this time, since the gate oxide films having the same thickness can be formed on the front and back surfaces, the gate oxide film thicknesses of the front gate and the back gate are different from each other as in the conventional example, and the characteristics do not vary.

As described above, in the MOSFET of the double gate SOI structure of the present invention, the single crystal silicon layer 2 is processed into a rectangular parallelepiped by using anisotropic dry etching, and the oxide film 1 is formed on the upper surface.
A silicon rectangular parallelepiped 50 having 2 is formed, and a part of this silicon rectangular parallelepiped 50 is used as a channel region. Therefore, the effective gate width can be changed by changing the dimension of the channel region in the direction perpendicular to the substrate and the repeating interval between the channel regions, which enables miniaturization and higher performance of the transistor. Become. Furthermore, in order to improve element characteristics such as current drive capability, SO
It is not necessary to extremely reduce the thickness of the single crystal silicon layer on the upper side of the I substrate. Therefore, it is not necessary to use an expensive ultra-thin film SOI substrate, and an increase in manufacturing cost can be avoided.

(3) Referring to FIG. 11, next, a polycrystalline silicon film 22 containing a high concentration of 10 ²⁰ cm ⁻³ or more of n-type impurities is formed on the surface of the substrate by the CVD method (a). Silicon rectangular parallelepiped 5 whose cross section looks like comb teeth as shown in
It is deposited so that the gap between 0s is filled, that is, at least ½ of the gap between the silicon rectangular parallelepipeds 50 arranged in parallel. Thereafter, the well-known photo-etching technique is used to pattern the polycrystalline silicon film 22 so as to leave a portion to be a gate as shown in FIGS. The polycrystalline silicon film 22 of the portion to be the gate is covered with the gate oxide film 14 at a portion of the front and back surfaces of the silicon rectangular parallelepiped 50 which is to be the channel region, and is covered on the upper surface of the silicon rectangular parallelepiped 50 via the oxide film 12. It is formed so as to extend to the portion of the thick silicon rectangular parallelepiped 55. Note that instead of depositing the polycrystalline silicon film 22 containing a high concentration of n-type impurities, after depositing a polycrystalline silicon film of a low impurity concentration,
Impurities may be implanted by ion implantation to form a polycrystalline silicon film having a high impurity concentration, or a metal material such as tungsten may be used. In this way, since the gate is processed in one photoetching step, the problem of misalignment of the double gates facing each other across the channel region as described in the conventional example does not occur, and parasitic capacitance and transistor Variations in characteristics can be reduced. Furthermore, the number of manufacturing steps becomes equal to that of a normal single-gate MOS transistor, and an increase in manufacturing cost can be avoided.

(4) Referring to FIG. 12, the surface of the heavily doped polycrystalline silicon 22 is thickly oxidized by applying the impurity concentration dependence of the oxidation rate of silicon to, for example, 50 nm. An oxide film 13 having a certain thickness is provided.
At the same time, the surface of the p-type impurity layer 3 that becomes the source / drain regions doped with a low concentration of 10 ¹⁷ cm ⁻³ or less is thinly oxidized. After that, the thin oxide film in the regions to be the source / drain formed by this concentration difference oxidation is removed.

(5) Referring to FIG. 13, next, a polycrystalline silicon film 21 containing a high concentration of n-type impurities is formed on the surface of the substrate by C.
It is deposited by the VD method. The thickness at this time is at least silicon so that the gap between the silicon rectangular parallelepipeds 50 is filled with the polycrystalline silicon film 21 as shown in FIG. 2B, as in the case of depositing the polycrystalline silicon film 22 for the gate. The rectangular parallelepiped 50 is deposited to a thickness of ½ of the gap. Next, the polycrystalline silicon film 21 is patterned by anisotropic dry etching so as to cover the p-type impurity layer 3 in the region where the source / drain is formed. Instead of depositing the polycrystalline silicon film 21 containing a high concentration of n-type impurities, after depositing the polycrystalline silicon film of a low impurity concentration, impurity implantation is performed by ion implantation to form a polycrystalline silicon film of a high impurity concentration. Alternatively, a metal material such as tungsten may be used.

(6) Referring to FIG. 14, after that, for example, a heat treatment is performed at 850 ° C. for about 30 minutes to diffuse impurities from the n-type polycrystalline silicon film 21 and, as shown in FIG. An n-type diffusion layer 4 serving as a source / drain sandwiching the p-type impurity layer 3 in the channel region is formed. Next, an oxide film 15 is provided on the surface of the substrate, and a contact hole is formed at a required position by using a photo etching technique.

If an aluminum electrode is formed after the manufacturing steps described in (1) to (6) above, a low-cost, high-performance MOSF having a double-gate SOI structure shown in FIG. 1 is formed.
ET can be realized.

<Embodiment 2> FIG. 3 shows the second embodiment.
And FIG. 4 will be described. FIG. 3 shows an MO of a double gate SOI structure showing another embodiment of the semiconductor device according to the present invention.
FIG. 4 is a cross-sectional structural view of an essential part of the SFET, and FIG. 4 is a layout pattern diagram schematically showing the planar structure thereof. Here, in FIG. 3, (a), (b), and (c) are cross-sectional views taken along line AA, BB, and CC in FIG. 4, respectively. 3 (d), in order to facilitate understanding, the aluminum 31, the oxide films 13 and 15 are removed,
It is a plan view drawn for convenience so that the oxide film 12 on the upper surface of the silicon rectangular parallelepiped 50 can be seen through the polycrystalline silicon films 21 and 22. 15A to 20 to be described later, (a), (b) and (c) show sectional structures in the same direction as FIG. Further, in FIG. 3, FIG.
For the convenience of explanation, the same components as those indicated by are denoted by the same reference numerals, and detailed description thereof will be omitted. That is, the MOSFET having the structure shown in FIG. 3 is different in the structure of the extraction portion of the gate electrode G via the polycrystalline silicon film 22 for gate.

FIGS. 3A and 3C and FIGS. 1A and 1C
As can be seen by comparing with, the polycrystalline silicon film for gate 22 and the gate electrode G are taken out from directly above the silicon rectangular parallelepiped 50 arranged in parallel, and the polycrystalline silicon film up to the silicon rectangular parallelepiped 55 as shown in FIG. 22 is not pulled out and taken out. With such a structure,
In addition to the advantages of the first embodiment, there is no concern that the gate will be broken or the resistance will become high, and the gate can be processed after the source / drain formation as described later, so that the gate reliability is further improved. Since the degree of freedom in selecting the gate material is also high, a gate having low resistance can be formed by using a metal material or the like.

Hereinafter, an example of a method of manufacturing the semiconductor device according to the present invention shown in FIG. 3 will be described in order in the following (7) to (12) with reference to FIGS. here,
15 to 20 are sectional structures sequentially showing the manufacturing process of the semiconductor device according to the present embodiment, and show the structure before the sectional structure of FIG.

(7) Referring to FIG. 15;
Using the I technique, an SOI substrate having an oxide film 11 on a silicon substrate 1 and a single crystal silicon layer 2 thereon is formed. To form this SOI substrate, the method described in (1) of Example 1 with reference to FIG. 9 may be used. Then, the oxide film 12 is deposited by the CVD method to form a laminated substrate in which four layers of the silicon substrate 1, the oxide film 11, the single crystal silicon layer 2 and the oxide film 12 are sequentially laminated.
At this time, as in the first embodiment, the uppermost oxide film 12 is formed in order to prevent deformation of the single crystal silicon layer 2 which will later become the source / drain due to anisotropic dry etching in the subsequent manufacturing process. The film thickness is formed sufficiently thick. For example, if the thickness of the single crystal silicon layer 2 is about 500 nm, the thickness of the oxide film 12 is at least 100 nm.
It is desirable to set the degree.

(8) Referring to FIG. 16, next, a photoresist pattern is formed by using a photoresist etching technique, and then the oxide film 12 is first anisotropically dry-etched using this photoresist pattern as a mask. Using the oxide film 12 as a mask, anisotropic dry etching is performed under the condition that silicon is easily etched to pattern the single crystal silicon layer 2. After that, boron as a p-type impurity is implanted into the single crystal silicon layer 2 by using an ion implantation technique, and subsequently, a heat treatment is performed at 800 to 900 ° C. for about 60 minutes, for example, and a p-type diffusion layer to be a channel region later is formed. 3 is formed. Here, by oxidizing the surface of the substrate and removing the oxide film on the surface by the thickness of this oxide film, a finer
For example, the thickness between the front and back surfaces of the silicon rectangular parallelepiped 50 may be thinned to about 1/2 of the effective gate length so that a short channel can be formed.

(9) Referring to FIG. 17, thereafter, a polycrystalline silicon film 21 containing a high concentration of 10 ²⁰ cm ⁻³ or more of n-type impurities is deposited on the substrate surface by the CVD method. At this time, the thickness is at least ½ of the gap between the silicon rectangular parallelepipeds 50 so that the gap between the silicon rectangular parallelepipeds 50 is filled with the polycrystalline silicon film 21 as shown in FIG. . Thereafter, as shown in FIGS. 9B and 9C, the polycrystalline silicon film 21 is patterned by anisotropic dry etching so as to leave the portions to be the source / drain.

(10) Referring to FIG. 18, next, by applying the impurity concentration dependence of the oxidation rate of silicon, for example, 8
A heat treatment is performed at 50 ° C. for about 30 minutes to thickly oxidize the surface of the polycrystalline silicon film 21 that is heavily doped with impurities,
For example, the oxide film 13 having a thickness of about 50 nm is provided. At the same time, the surface of the p-type impurity layer 3 that becomes the channel region doped with a low concentration of 10 ¹⁷ cm ⁻³ or less is thinly oxidized. Further, by the heat treatment at this time, a high concentration of n
Impurities are diffused from the polycrystalline silicon film 21 that is doped in the shape of the n-type to form the n-type diffusion layer 4 serving as the source / drain. After that, the thin oxide films on the front and back surfaces of the channel region formed by this concentration difference oxidation are removed. Next, the front and back surfaces of the channel region of the silicon rectangular parallelepiped 50 are again oxidized to form the gate oxide film 14 having a thickness of 5 nm, for example. In addition,
A thin oxide film on the front and back surfaces of the channel region formed by concentration difference oxidation may be used as the gate oxide film.

(11) Referring to FIG. 19, thereafter, a polycrystalline silicon film 22 containing a high concentration of n-type impurities of 10 ²⁰ cm ^-3 or more is deposited on the substrate surface by the CVD method. The thickness at this time is similar to that when the polycrystalline silicon film 21 for the source / drain extraction electrodes is deposited, and the silicon rectangular parallelepiped 50 is used.
The gap between the polycrystalline silicon film 2 is as shown in FIG.
At least a silicon rectangular parallelepiped 50 to be embedded with 1.
Deposit to half the thickness of the gap between them. Next, the polycrystalline silicon film 22 is patterned by anisotropic dry etching so as to cover the p-type diffusion layer 3 to be the channel region, thereby forming a gate. Since the gate is processed after forming the source / drain in this way, instead of using the polycrystalline silicon film 22 containing a high concentration of n-type impurities as the gate material, a low resistance metal material such as tungsten is used. Is also good.

(12) Referring to FIG. 20, next, an oxide film 15 is provided on the surface of the substrate, and a contact hole is formed at a required position by using a photoetching technique.

If the aluminum electrode is formed after the manufacturing steps described in (7) to (12) above, a double-layered structure that is inexpensive, has little variation in transistor characteristics, and is fine and high-performance, as shown in FIG. Gate SOI structure MOSFE
T can be realized.

<Third Embodiment> Next, a third embodiment will be described with reference to FIG. FIG. 21 is a block diagram showing an example of a high-speed large-scale computer having a large-scale integrated circuit to which the semiconductor device according to the present invention is applied. Since the high-speed silicon semiconductor integrated circuit can be highly integrated by using the above-described MOSFET of the double gate SOI structure of the present invention,
It is applied to a processor 500 that processes instructions and operations, a system control device 501, a main storage device 502, etc.
It could be composed of a silicon semiconductor chip having a side of about 10 to 30 mm. The processor 500 for processing these instructions and operations, the system controller 501, and the data communication interface 503 composed of a high-speed silicon semiconductor integrated circuit and a compound semiconductor integrated circuit using the MOSFET of the double gate SOI structure of the present invention are the same. It was mounted on a ceramic substrate 506. Further, the data communication interface 503 and the data communication control device 504 are mounted on the same ceramic substrate 507. The ceramic substrates 506 and 507 and the ceramic substrate on which the main memory device 502 is mounted are mounted on a substrate having a size of about 50 cm or less, and a central processing unit 508 of a large-scale computer is configured. Data communication within the central processing unit 508, data communication between a plurality of central processing units,
Alternatively, data communication between the data communication interface 503 and the board 509 on which the input / output processor 505 is mounted is performed via the optical fiber 510 indicated by the double-ended arrow lines in the figure.

In the large-scale computer configured as described above, the processor 500 for processing instructions and operations, the system control unit 501, the silicon semiconductor integrated circuits such as the main storage unit 502 operate in parallel at high speed, and Since the communication is performed using light as a medium, the number of instruction processings per second can be significantly increased. Further, since the semiconductor device according to the present invention having the double gate SOI structure used in the silicon semiconductor integrated circuit can be manufactured on the SOI substrate which is cheaper than the conventional one, the increase in the product price can be suppressed and the higher speed arithmetic processing can be performed. We were able to realize a possible large-scale computer.

The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above embodiments, and various design changes are made within the scope not departing from the spirit of the present invention, for example, the embodiments. Although the n-channel MOSFET has been described, a p-channel MO can be obtained by changing the conductivity type.
Of course, the SFET can be used, and the number of upstanding silicon cuboids arranged in parallel, the thickness and height of the front and back surfaces, and the impurity concentration can be changed.

[0053]

As is apparent from the above-described embodiments, according to the present invention, since the gate can be formed by one photo-etching step, there is no problem of misalignment of the gates facing each other with the channel sandwiched therebetween. , MOSFET of double gate SOI structure with less parasitic capacitance and characteristic variation
Can be realized. In addition, the silicon layer of the SOI substrate is processed into an upright rectangular parallelepiped by using anisotropic dry etching, and a part of this is used as a channel region, and the upright rectangular parallelepipeds are arranged in parallel, so that an effective gate width is achieved. It is possible to obtain a MOSFET having a double-gate SOI structure with an increased gate width. Furthermore, since the number of manufacturing steps is the same as that of a normal single-gate MOSFET manufacturing method, it is possible to avoid an increase in manufacturing cost.

[Brief description of drawings]

FIG. 1 is a cross-sectional structural view showing an embodiment of a semiconductor device according to the present invention, wherein (a) is a gate portion, (b) is a source portion, and (c) is a cross-sectional view schematically showing a channel portion. .

FIG. 2 is a layout pattern diagram showing an outline of a planar structure of the semiconductor device according to the present invention shown in FIG.

3A and 3B are cross-sectional structural views showing another embodiment of the semiconductor device according to the present invention, in which FIG. 3A is a gate portion, FIG. 3B is a source portion, and FIG. And (d) is a schematic plan view showing a rectangular parallelepiped 50 that stands upright with the polycrystalline silicon films 21 and 22.

FIG. 4 is a layout pattern diagram showing an outline of a planar structure of the semiconductor device according to the present invention shown in FIG.

FIG. 5 is a conventional MOSFET having a double-gate SOI structure.
FIG. 3A is a cross-sectional structure diagram showing the structure of FIG.
FIG. 3A is a cross-sectional view showing an outline of a source portion and FIG.

6 is a layout pattern diagram showing an outline of a planar structure of the conventional semiconductor device shown in FIG.

FIG. 7 is a diagram showing a relationship between an occupied gate width and an effective gate width in a semiconductor device according to the present invention.

FIG. 8 is a diagram showing a relationship between an SOI film thickness and an effective gate width in a semiconductor device according to the present invention, using a channel repetition interval as a parameter.

9A and 9B are cross-sectional structural views in an intermediate step for explaining the method for manufacturing the semiconductor device shown in FIG. 1, in which (a) is a gate portion, (b) is a source portion, and (c) is a channel portion schematically. It is a figure which respectively shows.

FIG. 10 is a cross-sectional structural view in a next manufacturing process of each part illustrated in FIG.

FIG. 11 is a sectional structural view in a manufacturing process subsequent to each part illustrated in FIG. 10.

FIG. 12 is a cross-sectional structure diagram in a manufacturing process next to each part illustrated in FIG. 11.

FIG. 13 is a cross-sectional structure diagram in a manufacturing process next to each part illustrated in FIG.

FIG. 14 is a cross-sectional structure diagram in a manufacturing process next to each part illustrated in FIG.

15A and 15B are cross-sectional structural views in an intermediate step for explaining the method for manufacturing the semiconductor device shown in FIG. 3, in which (a) is a gate portion, (b) is a source portion, and (c) is a schematic channel portion. It is a figure which respectively shows.

16 is a cross-sectional structure diagram in a manufacturing process next to each part illustrated in FIG. 15. FIG.

FIG. 17 is a cross-sectional structure diagram in a manufacturing process next to each part illustrated in FIG. 16.

FIG. 18 is a sectional structural view in a manufacturing process subsequent to each part shown in FIG. 17.

FIG. 19 is a sectional structural view in a manufacturing process subsequent to each portion illustrated in FIG. 18.

FIG. 20 is a cross-sectional structure diagram in a manufacturing process next to each part illustrated in FIG. 19.

FIG. 21 is a diagram showing a configuration example of a large-scale computer to which the semiconductor device according to the present invention can be suitably applied.

[Explanation of symbols]

1 ... Silicon substrate (supporting substrate), 2 ... Single crystal silicon layer (device-side substrate), 3 ... P-type diffusion layer (channel region, active region), 4 ... N-type diffusion layer (source / drain region), 5 ... SOI layer, 6 ... Support substrate, 7 ... Oxide film, 10 ... Gate, 11, 12, 13, 15 ... Silicon dioxide film (oxide film), 14, 17 ... Gate oxide film, 16, 18, 19 ... Silicon dioxide film (Oxide film), 21 ... Polycrystalline silicon film, 22, 23 ... Polycrystalline silicon film (gate), 31 ... Aluminum, 40 ... Contact hole, 50, 55 ... Silicon rectangular parallelepiped, 500 ... Processor, 501 ... System control device, 502 ... Main memory device, 503 ... Data communication interface, 504 ... Data communication control device, 505 ... Input / output processor, 506, 507 ... Ceramic substrate, 508 ... Central Management unit, 509 ... input-output processor mounting substrate, 510 ... communication optical fiber.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yukihiro Kiyoda 1-280 Higashi Koikeku, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Inventor Shun Uchino 1-280 Higashi Koikeku, Kokubunji, Tokyo Hitachi, Ltd. Central Research Laboratory (72) Inventor Kazuhiro Onishi 1-280 Higashi Koikekubo, Kokubunji, Tokyo Hitachi Central Research Laboratory (72) Inventor Takeo Shiba 1-280 Higashi Koikeku, Kokubunji, Tokyo Hitachi Central Research Center

Claims (12)

[Claims] 1. A silicon rectangular parallelepiped having a plurality of silicon rectangular parallelepipeds arranged in parallel on a supporting substrate with a first insulating film interposed therebetween, the front and back surfaces of each silicon rectangular parallelepiped being wider than the bottom surface in contact with the first insulating film, and the silicon rectangular parallelepiped. While covering a part of the upper surface continuously, the front and back surfaces are formed with the gate insulating film interposed therebetween, and the upper surface is formed with the second insulating film formed therebetween, one side surface of each silicon rectangular parallelepiped and its side surface. The source extraction electrode is taken out from the front and back surfaces near the side surface, and the drain extraction electrode is taken out from the other side surface and the front and back surfaces near the side surface.Each adjacent same electrode is electrically connected to each other. A semiconductor device characterized in that 2. The semiconductor device according to claim 1, wherein the second insulating film is thicker than the gate insulating film. 3. The semiconductor device according to claim 1, wherein an electrode material is embedded in a part between adjacent silicon rectangular parallelepipeds arranged in parallel. 4. The thickness between the front and back surfaces of adjacent silicon rectangular parallelepipeds arranged in parallel is less than ½ of the effective gate length. Semiconductor device. 5. A step of sequentially forming a first insulating film, a low-impurity-concentration first semiconductor layer, and a second insulating film on a supporting substrate, and the second insulating film and the first insulating film. Patterning the multi-layered film with the semiconductor film into an upright rectangular parallelepiped to form an active region of the transistor, and forming a gate insulating film in the active region to cover the rectangular parallelepiped.
A step of depositing a polycrystalline silicon film of 1), a step of patterning the first polycrystalline silicon film into a desired shape to form a gate, and a thick insulating film on the surface of the first polycrystalline silicon film by concentration difference oxidation. Forming a thin insulating film on the surface of the first semiconductor layer having a low impurity concentration that serves as a source / drain; removing the thin insulating film in the source / drain region; And a step of forming the source / drain lead-out electrodes by patterning the second polycrystalline silicon film into a desired shape. 6. A step of depositing a polycrystalline silicon film having a low impurity concentration, in place of at least one of the steps of depositing the first and second polycrystalline silicon films having a high impurity concentration, and the polycrystalline silicon. The method of manufacturing a semiconductor device according to claim 5, further comprising a step of doping the film with impurities to increase the concentration. 7. A step of sequentially forming a first insulating film, a first semiconductor layer having a low impurity concentration, and a second insulating film on a support substrate, the second insulating film and the first insulating film. Patterning the multilayer film of the semiconductor layer into an upright rectangular parallelepiped to form an active region of a transistor, and depositing a first polycrystalline silicon film having a high impurity concentration so as to cover the rectangular parallelepiped multilayer film, Patterning the first polycrystalline silicon film into a desired shape to form source / drain lead-out electrodes; forming a thick insulating film on the surface of the first polycrystalline silicon film by concentration difference oxidation; And a step of forming a gate so as to cover the thin insulating film, and a step of forming a thin insulating film on the surface of the first semiconductor layer. 8. The method according to claim 7, further comprising a step of removing the thin insulating film formed on the surface of the first semiconductor layer having a low impurity concentration after the concentration difference oxidation and a step of performing gate oxidation again. Manufacturing method of semiconductor device. 9. A step of depositing a polycrystalline silicon film having a low impurity concentration instead of the step of depositing the first polycrystalline silicon film having a high impurity concentration; 9. The method for manufacturing a semiconductor device according to claim 7, further comprising a step of increasing the concentration. 10. A step of forming an insulating film on the surface of the first semiconductor layer by patterning a multilayer film of the second insulating film and the first semiconductor film into a standing rectangular parallelepiped and then oxidizing the same, and the insulating step. The method for manufacturing a semiconductor device according to claim 5, further comprising a step of removing the film and the insulating film on the surface of the substrate corresponding to the film thickness. 11. A large scale integrated circuit comprising the semiconductor device according to claim 1. Description: 12. A high-speed large-scale computer comprising the large-scale integrated circuit according to claim 11.