JPH08180016A - Communication interface circuit - Google Patents

Abstract

PURPOSE: To accelerate a data input/output processing speed by transmitting and receiving addresses and data by respective dedicated general purpose asynchronous transmission/reception circuits and generating write signals from the start bit of serial data signals to be significant at the time of receiving the data. CONSTITUTION: In the case of writing the data in serial communication, the general purpose asynchronous transmission/reception circuit (UART) 8 transmits and receives the addresses, the UART 9 transmits and receives the data and a start bit detection circuit 22 detects the start bit of the serial data signals 12. Then, a write signal pulse generation circuit 17 forms the write signals 20 to a RAM 13 with a start bit detection signal 23 detected in the start bit detection circuit 22 as a trigger. Thus, the data output processing speed is accelerated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication interface circuit for performing data input / output processing to an external memory or an external input / output device by serial communication.

[0002]

2. Description of the Related Art FIG. 14 is an example showing a configuration of a conventional communication interface circuit. In the figure, 1 is a central processing unit (hereinafter referred to as a CPU unit), 2 is a CPU,
3 is R in which a program for installing the CPU 2 is input
OM, 4 is an address bus, 5 is a data bus, 6 is a read signal, 7 is a transmission signal for starting serial transfer of data, 9 is a general-purpose asynchronous transmission / reception circuit (hereinafter referred to as UART) for performing serial communication, Reference numeral 10 is an external I / F circuit for fetching sensor data and the like, 11 is a memory unit apart from the CPU unit 1, 12 is a serial data signal between the CPU unit 1 and the memory unit 11, 13
Is RAM, 14 is an address bus, 15 is a data bus, 1
Reference numeral 9 is a reception flag reset signal that is input to the UART 9 when the next serial data signal 12 can be accepted, 20 is a write signal, 21 is a reception flag that becomes significant when the UART 9 receives the serial data signal 12, 27
Is a read signal, 39 is a transmission signal input to the UART as a trigger when transmitting data to the CPU unit 1, 4
Reference numeral 9 is a CPU, and 50 is a ROM into which a program for controlling the CPU 49 is input.

FIG. 15 is a timing chart of a conventional communication interface circuit. Serial data signal 12
Are transmitted in the order of start bit, data, parity bit, stop bit. (A) shows a data write cycle and (b) shows a data read cycle. Here, T11, T21, ... Are serial data signals 1
2 is the time to receive, T12, T22 ... Is the time until the CPU 1 reads the received data and stores it in the register, T3
Is the time to decode the command, T14, T24 ... Is the time to reset the reception flag, T5 is the time to execute the data write command, T6 is the time to execute the data read command, and T17, T27. The waiting time is shown respectively. In addition, T12, T22 ... each time, T14, T24 ... each time, T1
7, T27 ... The respective times can be set equal to each other, so when considering only the times, they are expressed as T2, T4, T7 in order. Further, when the lowercase letter t is used to represent t **, it indicates the first timing of the period of T **.

Data such as sensor data is input from the external I / F circuit 10 to the CPU unit 1, and the CPU 2
Consider the case of writing the data to the memory unit 11 located at a remote place and reading the data of the address designated by the CPU unit 1 from the memory unit 11 under the control of 1. The transmission order is decided between the units, but here, in the case of data writing, the command, the address upper bit, the address lower bit, and the data are set, and in the data reading, the command, the address upper bit, and the address lower bit are set. Further, the command is transmitted by the code defined between the CPU unit 1 and the memory unit 11.

First, consider the data write cycle in FIG. 15 (a). When a command is transmitted as the serial data signal 12 from the UART 9 of the CPU unit 1, the UART 9 on the memory unit 11 side receives the serial data signal 12 at T11, converts it to parallel data, and ends the reception flag 21 as significant. Become. At this time, the received command is output to the data bus 15. At T12, the CPU 49 reads this command,
In step 3, the command is decoded, and it is determined that the process of writing the data to be transmitted next in the address transmitted in the following 2 bytes should be performed. When the command reception process is completed, the reception flag 21 is reset by the reception flag reset signal 19 at T14, and the UART 9 enters the waiting state for the serial data signal 12. Next serial data signal 1
When 2 is received, it is determined as the upper bit of the address, and T22
Is taken into the internal register of the CPU 49, and the reception flag 21 is reset at T24. Similarly, the lower bits of the address and the data are read, and when the address and the data are prepared, the command is executed at T5, the write signal 20 is output, and the data is written in the RAM 13. Summarizing these operations, the time required to write data is as shown in equation (1). T11 + T21 + T31 + T41 + 4 × T2 + T3 + 4 × T4 + T5 + 3 × T7 (1)

Next, consider the data read cycle shown in FIG. The process is similar to the data write cycle until the command is received at T11 and read by the CPU 49 at T12. When the command is decoded at T3, it is determined that the data of the address transmitted by the next 2 bytes is read from the RAM 13 and transmitted to the CPU unit 1. Similarly to the data write cycle, the reception flag 21 is reset at T14, and the upper bits of the address and the lower bits of the address are received in order. When the addresses are aligned, the command is executed at T6, the read signal 27 is output, the data is read from the RAM 13, the transmission signal 39 is output to the UART 9, and the data is transmitted to the CPU unit 1. Summarizing these operations, the time required for reading data is as shown in equation (2). T11 + T21 + T31 + 3 × T2 + T3 + 3 × T4 + T6 + 2 × T7 (2)

The case where data input / output processing is performed in the memory unit 11 has been described above.
Even if is an external input / output device, the processing procedure is the same. Further, the case where the address is twice and the command and data are serially transferred at one time has been described. However, even if the bit length is changed, the number of serial transfers is increased or decreased and the processing procedure is the same.

[0008]

As described above, in the conventional communication interface circuit, when data input / output processing is performed by serial communication with an external memory or an external input / output device, commands, addresses and data must be transmitted in series. However, there is a problem that the processing speed is slow.

The present invention has been made to solve the above problems, and an object thereof is to improve the processing speed when performing data input / output processing by conventional serial communication.

[0010]

A communication interface circuit according to a first embodiment of the present invention uses a UART at the head of address transmission / reception when writing data by serial communication.
And a UART dedicated to data transmission / reception, a start bit detection circuit for detecting a start bit of a serial data signal, and a write signal pulse generation for generating a write signal to a RAM triggered by the start bit detection signal detected by the start bit detection circuit And a circuit.

Further, the communication interface circuit according to the second embodiment of the present invention detects a UART dedicated to address transmission / reception, a UART dedicated to data transmission / reception, and a stop bit of a serial data signal when data is written by serial communication. It is provided with a stop bit detection circuit and a gate for generating a write signal to the RAM in response to the stop bit detection signal detected by the stop bit detection circuit.

Further, in the communication interface circuit according to the third embodiment of the present invention, the start bit detection signal of the serial data signal received by the address transmission / reception dedicated UART and the data transmission / reception only UART so that not only the data writing but also the data reading can be performed. And a read signal pulse generation circuit that generates a write signal and a read signal by using a combination of the start bit detection signals of the serial data signal received in step 1, and outputs the mask signal to the write signal pulse generation circuit.

Further, in the communication interface circuit according to the fourth embodiment of the present invention, the stop bit detection signal of the serial data signal received by the address transmission / reception dedicated UART is written to the RAM so that not only the data writing but also the data reading can be performed. Signal and read signal,
A circuit for selecting one of them by a stop bit detection signal of a serial data signal received by a UART dedicated to data transmission and reception.

The communication interface circuit according to the fifth embodiment of the present invention uses a UART dedicated to address transmission / reception and an UART for address / data transmission / reception and respective start bit detection signals in order to perform data writing and data reading. And a circuit for generating a write signal or a read signal.

[0015]

According to the first embodiment of the present invention, the address and the data are transmitted and received by the dedicated UART, the start bit of the serial data signal is detected, and the write signal to the RAM is generated by using this as a trigger to generate the data. The output processing speed is improved.

Further, according to the second embodiment of the present invention, the address and the data are transmitted and received by the dedicated UART, respectively.
The stop bit of the serial data signal is detected, and the write signal to the RAM is generated through the gate to improve the data output processing speed.

According to the third embodiment of the present invention, the address and the data are transmitted and received by the dedicated UARTs, respectively.
A write signal to the RAM is generated from the start bit of the serial data signal received by the address dedicated UART, and a read signal to the RAM is generated from the start bit of the serial data signal received by the data dedicated UART, and at the same time the write signal is masked. Therefore, the data input / output processing speed is improved.

According to the fourth embodiment of the present invention, the address and the data are transmitted and received by the dedicated UARTs, respectively.
The data input / output processing speed is improved by detecting the stop bit of each serial data signal, generating a pulse upon the detection of the stop bit, and switching to a write signal or a read signal to the RAM.

Further, according to the fifth embodiment of the present invention, the address is divided and transmitted / received by two UARTs, the start bit signal of each serial data signal is detected, and the write signal or read to the RAM from the reception timing is performed. By generating a signal, the data input / output processing speed is improved.

[0020]

【Example】

Example 1. FIG. 1 shows an embodiment of the present invention. In the figure, 8 is a UART dedicated to address transmission / reception,
Reference numeral 16 is a reception flag of the UART 8, 17 is a write signal pulse generation circuit for generating a write signal 20 for writing data in the RAM 13, 18 is a reset pulse generation circuit for generating a pulse for resetting the circuit, and 19 is a reset pulse generation circuit. The flag reset signal generated at 18, 22 is a start bit detection circuit for detecting the start bit of the serial data signal 12, 23 is a start bit detection signal that becomes significant when the start bit detection circuit 22 detects the start bit, and 31 is an input A delay circuit for delaying the signal, 32 is a delayed start bit detection signal obtained by delaying the start bit detection signal 23 by the delay circuit 31, 33
Is a delay circuit for delaying the input signal, and 34 is a delayed start bit detection signal obtained by delaying the start bit detection signal 23 by the delay circuit 33.

FIG. 2 is a timing chart of one embodiment. RA of address and data from CPU unit 1
It shows a case where the data is transmitted to be written in M13. U
When the ART 8 receives the serial data signal 12, the start bit detection circuit 22 detects it and the start bit detection signal 23 becomes significant at t21. The start bit detection signal 23 is delayed by the delay circuit 31 until the serial data signal 12 is converted into parallel, and the write signal pulse generation circuit 17 generates the write signal 20. At the rising of the write signal 20, when the data output from the UART 9 is written to the address output from the UART 8 at that time, next, the start bit detection signal delayed from the delay start bit detection signal 32 by the delay circuit 33. After 34 from the write signal 20, the reset pulse generation circuit 18 generates the flag reset signal 19 at t34. If the UART8, the UART9, and the start bit detection circuit 22 are reset at T34, the memory unit 11 side waits for the next serial data signal 12. Summarizing these operations, the time required to write data is as shown in Expression (3). T21 + T31 + T4 + T5 (3)

Comparing the equation (3) with the equation (1) as described above, the processing speed of the present embodiment is improved by four times as compared with the conventional example. T11 + T41 + 4 × T2 + T3 + 3 × T4 + 3 × T7 (4)

Although the case of writing data to the memory unit 11 has been described, the processing procedure is the same even when the memory unit 11 is an external output device. The case where the write signal 20 and the flag reset signal 19 are generated from the start bit of the serial data signal 12 received by the UART 8 dedicated to address transmission / reception has been described, but the start of the serial data signal 12 received by the UART 9 dedicated to data transmission / reception has been described. Write signal 20 from bit
And the flag reset signal 19 may be generated, and the processing procedure is the same. Further, no matter how the bit lengths of the address and data change, the start bit detection signal 23 may be delayed until the transfer of both companies is completed, and the flag reset signal 19 and the write signal 20 may be generated. Is the same.

Embodiment 2 FIG. FIG. 3 is a block diagram showing the second embodiment. In the figure, 25 is a gate whose output is significant only when the logic of the input signal is different, 28 is a stop bit detection circuit for detecting a stop bit of the serial data signal 12, 29 is a stop bit detection circuit 28 for detecting a stop bit. A stop bit detection signal that becomes significant, and 30 is a stop bit detection signal that becomes significant when the stop bit detection circuit 28 detects a stop bit.

FIG. 4 is a timing chart of the second embodiment. RA of address and data from CPU unit 1
It shows a case where the data is transmitted to be written in M13. When the serial data signal 12 is received, the stop bit detection circuit 28 detects the stop bit. Since the stop bit is detected when a certain time or more has elapsed after the data became significant, the detection is performed here by taking time until the serial data signal 12 is converted into parallel. Further, it is assumed that the address has a bit length longer than the data, and the timings at which the stop bit detection signal 29 and the stop bit detection signal 30 become significant are deviated by the difference in bit length. If this timing is used, a pulse is generated within the period of T5 at a time when the stop bit detection signal 30 is significant and the stop bit detection signal 29 is not significant. This is a write signal 20. At the rising edge of the write signal 20, at that time UAR
When the data output from UART9 is written to the address output from T8, the write signal 2
0 is delayed by the delay circuit 33, and the flag reset signal 19 is generated at t34. UART8 and UART at T34
9 and the stop bit detection circuit 22 are reset,
The memory unit 11 side waits for the next serial data signal 12. Summarizing these operations, the time required to write data is expressed by equation (3) as in the first embodiment.

Therefore, comparing equation (3) with equation (1),
In the present embodiment, the processing speed is improved by four hours as compared with the conventional example.

The case of writing data to the memory unit 11 has been described, but the processing procedure is the same even when the memory unit 11 is an external output device. Further, no matter how the bit lengths of the address and data change, if the bit lengths are not equal, the stop bit is detected and the write signal 20
And the flag reset signal 19 may be generated, and the processing procedure is the same.

Example 3. FIG. 5 is a block diagram of the third embodiment. In the figure, 24 is a start bit detection circuit 2
2 is a start bit detection signal that becomes significant when a start bit is detected, and 26 generates a read signal 27 when the input signal becomes significant, and at the same time, a write signal pulse generation circuit 17
Read signal pulse generation circuit that outputs a signal that masks the output of the signal, 35 is a mask signal that masks the output of the write signal generation circuit 17, and 47 is a significant time of the read signal 27 in order to extend the data output from the RAM 13. An extension circuit for extension, 48 is an extension read signal extended by the extension circuit 47.

FIG. 6 shows a timing chart of the data write cycle of the third embodiment, and FIG. 7 shows a timing chart of the data read cycle of the third embodiment. First, consider the data write cycle of FIG. When writing data, the CPU unit 1 sends an address and data, and at t21 the start bit detection circuit 2
1 detects the start bit, and both the start bit detection signal 23 and the start bit detection signal 24 become significant. The start bit detection signal 23 is delayed by the delay circuit 31 until the serial data signal 12 is converted into parallel, and is input to the write signal pulse generation circuit 17 as the delayed start bit detection signal 32 to generate the write signal 20. At that time, the data output from the UART 9 is written to the address output from the UART 8. The read signal pulse generation circuit uses the start bit detection signal 2
It does not operate when both 3 and the start bit detection signal 24 are significant. After that, as in the first embodiment, the write signal 20
After a further delay, the reset pulse generation circuit 18 generates the flag reset signal 19, and at T34, UART8 and UART are generated.
9 and the start bit detection circuit 22 are reset, and the memory unit 11 side waits for the next serial data signal 12. Summarizing these operations, the time required to write data is the same as that in the first embodiment and is expressed by the equation (3).

Comparing the equation (3) with the equation (1) as described above, the processing speed of the present embodiment is improved by 4 times as compared with the conventional example.

Next, consider the data read cycle of FIG. CPU unit 1 in the data read cycle
Sends the address only. Therefore, the start bit detection signal 23 becomes significant, but the start bit detection signal 24 does not become significant, and the delayed start bit detection signal 3
Only 2 will be significant. At this time, as in the data write cycle, the write signal 20 is generated in the write signal pulse generation circuit 17, but only the delayed start bit detection signal 32 is significant in the read signal pulse generation circuit 26, so that in the data read cycle. It is determined that there is a read signal 27, and a mask signal 35 for masking the output of the write signal 20 is supplied to the write signal pulse generation circuit 1
Output to 7. In this way, only the read signal 27 is output, and the data of the address output from the UART 8 at that time is read from the RAM 13. The read signal 27 is extended and input to the RAM 13 by the extension circuit 47, and the read signal 27 is transmitted to the transmission signal 3
If it is input to the UART 9 as 9, the data output to the data bus 15 at the rising edge of the transmission signal 39 will be the CPU.
Serially transferred to unit 1. The processing procedure for resetting the reception flag 16 at T34 and setting the next serial data signal 12 in the waiting state is the same as that in the data write cycle. Summarizing these operations, the time required to read data is as shown in equation (5). T21 + T31 + T4 + T6 (5)

By comparing the equation (5) with the equation (2) as described above, the processing speed of the present embodiment is improved by the number of hours 6 as compared with the conventional example. T11 + 3 × T2 + T3 + 2 × T4 + 2 × T7 (6)

The case of writing data to the memory unit 11 and the case of reading data from the memory unit 11 have been described, but the processing procedure is the same even when the memory unit 11 is an external input / output device. In addition, no matter how the bit lengths of the address and the data change, the start bit detection signal 23 and the start bit detection signal 24 are delayed by the delay circuit 31 until the transfer of both is completed, and the write signal 20 and the read signal are read. 27 and the flag reset signal 19 may be generated, and the processing procedure is the same.

Embodiment 4 FIG. FIG. 8 is a block diagram of the fourth embodiment. In the figure, 36 is a pulse generation circuit that generates a pulse when the input signal becomes significant, 37 is a pulse signal output from the pulse generation circuit 36, and 38 is the pulse signal 37 that is output as the write signal 20 or the read signal 27. It is a switching circuit that selects whether to perform the stop bit detection signal as a switching signal.

FIG. 9 shows a timing chart of the data write cycle of the fourth embodiment, and FIG. 10 shows a timing chart of the data read cycle of the fourth embodiment. First, consider the data write cycle in FIG. In the case of data writing, when the address and data are transmitted from the CPU unit 1 and the serial data signal 12 is received, the stop bit detection circuit 28 detects the stop bit. Since the stop bit is detected when a certain time or more has elapsed since the data became significant, the detection of the stop bit takes time until the serial data signal 12 is converted into parallel, as in the second embodiment. I will do it. The pulse generation circuit 36 generates a pulse signal 37 when the stop bit detection signal 29 becomes significant. In the case of data writing, the start bit detection signal 30 becomes significant, and the switching circuit 38 outputs the pulse signal 37 as the write signal 20 at this time. At that time, the data output from the UART 9 is written to the address output from the UART 8. Thereafter, the delay circuit 33 outputs the flag reset signal 19 later than the write signal 20, resets the UART8, the UART9 and the stop bit detection circuit 22 at T34, and the memory unit 11 side waits for the next serial data signal 12. Become. Summarizing these operations, the time required to write data is the same as that in the first embodiment and is expressed by the equation (3).

Comparing the equation (3) with the equation (1) as described above, the processing speed of this embodiment is improved by 4 times as compared with the conventional example.

Next, consider the data read cycle in FIG. In the data read cycle, only the address is transmitted from the CPU unit 1. Therefore, the stop bit detection signal 29 becomes significant, but the stop bit detection signal 30 does not become significant. Similar to the data write cycle, the pulse generation circuit 36 generates the pulse signal 37 when the stop bit detection signal 29 becomes significant.
In the case of data reading, the stop bit detection signal 30 does not become significant, so the switching circuit 38 outputs the pulse signal 37 as the read signal 27. Then UAR
The data of the address output from T8 is RAM13.
Is read from. The read signal 27 is extended and input to the RAM 13 by the extension circuit 47.
When 7 is input to the UART 9 as the transmission signal 39, the data output to the data bus 15 at the rising edge of the transmission signal 39 is serially transferred to the CPU unit 1. T3
The processing procedure for resetting the reception flag 16 in 4 and setting the next serial data signal 12 in the waiting state is the same as that in the data write cycle. Summarizing these operations, the time required to read the data is the same as that in the third embodiment and is expressed by the equation (5).

Therefore, comparing equation (5) with equation (2),
In this embodiment, the processing speed is improved by 6 hours compared to the conventional example.

The case of writing data to the memory unit 11 and the case of reading data from the memory unit 11 have been described, but the processing procedure is the same even when the memory unit 11 is an external input / output device. In addition, no matter how the bit lengths of the address and data change, it takes time for the transfer of both to be completed, the stop bit detection circuit 28 detects the stop bit, and the write signal 2
0, the read signal 27 and the flag reset signal 19 may be generated, and the processing procedure is the same.

Example 5. FIG. 11 shows a fifth embodiment of the present invention.
FIG. In the figure, 40 is a gate whose output is significant only when the start bit detection signal 23 is significant and the start bit detection signal 24 is not significant,
41 is a write trigger signal output from the gate 40, 42
Is a read trigger signal output from the gate 40, 43 is a delayed write trigger signal obtained by delaying the write trigger signal 41 until the serial data signal 12 is converted into parallel by the delay circuit 31, and 44 is delayed the read trigger signal 42. A delayed read trigger signal delayed until the serial data signal 12 is converted into parallel in the circuit 31, 45 is a filter that allows only a certain pulse width to pass, and 46 is a filter that allows only a certain pulse width to pass.

FIG. 12 shows a timing chart of the data write cycle of the fifth embodiment, and FIG. 13 shows a timing chart of the data read cycle of the fifth embodiment.
First, consider the data write cycle in FIG. When writing data, the CPU unit 1 divides the upper address bits from the UART 8 and the lower address bits from the UART 9 and transmits the divided data. An address transmission timing is preliminarily agreed between the CPU unit 1 and the memory unit 11. For example, when writing data, the upper bit of the address and the lower bit of the address are shifted by 1 bit and transmitted, and when reading the data, The upper bits of the address and the lower bits of the address are shifted by 2 bits before transmission. In the memory unit 11, the start bit detection circuit 22 detects the start bit and makes the start bit detection signal 23 and the start bit detection signal 24 significant at their respective timings. Since the output of the gate 25 is significant only when the start bit detection signal 23 is significant and the start bit detection signal 24 is not significant, a pulse of 1 bit width transmitted by shifting is written to the write trigger signal 41 and the read trigger signal. It outputs as 42. Output light trigger signal 41
The read trigger signal 42 is delayed by the delay circuit 31. In the data write cycle, data is further transmitted from the CPU unit 1 via the UART 9 after the address is received, and therefore the delay time is t4 when the UART 9 is t4.
Until the reception processing of the data received in 1 is completed. After that, the delayed write trigger signal 43 and the delayed read trigger signal 44 are input to the filter 45 and the filter 46, respectively. If the filter 45 passes only the pulse of 1-bit width and the filter 46 passes only the pulse of 2-bit width, the signal output to the RAM 13 is only the write signal 20 passed through the filter 45. In this way, the data writing to the RAM 13 is executed. After that, as in the other embodiments, the memory unit 11
After the end of the processing in, the flag reset signal 19 is set to U at T44.
ART8, UART9 and start bit detection circuit 22
To reset the reception flag 16. The memory unit 11 side waits for the next serial data signal 12. Summarizing these operations, the time required to write data is as shown in Equation 7. T21 + T41 + 2 × T2 + T3 + 2 × T4 + T5 + T7 (7)

By comparing equation (7) with equation (1) as described above, the processing speed of this embodiment is improved by the time equation (8) as compared with the conventional example. T11 + T31 + 2 × T2 + 2 × T4 + 2 × T7 (8)

Next, consider the data read cycle in FIG. In the data read cycle, the upper bits of the address and the lower bits of the address are shifted by 2 bits and transmitted from the CPU unit 1. First, similarly to the data write cycle, the start bit detection signal 23 and the start bit detection signal 24 become significant, and the delayed write trigger signal 43 and the delayed read trigger signal 44 are input to the filter 45 and the filter 46, respectively. Since the UART 8 and the UART 9 receive the serial data signal 12 with a 2-bit shift, the delay write trigger signal 43 and the delay read trigger signal 44 have a pulse width of 2 bits. Therefore, the delayed write trigger signal 43 does not pass through the filter 45, and only the delayed read trigger signal 44 passes through the filter 46 and is output. After that, the read signal 27 is input to the UART 9 as the transmission signal 39 as in the other embodiments. In addition, RAM13
The extension read signal 48 extended by the extension circuit 47 is input to the so that the data is output to the data bus 15 while the UART 9 is transmitting the data. And T24
The procedure for resetting the reception flag 16 and resetting the next serial data signal 12 is the same as that in the data write cycle. Summarizing these operations, the time required to write data is as shown in equation (9). T21 + T2 + T3 + T4 + T6 (9)

By comparing the equation (9) with the equation (2) as described above, the processing speed of the present embodiment is improved by 10 times as compared with the conventional example. T11 + T31 + 2 × T2 + 2 × T4 + 2 × T7 (10)

The case of writing data to the memory unit 11 and the case of reading data from the memory unit 11 have been described, but the processing procedure is the same even when the memory unit 11 is an external input / output device. In addition, no matter how the bit lengths of the address and data change, the start bit detection signal 23 and the start bit detection signal 24 are delayed by the delay circuit 31 until the transfer of both is completed, and the write signal 20 and the read signal are read. The signal 27 and the flag reset signal 19 may be generated, and the processing procedure is the same.

[0046]

According to the first embodiment of the present invention, an address and data are transmitted and received by dedicated UARTs, and a write signal is generated from a start bit of a serial data signal which becomes significant at the time of data reception. The output processing speed can be improved.

Further, according to the second embodiment of the present invention, the address and the data are transmitted and received by the dedicated UARTs, respectively.
By generating the write signal from the stop bit of the serial data signal which becomes significant at the time of receiving the data, the data input / output processing speed can be improved.

Further, according to the third embodiment of the present invention, the write signal and the read signal are obtained by combining the start bit of the serial data signal received by the address transmission / reception dedicated UART and the start bit of the serial data signal received by the data transmission / reception only UART. By generating, the data input / output speed can be improved.

Further, according to the fourth embodiment of the present invention, the write signal and the read signal are combined by the combination of the stop bit of the serial data signal received by the address transmission / reception dedicated UART and the stop bit of the serial data signal received by the data transmission / reception only UART. By generating, the data input / output speed can be improved.

Further, according to the fifth embodiment of the present invention, the start bit and address of the serial data signal received by the address transmission / reception dedicated UART and the UAR for data transmission / reception.
By generating the write signal and the read signal using the timing of the start bit of the serial data signal received at T, it is possible to improve the data input / output speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart of the first embodiment of the present invention.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a timing chart of the second embodiment of the present invention.

FIG. 5 is a block diagram showing a third embodiment of the present invention.

FIG. 6 is a timing chart of a data write cycle according to the third embodiment of the present invention.

FIG. 7 is a timing chart of a data read cycle according to the third embodiment of the present invention.

FIG. 8 is a block diagram showing a fourth embodiment of the present invention.

FIG. 9 is a timing chart of a data write cycle according to the fourth embodiment of the present invention.

FIG. 10 is a timing chart of a data read cycle according to the fourth embodiment of the present invention.

FIG. 11 is a block diagram showing a fifth embodiment of the present invention.

FIG. 12 is a timing chart of a data write cycle according to the fifth embodiment of the present invention.

FIG. 13 is a timing chart of a data read cycle according to the fifth embodiment of the present invention.

FIG. 14 is a block diagram of a conventional example.

FIG. 15 is a timing chart of a conventional example.

[Explanation of symbols]

1 CPU unit, 2 CPU, 3 ROM, 4 address bus, 5 data bus, 6 read signal, 7 transmission signal, 8 UART, 9 UART, 10 external I / F
Circuit, 11 memory unit, 21 serial data signal, 13 RAM, 14 address bus, 15 data bus, 16 reception flag, 17 write signal pulse generation circuit, 18 reset pulse generation circuit, 19 flag reset signal, 20 write signal, 21 reception Flag, 2
2 start bit detection circuit, 23 start bit detection signal, 24 start bit detection signal, 25 gate, 26 read signal pulse generation circuit, 27 read signal, 28 stop bit detection circuit, 29 stop bit detection signal, 30 stop bit detection signal, 31
Delay circuit, 32 Delayed start bit detection signal, 33
Delay circuit, 34 Delayed start bit detection signal, 35
Mask signal, 36 pulse generation circuit, 37 pulse signal,
38 switching circuit, 39 transmission signal, 40 gates,
41 read trigger signal, 42 write trigger signal, 4
3 delayed read trigger signal, 44 delayed write trigger signal, 45 filter, 46 filter, 47 extension circuit, 48 extension read signal, 49 CPU, 50 RO
M.

Claims (5)

[Claims] 1. A communication interface circuit used when data is written from a central processing unit to an external memory or an external output device by serial communication. Address transmission / reception for transmitting / receiving an address to be written between the central processing unit and the external memory or external output device. A general-purpose asynchronous transmitter-receiver circuit dedicated to this address, a general-purpose asynchronous transmitter-receiver circuit dedicated to data transmission / reception that transmits / receives data to be written to an address transmitted / received by this general-purpose asynchronous transmitter-receiver circuit dedicated to address transmission / reception, and a serial transmitted / received by the general-purpose asynchronous transmitter-receiver circuit dedicated to address transmission / reception above A start bit detection circuit that detects the start bit of the data signal or the start bit of the serial data signal transmitted / received by the general-purpose asynchronous transmission / reception circuit dedicated to data transmission / reception and the address received by the general-purpose asynchronous transmission / reception circuit dedicated to address transmission / reception. A communication interface circuit, comprising: a write signal pulse generation circuit that generates a write signal for writing data received by a general-purpose asynchronous transmission / reception circuit dedicated to data transmission / reception. 2. In a communication interface circuit used when data is written from a central processing unit to an external memory or an external output device by serial communication, address transmission / reception for transmitting / receiving an address to be written between the central processing unit and the external memory or external output device. A general-purpose asynchronous transmitter-receiver circuit dedicated to this address, a general-purpose asynchronous transmitter-receiver circuit dedicated to data transmission / reception that transmits / receives data to be written to an address transmitted / received by this general-purpose asynchronous transmitter-receiver circuit dedicated to address transmission / reception, and a serial transmitted / received by the general-purpose asynchronous transmitter-receiver circuit dedicated to address transmission / reception above A stop bit detection circuit that detects the stop bit of the data signal and the start bit of the serial data signal transmitted / received by the general-purpose asynchronous transmission / reception circuit dedicated to data transmission / reception, and the address received by the general-purpose asynchronous transmission / reception circuit dedicated to address transmission / reception. And a gate for generating a write signal for writing data received by a general-purpose asynchronous transmission / reception circuit dedicated to transmission / reception of data. 3. A communication interface circuit used when data is written or read from a central processing unit to an external memory or an external output device by serial communication, and an address to be written is transmitted and received between the central processing unit and the external memory or external output device. A general-purpose asynchronous transceiver circuit dedicated to address transmission / reception, a general-purpose asynchronous transceiver circuit dedicated to data transmission / reception that transmits / receives data to be written to an address transmitted / received by this general-purpose asynchronous transceiver circuit dedicated to address transmission / reception, and the general-purpose asynchronous transceiver circuit dedicated to address transmission / reception described above. Start bit detection circuit for detecting the start bit of the transmitted / received serial data signal and the start bit of the serial data signal transmitted / received by the general-purpose asynchronous transmission / reception circuit dedicated to data transmission / reception, and reception by the general-purpose asynchronous transmission / reception circuit dedicated to address transmission / reception A write signal pulse generation circuit that generates a write signal for writing the data received by the general-purpose asynchronous transmission / reception circuit dedicated to data transmission / reception to the address
A communication interface circuit comprising: a read signal pulse generation circuit for generating a read signal for reading data of an address received by a general-purpose asynchronous transmission / reception circuit dedicated to address transmission / reception. 4. A communication interface circuit used when data is written or read from a central processing unit to an external memory or an external output device by serial communication, and an address to be written is transmitted and received between the central processing unit and the external memory or external output device. A general-purpose asynchronous transceiver circuit dedicated to address transmission / reception, a general-purpose asynchronous transceiver circuit dedicated to data transmission / reception that transmits / receives data to be written to an address transmitted / received by this general-purpose asynchronous transceiver circuit dedicated to address transmission / reception, and the general-purpose asynchronous transceiver circuit dedicated to address transmission / reception described above. Start bit detection circuit for detecting the start bit of the transmitted / received serial data signal and the start bit of the serial data signal transmitted / received by the general-purpose asynchronous transmission / reception circuit dedicated to data transmission / reception, and reception by the general-purpose asynchronous transmission / reception circuit dedicated to address transmission / reception And a pulse generation circuit that generates a write signal for writing data received by the general-purpose asynchronous transmission / reception circuit dedicated to data transmission / reception and a read signal for reading data at the address received by the general-purpose asynchronous transmission / reception circuit dedicated to address transmission / reception. A communication interface circuit characterized by being provided. 5. A communication interface circuit used when data is written or read from a central processing unit to an external memory or an external output device by serial communication, and an address to be written between the central processing unit and the external memory or external output device is transmitted and received. A general-purpose asynchronous transmitter-receiver circuit dedicated to address transmission / reception, a general-purpose asynchronous transmitter-receiver circuit for data transmission / reception that transmits / receives an address and data written in the address transmitted / received by the general-purpose asynchronous transmitter-receiver circuit dedicated to address transmission / reception, and a general-purpose asynchronous transmitter-receiver circuit dedicated to address transmission / reception The start bit of the serial data signal transmitted / received in and the start bit detection circuit that detects the start bit of the serial data signal transmitted / received by the general-purpose asynchronous transmission / reception circuit dedicated to data transmission / reception and the general-purpose asynchronous transmission / reception circuit dedicated to address transmission / reception Generates a write signal to write the data received by the general-purpose asynchronous transceiver circuit dedicated to data transmission / reception to the received address, and a read signal to read the data at the address received by the general-purpose asynchronous transceiver circuit dedicated to address transmission / reception And a communication interface circuit.