JPH08186272A - Tunnel transistor - Google Patents

Abstract

PURPOSE: To enlarge peak/valley ratio in N-type negative resistance characteristic and to control diffusion current at a gate. CONSTITUTION: In a surface area of a semiinsulation GaAs substrate 11, an n<+> -type GaAs source area 12 and p<+> -type InGaAs drain area 13 are formed. On a channel area, an n-type AlGaAs electron supply layer 14 is provided, and on tap of it a gate electrode 15 is farmed. On the source and drain areas, a source electrode 16 and a drain electrode 17 are formed. So that n<+> -p<+> tunnel joint is formed between channel drain, and, since the drain area becomes narrow forbidden band width, tunnel current is increased, so that peak/valley ratio is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect type tunnel transistor, and more particularly to a structure of a tunnel transistor having a large peak-to-valley ratio, a negative resistance characteristic and a wide operating margin. This tunnel transistor is used as a basic element of an ultra-high integrated circuit.

[0002]

2. Description of the Related Art In order to realize a high-performance semiconductor integrated circuit, high-performance and multifunctional transistors are required. One that can realize multiple functions is p on the semiconductor surface.
Ordinary Si that utilizes the tunneling phenomenon at the ⁺ -n ⁺ junction
A field-effect tunnel transistor having an operation principle different from that of a MOSFET or a GaAs MESFET has been proposed.

This device is described, for example, in Japanese Patent Application Laid-Open No. 58-96766 (Japanese Patent Publication No. 6-12821) and Japanese Patent Application Laid-Open No. 5-41520, which are filed by the present applicant. This transistor positively utilizes the tunnel effect, which is a problem in the limit of miniaturization of MOSFETs, and can realize a multifunctional operation by utilizing a negative resistance characteristic together with a structure suitable for miniaturization.
It is possible to increase the density of an integrated circuit.

FIG. 4 is a schematic sectional view of a conventional tunnel transistor of this type. In the figure, 31 is a semi-insulating GaAs substrate, 32 is an n ⁺ -type GaAs source region, 3
3 is a p ⁺ type GaAs drain region, 34 is an intrinsic AlGaAs insulating layer made of undoped Al _0.5 Ga _0.5 As, 35 is a gate electrode made of Al, and 36 and 37 are A
and a source electrode and a drain electrode which are in ohmic contact with the source region and the drain region, respectively.

FIG. 5 is a band diagram between a channel region and a drain region formed on the substrate surface below the gate of the conventional tunnel transistor shown in FIG. 4, where Ec is the conduction band edge and Ev is the valence band edge. , Ef is Fermi level, Ecf
Is the energy difference from the Fermi level of the channel region to the conduction band of the drain region, and Evf is the energy difference from the Fermi level of the drain region to the valence band of the channel region.

Next, the operation of this conventional tunnel transistor will be described with reference to FIGS. When the source electrode 36 is set to the ground potential, no voltage is applied to the gate electrode 35, and a positive voltage is applied to the drain electrode 37, n
^A forward bias is applied between the ⁺ type GaAs source region 32 and the p ⁺ type GaAs drain region 33 via the substrate.
In this bias direction, the drain current flows more easily than in the reverse bias, but if the diffusion current of carriers is not more significant (0.7 V or less for GaAs), almost no current will flow.

[0007] Next, the application of a large positive voltage to the gate electrode 35, a potential well is formed is lowered the potential of the substrate surface between the source and drain, 10 ¹²
A channel region where electrons of about cm ⁻² are accumulated is formed. As a result, this channel region becomes a degenerated semiconductor due to a high electron concentration, and is equivalent to n ⁺ -type GaAs. Therefore, the n ⁺ -type GaAs source region 32 and the channel region are brought into a complete conduction state.

On the other hand, a channel region and a drain region (p ⁺
Type GaAs), a junction (tunnel junction) similar to an Esaki diode (tunnel diode) is formed as shown in FIG. When a small forward voltage is applied between the source and the drain, electrons in the conduction band of the channel region tunnel to an empty state of the valence band of the drain region, so that a current increases according to the forward voltage. .

When the source-drain voltage increases, the energy overlap between the conduction band and the valence band decreases, so that the current once decreases. When the voltage is further increased, electrons in the conduction band in the channel region and holes in the drain region thermally cross the potential barrier (Ecf, Evf), and the current (diffusion current) increases again. At this time, since the drain region needs to be designed to have a greater degree of degeneracy than the channel region, Ec
f is larger than Evf (50 meV-100
meV), a hole current mainly flows as a diffusion current.

Therefore, an N-type negative resistance characteristic appears in the current-voltage characteristic. Since the magnitude of the tunnel current depends on the concentration of electrons induced in the semiconductor channel layer, this negative resistance characteristic is controlled by the voltage applied to the gate electrode. A transistor having a function is obtained.

[0011]

In the above-mentioned conventional tunnel transistor, since a large diffusion current due to holes flows from the drain region to the channel region, the valley current (valley current) of the negative resistance characteristic is large. The peak-valley ratio, which is a performance index of the negative resistance characteristic, is small. This hole current is hardly controlled by the gate voltage. For this reason, the operating margin of the functional circuit using this element is narrowed, making it difficult to design the circuit.

The present invention has been made in view of this point, and its purpose is to firstly increase the peak-valley ratio, and secondly, to improve the controllability of the gate voltage with respect to the diffusion current. This is intended to provide a tunnel transistor with higher performance.

[0013]

According to the present invention, there is provided a non-doped or low-impurity-concentration first-conductivity-type channel region provided in contact with one end of the channel region. A first conductivity type source region;
A band structure formed in contact with the other end of the channel region and made of a semiconductor material having a bandgap narrower than the bandgap of the channel region, the band structure being degenerated by being highly doped with an impurity of the second conductivity type. A drain region, a carrier supply layer and / or an insulating layer provided on the channel region, a gate electrode formed on the carrier supply layer or the insulating layer, and on the source region and the drain. A tunnel transistor having a source electrode and a drain electrode respectively provided on the region is provided.

[0014]

In the tunnel transistor of the present invention, a semiconductor having a narrower bandgap than the channel region is used for the drain region. Therefore, the tunnel current increases, the diffusion current due to holes relatively decreases, and a large peak valley occurs. The ratio is obtained. Also, by using a semiconductor having a narrower bandgap width than the channel region in the drain region,
The ratio of the electron current to the diffusion current increases, and as a result, the controllability of the diffusion current by the gate voltage increases.

[0015]

Next, embodiments of the present invention will be described in detail with reference to the drawings. [First Embodiment] FIG. 1 is a cross-sectional view showing the layer structure of the first embodiment of the present invention. In FIG. 1, 11 is a semi-insulating GaAs substrate, 12 is an n ⁺ type GaAs source region, 13
Is In _0.15 Ga with an acceptor concentration of 5 × 10 ¹⁹ cm ^-3.
P ⁺ type InGaAs drain region composed of _0.85 As, 1
4 is an n-type AlG composed of n-type Al _0.5 Ga _0.5 As
aAs electron supply layer, 15 is a gate electrode made of Al, 1
Reference numerals 6 and 17 denote a source electrode and a drain electrode which are made of Au and are in ohmic contact with the source region and the drain region, respectively.

FIG. 2 is a band diagram between the channel region and the drain region formed on the substrate surface under the gate of the tunnel transistor of the present embodiment. Ec is the conduction band edge, Ev is the valence band edge, and Ef is The Fermi level, Ecf, is the energy difference from the Fermi level of the channel region to the conduction band of the drain region, and Evf is the energy difference from the Fermi level of the drain region to the valence band of the channel region.

Next, the operation of the tunnel transistor of this embodiment will be described with reference to FIGS. The difference between this example and the conventional example is that, firstly, the bandgap width of the drain region is narrower than that of the channel region (substrate), and secondly, the selective doping heterojunction is formed under the gate. It is the point that is formed. According to the second feature, the channel region is already in a depletion state in which electrons are accumulated in a state where no voltage is applied to the gate electrode. The concentration of electrons accumulated here is controlled by the voltage applied to the gate electrode 15.

A p ⁺ type InGaAs drain region (In
The band gap width of _0.15 Ga _0.85 As) 13 is about 1.2
eV and about 0. 5 than that of the channel region (GaAs).
It is 2 eV smaller. For this reason, the tunnel probability between the channel and the drain becomes much larger than the case where GaAs is used for the conventional drain, and the tunnel current increases. On the other hand, the diffusion current due to holes depends on Evf,
Since this size is almost the same as the case of the conventional example,
The diffusion current due to holes does not change. Therefore, the diffusion current due to holes is relatively reduced as compared with the tunnel current, and the peak-valley ratio is improved.

The degree of degeneration of the channel region varies with the gate voltage, but is about 50 meV at the maximum. Therefore, even if the degeneracy of the narrow band gap drain region is about 0.1 eV, Ecf becomes smaller than Evf by about 50 meV, and the diffusion current is mainly an electron current from the channel region. In such a situation, the valley current is determined by the electron diffusion current. However, since the valley current is a current component originally hidden by the hole current, the peak valley ratio is larger than that of the conventional example.

Since the diffusion current due to the electrons depends on the carrier concentration in the channel region, and the carrier concentration can be controlled by the gate voltage as described above, this current is controlled by the gate voltage. become. As described above, in the tunnel transistor of the present invention, not only the tunnel current but also the diffusion current can be controlled by the gate electrode, and the entire transistor characteristics having negative resistance characteristics can be controlled by the gate.

Next, the manufacturing method of the first embodiment of the present invention will be described. First, non-doped GaAs having a thickness of 500 nm is formed on a semi-insulating GaAs substrate by MBE (Molecular).
Beam Epitaxy) was used for the growth. The source region was dug by etching, and Se-doped n ⁺ -type GaAs was buried therein by a vapor phase epitaxy (VPE) method. Next, the drain region is etched, and Zn-doped p ⁺ -type In
_0.15 Ga _0.85 As was embedded by the VPE method. The source region may be formed by an impurity introduction method such as ion implantation instead of the embedding method. Further, the source region and the drain region may be buried by using a metal organic chemical vapor deposition (MOCVD) method instead of the VPE method.

Further, a 30 nm n-type A
1 _0.5 Ga _0.5 As was formed by the MBE method. Subsequently, an Al film serving as a gate electrode was deposited, and this Al film and n-type Al _0.5 Ga _0.5 As were processed into a gate shape.
Finally, an Au electrode was formed on the n ⁺ -type GaAs source region and the p ⁺ -type InGaAs drain region to complete the structure of the present embodiment.

In an element having a gate width of 10 μm, the peak-to-valley ratio of the negative resistance characteristic is 15 which is several times larger than that of the conventional device, and the transistor characteristic in which the tunnel current and the diffusion current are controlled by the gate voltage is obtained. Was done.

[Second Embodiment] FIG. 3 is a schematic view showing the layer structure of the second embodiment of the present invention. In FIG. 3, 2
1 is a semi-insulating GaAs substrate, 22 is an n ⁺ type GaAs source layer, 28 is an undoped GaAs channel layer, and 23 is p
Type In _0.15 Ga _0.85 As composed of p ⁺ type InGaAs
A drain layer, 24 is an n-type AlGaAs electron supply layer made of n-type Al _0.5 Ga _0.5 As, 25 is a gate electrode made of Al, and 26 and 27 are made of Au, which make ohmic contact with the source layer and the drain layer, respectively. A source electrode and a drain electrode.

The operation of the tunnel transistor of the second embodiment is the same as that of the first embodiment. Since this structure does not need to undergo a plurality of re-growth steps in its manufacturing process, it has advantages that it can be easily manufactured and that impurities are less taken in at the tunnel junction interface. In particular, the latter can further improve the peak-valley ratio.

Next, the manufacturing method of the second embodiment will be described. First, an MBE is placed on a semi-insulating GaAs substrate.
The n ⁺ -type GaAs layer serving as the source layer is
m, a non-doped GaAs layer serving as a channel layer having a thickness of 100 nm, and ap ⁺ -type In _{0.15 serving} as a drain layer.
Ga _0.85 As was continuously grown to a thickness of 200 nm. Etching up to the source layer and n ⁺ -ip ⁺
The side surface of the structure is exposed and n-type Al _0.5 G is formed by the MBE method.
a _0.5 As was regrown to a thickness of 30 nm. continue,
An Al film serving as a gate electrode is deposited and this Al film and n
A mold Al _0.5 Ga _0.5 As was processed into a gate shape. Finally, an Au electrode was formed on the n ⁺ -type GaAs source layer and the p ⁺ -type InGaAs drain layer to complete the structure of the present example.

In a device having a gate width of 10 μm, transistor characteristics in which the tunnel current and the diffusion current are controlled by the gate voltage are obtained, and the peak-to-valley ratio of the negative resistance characteristic is 20 which is larger than that of the first embodiment. Obtained.

[Modifications of Embodiments] The preferred embodiments have been described above, but the present invention is not limited to these embodiments, and various modifications can be made within the scope of the claims. . For example, in the embodiments, only GaAs or In _0.15 Ga _0.85 As has been shown as a semiconductor material for a substrate or a drain region having a narrow band gap width. However, Si, Ge, SiGe, InP, InGaAs,
Similar effects can be obtained by using other semiconductor materials such as GaSb.

The semiconductors of the substrate, the source region (layer), and the channel region (layer) do not necessarily have to be the same type of semiconductor that forms a homojunction, but may be heterogeneous semiconductors that form a heterojunction. Also, as the electron supply layer,
Instead of n-type AlGaAs, n-type InAlAs, In
Other semiconductor materials such as P, GaP, and AlGaP may be used. Also, instead of the electron supply layer, non-doped AlGa
Insulating semiconductors such as As, InAlAs, InP, and GaP, and SiO ₂ , Si ₃ N ₄ , AlN, and Al ₂ O
MIS (Metal-Insula) using an insulator such as ₃
tor-Semiconductor) An FET structure may be used. Further, the MIS is formed by combining an n-type semiconductor layer and an insulator.
S (Metal-Insulator-Semiconductor-Semiconductor)
An FET structure may be used.

Although only Al is shown as a gate electrode material, other metal materials or low-resistance semiconductor materials that form a Schottky junction may be used. Further, although the source and drain electrodes have only shown Au, other metal materials or low resistance semiconductor materials which form ohmic junctions with the source and drain regions may be used.

In the above embodiment, only the n-type conductivity type of the source and the channel is shown. However, the present invention can be applied to a structure in which the conductivity types of all the regions are reversed so that these regions become p-type. It is clear that it can be applied.

[0032]

As described above, in the field effect tunnel transistor according to the present invention, the n ⁺ -p ⁺ junction is formed between the channel region and the drain region, and the band gap width of the drain region is set to the semiconductor layer of the channel region. Since it is narrower than that, the tunnel current can be increased and the ratio of electrons in the diffusion current can be increased. Therefore, according to the present invention, a large peak-to-valley ratio can be obtained, the diffusion current can be controlled by the gate voltage, and a functional circuit having a large operation margin can be realized.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

FIG. 2 is a band diagram between the channel region and the drain region of the embodiment of FIG.

FIG. 3 is a sectional view showing a second embodiment of the present invention.

FIG. 4 is a sectional view of a conventional example.

FIG. 5 is a band diagram between a channel region and a drain region in the conventional example of FIG. 4;

[Explanation of Codes] 11, 21, 31 Semi-insulating GaAs substrate 12, 32 n ⁺ type GaAs source region 22 n ⁺ type GaAs source layer 13 p ⁺ type InGaAs drain region 23 p ⁺ type InGaAs drain layer 33 p ⁺ type GaAs Drain region 14, 24 n-type AlGaAs electron supply layer 34 intrinsic AlGaAs insulating layer 15, 25, 35 gate electrode 16, 26, 36 source electrode 17, 27, 37 drain electrode 28 non-doped GaAs channel layer Ec conduction band edge Ev valence band Edge Ef Fermi level Ecf Conduction band edge-Fermi level energy Evf Valence band Edge-Fermi level energy

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 29/812

Claims (3)

[Claims] 1. A non-doped or low impurity concentration first conductivity type channel region, a first conductivity type source region provided in contact with one end of the channel region, and the other end of the channel region. A drain region which is formed of a semiconductor material having a bandgap narrower than the bandgap of the channel region, the drain region having a degenerate band structure doped with a second conductivity type impurity at a high concentration, A carrier supply layer and / or an insulating layer provided on the channel region, a gate electrode formed on the carrier supply layer or the insulating layer, and a source region and a drain region, respectively. A tunnel transistor having a source electrode and a drain electrode. 2. The semiconductor device according to claim 1, wherein said source region and said drain region are formed in a surface region of a non-doped or low-impurity-concentration first conductivity type semiconductor substrate constituting said channel region. Item 7. The tunnel transistor according to Item 1. 3. The semiconductor device according to claim 2, wherein the source region, the channel region, and the drain region are stacked in this order on the semiconductor substrate, and the carrier supply layer or the insulating layer is formed on a side surface of the channel region. The tunnel transistor according to claim 1, wherein