JPH08153391A - Dynamic ram - Google Patents

Abstract

PURPOSE: To relax the design criteria of a sense amplifier and to shorten a precharge time by arranging the cell array of a loop back bit line structure in the prolonging direction of a bit line and allocating the sense amplifiers on both sides of the prescribed cell array at every one bit line pair. CONSTITUTION: The cell array of the loop back bit line structure is arranged in the prolonging direction of the bit line, and the shared type sense amplifiers are allocated on both sides at every one bit line pair related to the cell array except the cell array of both sides. For instance, the shared type sense amplifiers 1300 -130n , 1310 -131n , are allocated on both sides of the cell array 122 at every one bit line pair. Further, a bit line precharge circuit is provided adjacent to the sense amplifier. For instance, the bit line precharge circuits 1260 -126n , 1270 -127n , 1280 -128n , 1290 -129n are provided adjacent to the sense amplifiers 1300 -130n , 1310 -131n .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic RAM (dynamic random access memory) (hereinafter referred to as DRAM) among semiconductor memory devices.

Generally, in a DRAM, in order to improve the manufacturing yield, there is a so-called redundancy technique in which spare cells are redundantly formed in addition to regular memory cells and defective cells are replaced with spare cells. Has been adopted.

However, since this redundancy technique is difficult to apply to a control circuit that controls reading and writing from and to a memory cell, a design standard that is looser than that of the memory cell is set for the control circuit so that defects are less likely to occur. Has been

Therefore, there is an inconvenience that the ratio of the area occupied by the control circuit to the memory cell increases on the chip surface, and a countermeasure against this is required.

Further, in DRAM, memory cells have been miniaturized, but the miniaturization of memory cells is
This causes an increase in wiring resistance and capacitance, which is an obstacle to speeding up.

Particularly in the recent DRAM, the precharge voltage of the bit line is set to 1 / 2.VCC, so that the gate voltage of the transistor forming the bit line precharge circuit cannot be sufficiently secured at the time of precharging the bit line. , Causing an increase in bit line precharge time,
This measure is also required.

[0007]

2. Description of the Related Art Conventionally, as a DRAM, for example, FIG.
Has been proposed in which a schematic plan view of a part thereof is shown.

This DRAM includes a cell array having a folded bit line structure, that is, a cell array having two bit lines extending in parallel as a pair, and a shared type sense amplifier, that is, two cells. A sense amplifier is provided between the arrays so as to correspond to these two cell arrays and is controlled so as to perform an amplifying operation on the selected cell array.

In FIG. 5, 1 and 2 are cell arrays of folded bit line structure, BL _1-0 , / BL _1-0 , BL _1-1 , / BL.
_1-1 , BL _1-n , / BL _1-n , BL _2-0 , / BL _2-0 , BL
_2-1 , / BL _2-1 , BL _2-n , / BL _2-n are bit lines.

Further, 3 ₀ , 3 ₁ , 3 _n , 4 ₀ , 4 ₁ , 4 _n are bit line precharge circuits for precharging bit lines, 5 ₀ , 5 ₁ , 5 _n are shared type sense amplifiers. Is.

FIG. 6 is a circuit diagram partially showing the circuit configuration of the portion shown in FIG. 5. In the cell arrays 1 and 2, WL _1-0 and WL _2-0 are word lines.

Further, 7 to 10 are memory cells, and 1
1 to 14 are capacitors for accumulating charges, and 15 to 18 are nMOS transistors (transfer transistors) for controlling input / output of charges.

The bit line precharge circuits 3 ₀ , 3 _n
, 19 is a bit line precharge signal line for transmitting the bit line precharge signal PC ₁ and 20 to 23 are nMOS transistors whose conduction and non-conduction are controlled by the bit line precharge signal PC ₁ (bit line precharge.
Transistors) and 24 are bit line precharge voltage lines for supplying 1/2 · VCC as the bit line precharge voltage.

The bit line precharge circuits 4 ₀ , 4 _n
, 25 is a bit line precharge signal line for transmitting the bit line precharge signal PC ₂ , and 26 to 29 are nMOS transistors whose conduction and non-conduction are controlled by the bit line precharge signal PC _2.
Transistors) and 30 are bit line precharge voltage lines for supplying 1/2 · VCC as the bit line precharge voltage.

In the sense amplifiers 5 ₀ and 5 _n , 3
Reference numerals ₁₀ and 31 _n are flip-flop circuits forming an amplifier circuit, 32 to 35 are pMOS transistors, and 36 to 3
Reference numeral 9 is an nMOS transistor.

Reference numeral 40 designates pMOS transistors 32 to.
35, etc., the sense amplifier drive voltage PSA is applied to the pMOS transistors forming the flip-flop circuits 31 _{0 to} 31 _n.
It is a sense amplifier drive voltage line for supplying (power supply voltage on the high voltage side).

Further, 41 is an nMOS transistor 36 to.
The sense amplifier drive voltage NSA is applied to the nMOS transistors that form the flip-flop circuits 31 _{0 to} 31 _n , such as 39.
It is a sense amplifier drive voltage line for supplying (power supply voltage on the low voltage side).

Further, 42 ₀ and 42 _n are isolation circuits, 43 is an isolation signal line for transmitting an isolation signal ISO ₁ , and 44 to 47 are controlled to be conductive or non-conductive by the isolation signal ISO _1. n
It is a MOS transistor (isolation transistor).

Further, 48 ₀ and 48 _n are isolation circuits, 49 is an isolation signal line for transmitting an isolation signal ISO ₂ , and 50 to 53 are controlled to be conductive or non-conductive by the isolation signal ISO _2. n
It is a MOS transistor (isolation transistor).

Reference numerals 54 ₀ and 54 _n are bit line precharge circuits, and 55 is a bit line precharge signal PC _3.
Bit line precharge signal lines for transmitting, 56 and 57 conductive by bit line precharge signal PC _3, an nMOS transistor nonconductive is controlled (bit line precharge transistor).

DB and / DB are data buses, 5
8 ₀ and 58 _n are column selection circuits, and 59 and 60 are nM whose conduction and non-conduction are controlled by the column selection signal CL _0.
The OS transistors 61 and 62 are column selection signals CL _n
Is an nMOS transistor whose conduction and non-conduction are controlled by.

Generally, in a DRAM, 1
Cell data is read to one of the pair of bit lines precharged to / 2 · VCC, and the difference between the cell data is amplified by the sense amplifier using the voltage of the other bit line as a reference voltage.

The amplified cell data is stored in the memory cell again.
When the cell is written and the word line is brought low, access to the memory cell is terminated and then the bit line is precharged to 1 / 2.VCC in preparation for the next read operation.

By the way, in the DRAM shown in FIG. 5 (FIG. 6), the sense amplifier 5 ₀ to 5 _n, in order to improve the area efficiency, are shared by two cell arrays 1 and 2,
The isolation circuits 42 _{0 to} 42 _n and 48 _{0 to} 48 _n are selectively connected to the bit line of either one of the cell arrays.

Further, the bit line precharge circuit 3 ₀ on the opposite side of the sense amplifier 5 ₀ to 5 _n across the cell array 1
Provided with a to 3 _n, the bit line precharge circuit 4 on the opposite side of the sense amplifier 5 ₀ to 5 _n across the cell array 2
₀ to 4 _n are provided.

As a result, in the DRAM shown in FIG. 5 (FIG. 6), it is necessary to lay out one sense amplifier at a pitch of two bit lines, which makes the design standard of the sense amplifier strict and the manufacturing yield. Was a factor that lowers.

Therefore, conventionally, a DRAM has been proposed in which a schematic plan view of a part thereof is shown in FIG.

In this DRAM, a cell array having a folded bit line structure is arranged and shared type sense amplifiers are arranged so as to reduce the arrangement pitch.

In FIG. 7, reference numerals 64-66 denote cell arrays having a folded bit line structure, BL _64-0 to / BL _64-4 , BL.
_65-0 to / BL _65-4 and BL _66-0 to / BL _66-4 are bit lines.

[0030] In addition, 67 _{0-67 2,} 68 _{0-68 2} is a shared sense amplifier, the sense amplifier 67 ₀ ~
67 ₂ and the sense amplifiers 68 _{0 to} 68 ₂ are arranged with the arrangement pitch shifted by 1/2.

FIG. 8 is a circuit diagram partially showing the circuit configuration of the portion shown in FIG. 7, in which cell arrays 64 and 65 are provided.
In, WL _64-0, WL _65-0 is the word line.

Further, 70 to 73 are memory cells,
74 to 77 are capacitors for accumulating charges, 78 to 81
Is an nMOS transistor (transfer transistor) that controls the input / output of charges.

In the sense amplifiers 67 ₀ and 67 ₂ , 82 ₀ and 82 ₂ are flip-flop circuits, and 83
To 86 are pMOS transistors, 87 to 90 are nMOS
It is a transistor.

Further, 91 is a pMOS transistor 83-
The sense amplifier drive voltage PSA (power supply voltage on the high voltage side) is applied to the pMOS transistors constituting the flip-flop circuits 82 _{0 to} 82 _n (flip-flop circuits 82 ₁ , 82 _{3 to} 82 _n are not shown) such as 86. Is a sense amplifier drive voltage line for supplying

Further, 92 is an nMOS transistor 87-
90 and the like, the sense amplifier drive voltage NSA is applied to the nMOS transistors forming the flip-flop circuits 82 _{0 to} 82 _n.
It is a sense amplifier drive voltage line for supplying (power supply voltage on the low voltage side).

Further, 93 _0, 93 ₂ is a bit line precharge circuit 94 is a precharge signal line for transmitting a bit line precharge signal PC, 95 to 100 is turned on by the bit line precharge signal PC, the non-conductive Controlled nMOS transistor (bit line precharge transistor), 101 is 1 / 2.V as precharge voltage
It is a precharge voltage line that supplies CC.

Further, 102 ₀ and 102 ₂ are isolation circuits, and 103 is an isolation signal ISO ₁
Is an nMOS transistor (isolation transistor) whose conduction and non-conduction are controlled by the isolation signal ISO ₁ .

Further, 108 ₀ and 108 ₂ are isolation circuits, and 109 is an isolation signal ISO ₂
Is an nMOS transistor (isolation transistor) whose conduction and non-conduction are controlled by an isolation signal ISO ₂ .

DB and / DB are data buses and 114
₀ and 114 ₂ are column selection circuits, 115 and 116 are nMOS transistors whose conduction and non-conduction are controlled by a column selection signal CL ₀ , and 117 and 118 whose conduction and non-conduction are controlled by a column selection signal CL _2. It is an nMOS transistor.

In the DRAM shown in FIG. 7 (FIG. 8), the cell arrays having the folded bit line structure are arranged in the extending direction of the bit lines, and the cell arrays except the cell arrays on both sides are arranged on both sides. In addition, since shared sense amplifiers are allocated to both sides of the cell array for each bit line pair, the arrangement pitch of the sense amplifiers can be relaxed and the design standard of the sense amplifiers can be relaxed.

[0041]

However, in the DRAM shown in FIG. 7 (FIG. 8), the side opposite to the sense amplifier with the cell array interposed, for example, the alternate long and two short dashes line 119 in FIG.
When arranging the bit line precharge circuit in the area indicated by, it is impossible to relax the sense amplifier design standard by narrowing the width of the sense amplifier in the bit line extending direction. A bit line precharge circuit is provided.

Therefore, when precharging the bit line, in the supply path of the bit line precharge voltage, the on resistance of the nMOS transistor forming the bit line precharge circuit is connected to the nMOS forming the isolation circuit. Since the on resistance of the transistor is also added, there is a problem that the precharge of the bit line is delayed.

In view of the above points, the present invention provides a DRAM in which the relaxation of the design standard of the shared type sense amplifier is ensured and the precharge time of the bit line can be shortened. To aim.

[0044]

A DRAM according to the present invention
Arranging three or more cell arrays of folded bit line structure in the extending direction of the bit lines. For cell arrays except for cell arrays on both sides, shared bit lines are shared on each side. Type sense amplifiers are allocated, and bit line precharge circuits are provided adjacent to these sense amplifiers.

[0045]

In the present invention, the folded bit line structure 3 is used.
Arranging more than one cell array in the extending direction of the bit line,
With respect to the cell arrays other than the cell arrays on both sides, shared type sense amplifiers are assigned to each bit line pair on both sides, so that the arrangement pitch of the sense amplifiers can be relaxed.

Moreover, since the bit line precharge circuit is provided adjacent to the sense amplifier, a sufficient width can be secured as the width of the sense amplifier in the bit line extending direction.

As described above, according to the present invention, it is possible to secure the relaxation of the arrangement pitch of the sense amplifiers, and further to secure a sufficient width in the extending direction of the bit lines of the sense amplifiers. Therefore, the relaxation of the sense amplifier design standard can be ensured.

Further, according to the present invention, since the bit line precharge circuit is provided adjacent to the sense amplifier, the isolation circuit provided in the sense amplifier is configured when the bit line is precharged. Since the bit line can be precharged without passing through the transistor, the precharge time of the bit line can be shortened.

[0049]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first embodiment of the present invention will now be described with reference to FIGS.
An example and a second example will be described.

First Embodiment ... FIG. 1 and FIG. 2 FIG. 1 is a plan view schematically showing a part of the first embodiment of the present invention. In FIG. 1, 121 to 123 are cells having a folded bit line structure.・ Array, BL _121-0 ~ / BL _121-4 , BL
_122-0 to / BL _122-4 and BL _123-0 to / BL _123-4 are bit lines.

Further, 126 _{0 to} 126 ₂ and 127 _{0 to} 12
7 ₂ , 128 _{0 to} 128 ₂ , 129 _{0 to} 129 ₂ are bit line precharge circuits.

Further, 130 _{0 to} 130 ₂ , 131 _{0 to} 13
Reference numeral ₁₂ denotes a shared type sense amplifier, which includes sense amplifiers 130 _{0 to} 130 _n (sense amplifiers 130 _{3 to} 130 _n are not shown) and sense amplifiers 131 _{0 to} 131 _0.
1 _n (the sense amplifiers 131 _{3 to} 131 _n are not shown) are arranged with the arrangement pitch shifted by ½.

Further, 132 generates a bit line precharge signal PC ₁ and the bit line precharge circuits 126 ₀ to 1
26 _n (bit line precharge circuits 126 _{3 to} 126 _n are not shown) is a bit line precharge transistor control circuit for controlling conduction / non-conduction of nMOS transistors.

Further, 133 generates a bit line precharge signal PC ₂ , and the bit line precharge circuits 127 ₀ to 127 ₀ -1.
27 _n (bit line precharge circuits 127 _{3 to} 127 _n are not shown) is a bit line precharge transistor control circuit for controlling conduction / non-conduction of nMOS transistors.

Further, 134 generates a bit line precharge signal PC ₃ , and the bit line precharge circuits 128 ₀ to 1
28 _n (bit line precharge circuits 128 _{3 to} 128 _n are not shown) is a bit line precharge transistor control circuit for controlling conduction / non-conduction of nMOS transistors.

Further, 135 generates the bit line precharge signal PC ₄ , and the bit line precharge circuits 129 ₀ to 129 ₀ to 1
29 _n (bit line precharge circuits 129 _{3 to} 129 _n are not shown) is a bit line precharge transistor control circuit for controlling conduction / non-conduction of nMOS transistors.

Further, 136 is an isolation signal IS
O ₁ is generated and the cells of the sense amplifiers 130 _{0 to} 130 _n
NM configuring the isolation circuit on the array 121 side
It is an isolation transistor control circuit that controls conduction and non-conduction of the OS transistor.

137 is an isolation signal IS
O ₂ is generated, and the cells of the sense amplifiers 130 _{0 to} 130 _n
NM configuring the isolation circuit on the array 122 side
It is an isolation transistor control circuit that controls conduction and non-conduction of the OS transistor.

138 is an isolation signal IS
O ₃ is generated, and the cells of the sense amplifiers 131 _{0 to} 131 _n
NM configuring the isolation circuit on the array 122 side
It is an isolation transistor control circuit that controls conduction and non-conduction of the OS transistor.

139 is an isolation signal IS
O ₄ is generated, and the cells of the sense amplifiers 131 _{0 to} 131 _n
NM forming the isolation circuit on the array 123 side
It is an isolation transistor control circuit that controls conduction and non-conduction of the OS transistor.

FIG. 2 is a circuit diagram partially showing the circuit configuration of the portion shown in FIG. 1. In FIG.
₂₁ and ₁₂₂ , WL _121-0 and WL _122-0 are word lines.

Further, 141 to 144 are memory cells, and 145 to 148 are capacitors for accumulating charges,
49 to 152 are nMOS transistors (transfer transistors) that control the input / output of charges.

Further, the bit line precharge circuit 12
6 _0, 126 in _2, 153 a bit line precharge signal lines for transmitting bit line precharge signal PC _1, 1
54 to 159 are nMOS transistors (bit line precharge transistors) whose conduction and non-conduction are controlled by the bit line precharge signal PC ₁ , and 160 is a bit line precharge for supplying 1 / 2.VCC as a bit line precharge voltage. It is a charge voltage line.

Further, the bit line precharge circuit 12
In 7 ₀ and 127 ₂ , 161 is a bit line precharge signal line for transmitting the bit line precharge signal PC ₂ and 1
62 to 167 are nMOS transistors (bit line precharge transistors) whose conduction and non-conduction are controlled by the bit line precharge signal PC ₂ , and 168 are bit line precharges for supplying 1/2 · VCC as the bit line precharge voltage. It is a charge voltage line.

In the sense amplifiers 130 ₀ and 130 ₂ , 169 ₀ and 169 ₂ are flip-flop circuits, 170 to 173 are pMOS transistors, and 174 to 174.
Reference numeral 177 is an nMOS transistor.

178 is a pMOS transistor 17
Flip-flop circuits 169 _{0 to} 16 such as _{0 to} 173
9 _n (flip-flop circuits 169 ₁ , 169 _{3 to} 169 _n
Is a sense amplifier drive voltage line for supplying a sense amplifier drive voltage PSA (power supply voltage on the high voltage side) to a pMOS transistor that constitutes (not shown).

179 is an nMOS transistor 17
4 to 177 and the like, flip-flop circuits 169 _{0 to} 16
9 _n is a sense amplifier drive voltage line for supplying a sense amplifier drive voltage NSA (power supply voltage on the low voltage side) to the nMOS transistors constituting 9 _n .

Further, 180 ₀ and 180 ₂ are isolation circuits, and 181 is an isolation signal ISO ₁
Is an nMOS transistor (isolation transistor) whose conduction and non-conduction are controlled by the isolation signal ISO ₁ .

186 ₀ and 186 ₂ are isolation circuits, and 187 is an isolation signal ISO _2.
Isolation signal line for supplying a, 188 to 191 is turned on by isolation signal ISO _2, an nMOS transistor nonconductive is controlled (isolation transistor).

DB and / DB are data buses and 192
₀ and 192 ₂ are column selection circuits, and 193 and 194 are nMOS transistors whose conduction and non-conduction are controlled by the column selection signal CL ₀ , and 195 and 196 whose conduction and non-conduction are controlled by the column selection signal CL _2. It is an nMOS transistor.

In the first embodiment, the isolation signals ISO _{1 to} ISO ₄ are set to the high level during standby, and the nMOS transistors 182 to 185 and 188 are set.
Such as ～191, isolation circuit 180 _0-18
0 _n , 186 _{0 to} 186 _n (isolation circuit 18
0 ₁ , 180 _{3 to} 180 _n , 186 ₁ and 186 _{3 to} 186 _n are omitted), and all nMOS transistors are made conductive.

Further, the bit line precharge signals PC ₁ to
PC ₄ = high level, nMOS transistor 154
Such ～158,162～166, bit line precharge circuit _{126 0 ~126 n, 127 0 ~127} n constituting the n
All MOS transistors are made conductive.

Thereafter, the active state is set, and for example,
When the cell array 121 is selected, the isolation signal ISO ₁ is maintained at a high level, and the bit lines BL _121-0 , / BL _121-0 , BL _{121- of the} cell array 121 such as the nMOS transistors 182 to 185 are maintained. ₂ , / BL _{121-2
..BL 121-2n} and / BL _121-2n and sense amplifier 130
Isolation circuit 180 ₀ for connecting _{0 to} 130 _n
The gate voltage of the nMOS transistors constituting ~ 180 _n is maintained at a high level.

On the other hand, the isolation signal ISO ₂ is set to the low level and the bit lines BL _122-0 , / BL of the cell array 122 such as the nMOS transistors 188 to 191 are set.
_122-0 , BL _122-2 , / BL _122-2 ... BL _122-2n , /
And _BL 122-2n, the gate voltage of the nMOS transistor constituting the isolation circuits 186 ₀ - 186 _n for connecting the sense amplifiers 130 ₀ to 130 DEG _n is low.

Further, the bit line precharge signal PC ₁ is set to the low level, and the nMOS transistors 154 to 159.
, The gate voltage of the nMOS transistors forming the bit line precharge circuits 126 _{0 to} 126 _n is set to a low level, and the bit lines BL _121-0 , / BL _121-0 , BL _121-2 ,
_Precharge for / BL _121-2 ... BL _121-2n , / BL _121-2n is stopped.

On the other hand, the bit line precharge signal PC₂Is
High level is maintained, and nMOS transistors 162 to 1
67, etc., bit line precharge circuit 127₀~ 127_n
The gate voltage of the nMOS transistor that constitutes the
Bit line BL _122-0, / BL_122-0, BL
_122-2, / BL_122-2... BL_122-2n, / BL_122-2nTo
Pre-charge will continue.

Then, when the restore operation to the memory cell is completed, the potential of the word line is set to the low level, and the standby state is again set, the bit line precharge signal PC
₁ is high level, and nMOS transistors 154-1
59, etc., bit line precharge circuits 126 _{0 to} 126 _n
The gate voltage of the nMOS transistor constituting the above is set to a high level.

Further, the isolation signal ISO ₂ is set to the high level, and the gate voltages of the nMOS transistors constituting the isolation circuits 186 _{0 to} 186 _n , such as the nMOS transistors 188 to 191, are set to the high level.

On the other hand, when the cell array 122 is selected, the isolation signal ISO ₂ is maintained at the high level, and the nMOS transistors 188 to 191 etc.
NM configuring the isolation circuits 186 _{0 to} 186 _n
The gate voltage of the OS transistor is maintained at a high level.

On the other hand, the isolation signal ISO ₁ is set to the low level, and the gate voltages of the nMOS transistors forming the isolation circuits 180 _{0 to} 180 _n , such as the nMOS transistors 182 to 185, are set to the low level.

Further, the bit line precharge signal PC ₂ is set to the low level and the nMOS transistors 162 to 167 are set.
, The gate voltage of the nMOS transistors forming the bit line precharge circuits 127 _{0 to} 127 _n is set to the low level, and the bit lines BL _122-0 , / B of the cell array 122 are set.
L _122-0 , BL _122-2 , / BL _122-2 ... BL _122-2n ,
Pre-charge for / BL _122-2n is stopped.

On the other hand, the bit line precharge signal PC₁Is
High level is maintained and nMOS transistors 154-1
59, etc., bit line precharge circuit 126₀~ 126_n
The gate voltage of the nMOS transistor that constitutes the
Bit line BL of the cell array 121
_121-0, / BL_121-0, BL_121-2, / BL_121-2... B
L _121-2n, / BL_121-2nPrecharge against
Be done.

Then, when the restore operation to the memory cell is completed, the potential of the word line is set to the low level, and the standby state is again set, the bit line precharge signal PC
₂ is set to a high level and the nMOS transistors 162 to
167 etc., bit line precharge circuits 127 _{0 to} 12
The gate voltage of the nMOS transistor constituting 7 _n is set to the high level.

Further, the isolation signal ISO ₁ is set to the high level, and the gate voltages of the nMOS transistors constituting the isolation circuits 180 _{0 to} 180 _n , such as the nMOS transistors 182 to 185, are set to the high level.

Here, in the first embodiment, the cell arrays of the folded bit line structure are arranged in the extending direction of the bit lines, and the cell arrays except the cell arrays on both sides are arranged on both sides of the cell array. Shared type sense amplifiers are assigned to each pair of bit lines (for example, shared type sense amplifiers 130 _{0 to} 130 _n and 131 ₀ to 1 on both sides of the cell array 122 for each pair of bit lines).
31 _n is allocated), so that the arrangement pitch of the sense amplifiers can be relaxed.

Moreover, the bit line precharge circuit is provided adjacent to the sense amplifier (for example, sense amplifiers 130 _{0 to} 130 _n and 131 _{0 to} 131 _n).
Adjacent to the bit line precharge circuits 126 ₀ to 126
6 _n , 127 _{0 to} 127 _n , 128 _{0 to} 128 _n , 129 ₀ ~
129 _n is provided), it is possible to secure a sufficient width in the bit line extending direction of the sense amplifier.

As described above, according to the first embodiment, the relaxation of the arrangement pitch of the sense amplifiers can be ensured, and further, the width of the sense amplifiers in the extending direction of the bit lines is ensured. It is possible to ensure the relaxation of the design standard of the sense amplifier.

Further, according to the first embodiment, since the bit line precharge circuit is provided adjacent to the sense amplifier, the isolation circuit provided in the sense amplifier when precharging the bit line. Since the bit line can be precharged without the intermediary of the transistor constituting the above, it is possible to shorten the precharge time of the bit line.

Further, in the first embodiment, it is preferable that the high level voltage of the bit line precharge signal and the isolation signal is made higher than the power supply voltage on the high voltage side of the flip-flop circuit which constitutes the sense amplifier. Is.

That is, in this case, the memory
In the restore operation and the write operation to the cell, it is possible to prevent the high level voltage supplied to the cell array from being lowered due to the threshold loss of the nMOS transistor forming the isolation circuit, and to prevent the bit line from being precharged. A sufficient gate-source voltage of the transistor forming the precharge circuit can be secured, and the bit line precharge operation can be further speeded up.

It is a conventional practice to set the high level voltage to be supplied to the gate of the nMOS transistor forming the isolation circuit higher than the power supply voltage on the high voltage side of the flip-flop circuit forming the sense amplifier. It was being appreciated.

In this case, the high-level voltage supplied to the gate of the nMOS transistor forming the isolation circuit is generally provided with a booster circuit in the DRAM, and the power supply voltage VCC supplied from the outside is pumped by the capacitor. It was supposed to be boosted at.

Since the voltage VPP obtained by boosting by the pumping action of the capacitor is a relatively unstable voltage, a huge capacitor is inserted between it and the ground level, and a large amount of electric charge is applied to this capacitor. It is common to accumulate the charges and compensate for the charges consumed by the current with this charge to stabilize the voltage VPP.

However, as described above, when the high level voltage of the bit line precharge signal is set higher than the power supply voltage on the high potential side of the flip-flop circuit which constitutes the sense amplifier, the bit line precharge circuit is Some of the transistors that make up hold high levels during operation, so
Since the gate capacitance of that portion also plays the role of a huge capacitor for stabilizing the voltage VPP, a huge capacitor for stabilizing the voltage VPP that the designer intentionally inserts can be small, and the chip area can be reduced. Can be realized.

Second Embodiment FIG. 3 and FIG. 4 FIG. 3 is a plan view schematically showing a part of the second embodiment of the present invention, and FIG. 4 is a partial view of the circuit configuration of the part shown in FIG. It is a circuit diagram.

Here, in the first embodiment shown in FIG. 1 (FIG. 2), when active, the bit line precharge signal P
The logic of C ₁ and the isolation signal ISO ₂ are the same, and the logic of the bit line precharge signal PC ₂ and the isolation signal ISO ₁ are the same.

The logic of the bit line precharge signal PC _{3 and} the logic of the isolation signal ISO ₄ are the same, and the logic of the bit line precharge signal PC _{4 and} the logic of the isolation signal ISO ₃ are the same.

That is, for example, when the cell array 121 is selected, the bit line precharge signal PC ₁ = low level, the isolation signal ISO ₂ = low level,
The bit line precharge signal PC ₂ = high level and the isolation signal ISO ₁ = high level are maintained.

When the cell array 122 is selected, the bit line precharge signal PC ₂ = low level,
The isolation signal ISO ₁ is kept low, the bit line precharge signal PC ₁ is kept high, and the isolation signal ISO ₂ is kept high.

Further, the bit line precharge signal PC ₃ =
Low level, isolation signal ISO ₄ = low level, bit line precharge signal PC ₄ = high level, isolation signal ISO ₃ = high level are maintained.

When the cell array 123 is selected, the bit line precharge signal PC ₄ = low level,
The isolation signal ISO ₃ = low level, the bit line precharge signal PC ₃ = high level, and the isolation signal ISO ₄ = high level are maintained.

In consideration of this point, the second embodiment of the present invention is to improve the first embodiment shown in FIG. 1 (FIG. 2). The bit line precharge transistor and the isolation transistor control circuit are provided, and the others are configured in the same manner as in the first embodiment.

For example, for the sense amplifiers 130 _{0 to} 130 _n , bit line precharge transistor and isolation transistor control circuits 198 and 199.
And the bit line precharge transistor and isolation transistor control circuits 200 and 201 are provided for the sense amplifiers 131 _{0 to} 131 _n .

Here, the bit line precharge transistor and isolation transistor control circuit 19
8 outputs the output signal to the bit line precharge circuit 12
6 ₀ For - 126 _n, the bit line precharge signal P
It is supplied as C ₁ and the isolation circuits 186 ₀ to 18
6 _n is supplied as an isolation signal ISO ₂ .

Further, the bit line precharge transistor and isolation transistor control circuit 199.
Outputs its output signal to the bit line precharge circuit 127
_{For 0 to} 127 _n , the bit line precharge signal PC
₂ , and the isolation circuits 180 _{0 to} 180
_{For n} , it is supplied as an isolation signal ISO ₁ .

In addition, the bit line precharge transistor and isolation transistor control circuit 200
Outputs its output signal to the bit line precharge circuit 128.
_{For 0 to} 128 _n , the bit line precharge signal PC
Supplied as _3, the bit line precharge circuit 128 _0-1
The isolation signal ISO ₄ is supplied to the isolation circuit adjacent to 28 _n .

Further, the bit line precharge transistor and isolation transistor control circuit 201
Outputs its output signal to the bit line precharge circuit 129.
_{For 0 to} 129 _n , the bit line precharge signal PC
₄ , and the bit line precharge circuits 129 ₀ to 1
The isolation circuit adjacent to 29 _n is supplied with an isolation signal ISO ₃ .

According to the second embodiment, similarly to the first embodiment, it is possible to secure the relaxation of the design standard of the shared type sense amplifier and shorten the precharge time of the bit line.

Further, according to the second embodiment, two bit line precharges / charge lines for one sense amplifier column.
Since the transistor and the isolation transistor control circuit are provided, two bit line precharge transistor control circuits and two isolation transistor control circuits are provided for one sense amplifier row. Compared with the case of the first embodiment, 1
Since the number of control circuits for each sense amplifier row can be reduced by two, the design criteria for the control circuits can be relaxed.

Also in the second embodiment, it is preferable that the high level voltage of the bit line precharge signal and the isolation signal is set higher than the power supply voltage on the high voltage side of the flip-flop circuit forming the sense amplifier. Is.

That is, in this case, as described above, in the restore operation and the write operation to the memory cell, the high voltage supplied to the cell array due to the threshold loss of the nMOS transistor forming the isolation circuit. It is possible to prevent the level voltage from dropping and to secure a sufficient gate-source voltage of the transistor that constitutes the bit line precharge circuit when precharging the bit line, which further improves the bit line precharge operation. The speed can be increased.

Further, when the high level voltage of the bit line precharge signal is set higher than the power supply voltage on the high potential side of the flip-flop circuit which constitutes the sense amplifier in this way, even in the case of the first embodiment. As explained, some of the transistors that make up the bit line precharge circuit are
Since a high level is maintained during operation, the gate capacitance of that portion also plays the role of a huge capacitor for stabilizing the voltage VPP, and therefore a huge capacitor for stabilizing the voltage VPP that the designer intends to insert. Is small, and the chip area can be reduced.

[0113]

As described above, according to the present invention, by adopting the configuration in which the bit line precharge circuit is provided adjacent to the sense amplifier, it is possible to secure the relaxation of the arrangement pitch of the sense amplifiers. In addition, it is possible to secure a sufficient width as the width of the sense amplifier in the extending direction of the bit line. Therefore, it is possible to secure the relaxation of the design standard of the sense amplifier and the isolation provided in the sense amplifier. Since the bit line can be precharged without passing through the transistor that constitutes the circuit, the precharge time of the bit line can be shortened.

[Brief description of drawings]

FIG. 1 is a plan view schematically showing a part of a first embodiment of the present invention.

FIG. 2 is a circuit diagram partially showing a circuit configuration of a portion shown in FIG.

FIG. 3 is a plan view schematically showing a part of a second embodiment of the present invention.

FIG. 4 is a circuit diagram partially showing a circuit configuration of a portion shown in FIG.

FIG. 5 is a plan view schematically showing a part of an example of a conventional DRAM.

FIG. 6 is a circuit diagram partially showing a circuit configuration of a portion shown in FIG.

FIG. 7 is a plan view schematically showing a part of another example of a conventional DRAM.

8 is a circuit diagram partially showing a circuit configuration of a main part of the DRAM shown in FIG.

[Explanation of symbols]

PC _{1 to} PC ₄ Bit line precharge signal ISO _{1 to} ISO ₄ isolation signal

Claims (3)

[Claims] 1. A folded bit line structure comprising three or more cells.
Arrays are arranged in the extending direction of the bit lines. For cell arrays other than the cell arrays on both sides, shared type sense amplifiers are allocated to each bit line pair and adjacent to these sense amplifiers. And a bit line precharge circuit. 2. The sense amplifier includes a flip-flop circuit, a first isolation circuit that controls connection and disconnection of a bit line pair of a cell array adjacent on one side to the flip-flop circuit, and the other one. A bit line precharge circuit adjacent to one side of the sense amplifier, and a second isolation circuit for controlling connection / disconnection of the bit line pair of the cell array adjacent to the side to the flip-flop circuit. The second isolation circuit is controlled by a first control signal, and the bit line precharge circuit adjacent to the other side of the sense amplifier and the first isolation circuit are controlled by a second control signal. 2. The dynamic RAM according to claim 1, wherein the dynamic RAM is configured to be controlled by. 3. The high-level voltage of the first and second control signals is higher than the high-voltage power supply voltage supplied to the flip-flop circuit. Dynamic RAM.