JPH08125277A - Semiconductor device having V-groove structure - Google Patents
Semiconductor device having V-groove structureInfo
- Publication number
- JPH08125277A JPH08125277A JP26283894A JP26283894A JPH08125277A JP H08125277 A JPH08125277 A JP H08125277A JP 26283894 A JP26283894 A JP 26283894A JP 26283894 A JP26283894 A JP 26283894A JP H08125277 A JPH08125277 A JP H08125277A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- groove
- shaped groove
- active layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims description 16
- 239000012808 vapor phase Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 17
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 10
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 abstract 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 6
- 238000005253 cladding Methods 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 229910000070 arsenic hydride Inorganic materials 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
- Semiconductor Lasers (AREA)
- Led Devices (AREA)
Abstract
Description
【0001】[0001]
【発明の利用分野】本発明は半導体装置、好ましくは量
子効果を用いた半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, preferably a semiconductor device using the quantum effect.
【0002】[0002]
【従来の技術】量子井戸、量子細線、量子箱等の量子マ
イクロ構造を有する半導体装置は、特に半導体発光装置
として特に好適に用いられ、電子と正孔の量子化効果に
よって、低しきい値電流、高変調帯域、高コヒーレンス
特性等において、優れた特性が得られている。この効果
は、活性層に臨界膜厚以下の歪を導入した場合に顕著に
現れている。2. Description of the Related Art A semiconductor device having a quantum microstructure such as a quantum well, a quantum wire, and a quantum box is particularly preferably used as a semiconductor light emitting device, and has a low threshold current due to a quantization effect of electrons and holes. Excellent characteristics are obtained in high modulation band, high coherence characteristics, and the like. This effect is prominent when the strain less than the critical film thickness is introduced into the active layer.
【0003】そして量子細線の作成方法としては、量子
井戸構造を作っておいてから、電子線露光等による微細
なフォトリソグラフィー法とイオンビームによる垂直エ
ッチングを組み合わせて用いて細線を形成する方法や、
図4に示す基板上にV字形状の溝を設け、この後に断面
がV字になる溝(以下、「V溝」という)形状を有する
基板全面にダブルヘテロ構造を成長させる方法が行われ
ている。As a method of forming a quantum wire, a quantum well structure is formed and then a fine photolithography method by electron beam exposure or the like and vertical etching by an ion beam are used in combination to form a wire.
A method of forming a V-shaped groove on the substrate shown in FIG. 4 and then growing a double hetero structure on the entire surface of the substrate having a groove having a V-shaped cross section (hereinafter referred to as “V groove”) is performed. There is.
【0004】[0004]
【発明が解決すべき課題】量子細線などの微細構造で
は、平面上よりも厚膜でも量子効果が存在し、この事実
は利得を稼ぐ上では好都合である。平坦な基板表面に歪
の効果が現れる格子不整合率1〜2%の歪活性層を成長
させようとした時、歪活性層が全面で応力を受けるため
に、転位の発生し始める膜厚すなわち臨界膜厚は10〜
20nm程度しかなく、細線として利用しようとした場
合、歪活性層を充分に厚くできない場合が多い。しかし
ながら、前者の方法は、加工による溝側壁の損傷が大き
く、細線の品質は劣ったものになりやすい。一方後者
は、成長速度の方位依存性を利用し、量子細線を選択的
に行うことができるが、V溝を形成しようとする部分の
組成によっては、形成したV溝の底が丸みを帯びてしま
ったり、あるいはウェットエッチングのさいに、エッチ
ング表面に酸化膜が形成されてしまったり、不純物で汚
染されてしまったり、あるいはエッチングにより、V溝
の底が丸まってしまったりすることがある。In a fine structure such as a quantum wire, a quantum effect exists even in a thick film rather than on a plane, and this fact is convenient for gaining. When an attempt is made to grow a strained active layer having a lattice mismatch rate of 1 to 2% in which a strain effect appears on a flat substrate surface, the strained active layer receives stress on the entire surface, and thus the film thickness at which dislocation begins to occur, that is, The critical film thickness is 10
Since it is only about 20 nm, it is often impossible to make the strained active layer sufficiently thick when it is used as a thin wire. However, in the former method, the side wall of the groove is largely damaged by the processing, and the quality of the fine wire is likely to be inferior. On the other hand, in the latter, the quantum wire can be selectively formed by utilizing the orientation dependence of the growth rate, but the bottom of the formed V groove is rounded depending on the composition of the portion where the V groove is to be formed. In some cases, during wet etching, an oxide film is formed on the etching surface during wet etching, it is contaminated with impurities, or the bottom of the V groove is rounded due to etching.
【0005】このため、品質のよい量子細線を、容易に
得られる構造が望まれている。又、半導体装置の効率の
向上もまた現在の課題である。Therefore, there is a demand for a structure capable of easily obtaining a high quality quantum wire. In addition, improving the efficiency of semiconductor devices is also a current issue.
【0006】[0006]
【課題を解決するための手段】そこで本発明者らは、鋭
意研究の結果、かかる課題が、特定の構造により解決さ
れることを見いだし本発明に到達した。すなわち本発明
の目的は、品質のよい量子細線を有する半導体装置を提
供することであり、かかる目的は、半導体基板又は半導
体基板上に成長させたエピタキシャル成長層の少なくと
も一部に断面がV字になる溝を有し、該V字になる溝の
底の部分に歪を有する活性層を設け、該活性層が、クラ
ッド層により埋め込まれた構造を有する半導体装置、よ
り好ましくは、該活性層が、量子井戸構造を有する前記
半導体装置、該V字になる溝の斜面で接しているV字構
造の内側と外側のクラッド層を有し、該外側のクラッド
層のエネルギーギャップが、該内側のクラッド層のエネ
ルギーギャップより大きくなっている構造を有する前記
半導体装置、該V字になる溝の斜面が、{111}B面
である前記半導体装置、V字になる溝が、気相エッチン
グにより形成された前記半導体装置等により、容易に達
成される。The inventors of the present invention, as a result of intensive research, have found that such a problem can be solved by a specific structure, and have reached the present invention. That is, an object of the present invention is to provide a semiconductor device having a high-quality quantum wire, and an object thereof is to form a V-shaped cross section in at least a part of a semiconductor substrate or an epitaxial growth layer grown on the semiconductor substrate. A semiconductor device having a groove, in which a strained active layer is provided at the bottom of the V-shaped groove, and the active layer has a structure filled with a cladding layer, more preferably, the active layer is The semiconductor device having a quantum well structure, which has inner and outer clad layers of a V-shaped structure that are in contact with each other at the slope of the V-shaped groove, and the energy gap of the outer clad layer is the inner clad layer. Of the semiconductor device having a structure that is larger than the energy gap of the semiconductor device, the semiconductor device in which the slope of the V-shaped groove is a {111} B plane, and the groove of the V-shaped groove are vapor-phase etched. By the semiconductor device or the like which is more formed, it is readily achieved.
【0007】以下に本発明を詳細に説明する。本発明の
半導体装置の構造は、III−V族化合物半導体、II−VI
族化合物半導体等に好適に使用できる。そして本発明の
構造は、活性領域内でのキャリアの伝導を利用した電子
素子として好適に用いられるが、特に好適には発光半導
体装置として用いられる。The present invention will be described in detail below. The structure of the semiconductor device of the present invention is III-V compound semiconductor, II-VI.
It can be suitably used for group compound semiconductors and the like. The structure of the present invention is preferably used as an electronic element utilizing the conduction of carriers in the active region, and particularly preferably used as a light emitting semiconductor device.
【0008】本発明の半導体装置の構造を、実施例で作
成したIII−V族の(100)面GaAs基板上に成長
させた図1の装置の説明図を用いて説明する。(10
0)面を用いたのは、V溝の対称性や直進性によって量
子井戸の対称性や直進性が影響を受けるため、この点で
最も有利である方位を選んだためであるが、極端に量子
井戸の対称性や直進性が影響を受けない限り、任意の方
向の基板を用いることができる。もちろんオフアングル
方向についても同様のことが言える。本発明のV溝は、
基板又は基板上に成長したエピタキシャル層に設けられ
る。そして、V溝の方向は、<110>方向から10°
以下が好ましく、より好ましくは5°以下である。10
°を越えて<110>方向からずれると、V溝の側面の
状態が、ギザギザの階段状になりやすくあまり好ましく
ない。The structure of the semiconductor device of the present invention will be described with reference to the explanatory view of the device of FIG. 1 grown on the III-V group (100) plane GaAs substrate prepared in the embodiment. (10
The (0) plane is used because the symmetry and straightness of the V-groove affect the symmetry and straightness of the quantum well. A substrate in any direction can be used as long as the symmetry and straightness of the quantum well are not affected. Of course, the same can be said for the off-angle direction. The V groove of the present invention is
It is provided on a substrate or an epitaxial layer grown on the substrate. The direction of the V groove is 10 ° from the <110> direction.
The following is preferable, and 5 ° or less is more preferable. 10
If it deviates from the <110> direction by more than °, the state of the side surface of the V groove is likely to be jagged and is not so preferable.
【0009】そして活性層は、このV溝の底の部分に設
けられる。活性層の厚さは、活性層として量子井戸構造
を用いる場合、量子細線として用いるためには20nm
以下が好ましいが、50nm程度までは使用することが
できる。活性層の組成や導電型については、通常使用さ
れる全てのものが使用でき、特に限定されない。本発明
のように、歪活性層を局所的に成長すると、平坦な表面
に成長させたときと比べて、歪活性層が受ける応力が小
さくて済むために、より厚膜の活性層を用いることが可
能となる。本発明においては、活性層をV溝の底に設け
たため、より細い量子細線を作成することができる。The active layer is provided at the bottom of the V groove. When the quantum well structure is used as the active layer, the thickness of the active layer is 20 nm for use as quantum wires.
The following is preferable, but it can be used up to about 50 nm. With respect to the composition and conductivity type of the active layer, any of those usually used can be used, and there is no particular limitation. When the strained active layer is locally grown as in the present invention, a stress applied to the strained active layer is smaller than that when the strained active layer is grown on a flat surface. Therefore, a thicker active layer is used. Is possible. In the present invention, since the active layer is provided on the bottom of the V-groove, it is possible to make a finer quantum wire.
【0010】本発明の好ましい態様としては、基板上に
エピタキシャル成長させたクラッド層を設け、これにV
溝を設けて活性層を設け、この活性層の上にさらに第2
のクラッド層を設けた構造である。そして本発明の好適
な構造の一つは、V溝の斜面で接しているV字構造の内
側と外側のクラッド層が、該外側のクラッド層のエネル
ギーギャップが、該内側のクラッド層のエネルギーギャ
ップより大きくなっている関係にあることであり、この
ような構造をとることで、電流をV溝の底にある活性層
に集中させることができるのでレーザダイオード等に特
に好適に用いられる。In a preferred embodiment of the present invention, a clad layer epitaxially grown on the substrate is provided and V
A groove is provided to provide an active layer, and a second layer is formed on the active layer.
This is a structure in which a clad layer is provided. One of preferred structures of the present invention is that the inner and outer clad layers of the V-shaped structure which are in contact with each other at the slope of the V groove, the energy gap of the outer clad layer, and the energy gap of the inner clad layer. It has a larger relationship, and by adopting such a structure, the current can be concentrated in the active layer at the bottom of the V groove, so that it is particularly preferably used for a laser diode or the like.
【0011】そしてこのV溝の斜面は、{111}B面
であることが好ましい。{111}B面とは、III−V
族化合物半導体であればV族のみが表面にならぶ{11
1}面になり、II−VI族化合物半導体であればVI族のみ
が表面にならぶ{111}面になる。これは、一般に
{111}B面上には、V族原子の立体障害やV/III
>1であることから結晶成長が生じにくく、V溝の底か
ら成長を始めることが容易であるためである。この現象
は、歪み活性層を成長させたときには、{111}B面
からの応力が少ないことを意味しており、臨界膜厚を増
加させることができる。The slope of the V groove is preferably the {111} B plane. The {111} B plane is III-V.
If it is a group compound semiconductor, only the group V has a surface {11
If the compound semiconductor is a II-VI group compound semiconductor, only the group VI becomes a {111} plane. This is due to the steric hindrance of group V atoms and V / III on the {111} B plane.
This is because the crystal growth is less likely to occur since> 1 and it is easy to start the growth from the bottom of the V groove. This phenomenon means that the stress from the {111} B plane is small when the strained active layer is grown, and the critical film thickness can be increased.
【0012】そして本発明のV溝は、気相エッチングに
より形成することが好ましい。これは、従来のようにウ
ェットエッチングでV溝を作成すると、V溝の底が、丸
まった形状になりやすく、また、不純物がエッチング面
に残ったり、酸化膜が形成されたりすると、エッチング
面に接する形で活性層を設けても、品質のよい活性層を
得ることが困難になりやすいためである。The V groove of the present invention is preferably formed by vapor phase etching. This is because when the V groove is formed by wet etching as in the conventional case, the bottom of the V groove tends to have a rounded shape, and when impurities remain on the etching surface or an oxide film is formed on the etching surface, This is because it is difficult to obtain a high quality active layer even if the active layer is provided in contact with each other.
【0013】又、V溝は逆ピラミッド状のような、長手
方向の長さを持たないような構造でもよいことはいうま
でもない。本発明の構造の好ましい製造方法の1例とし
ては、まず基板上に第1クラッド層となる層をエピタキ
シャル成長させる。このとき用いる成長方法は、有機金
属気相成長法(MOCVD法)が好ましい。このエピタ
キシャルウェハ表面に、フォトリソグラフィー法等のパ
ターニングプロセスを用いてストライプ状の窒化シリコ
ン膜を形成する。このとき窒化シリコン膜のストライプ
の方向は、<110>方向であることが好ましい。この
後、有機金属気相成長(MOCVD)法用のリアクタ内
にエッチングガスを導入することにより、窒化シリコン
膜をマスクとした、第1クラッド層のin−situガ
スエッチングを行い、先端の鋭く尖ったV溝を形成し、
そのまま基板を空気中にさらすことなく連続的に量子細
線及び第2クラッド層をV溝内に成長させる。このとき
好適なエッチングガスとしては、HClが挙げられる。
又、この方法を用いると、不純物がエッチング面に残っ
たり、酸化膜が形成されたりすることがないので、エッ
チング面に直接活性層を成長させても、品質のよい活性
層をえることができる。Needless to say, the V-groove may have a structure having no length in the longitudinal direction, such as an inverted pyramid shape. As an example of a preferred method of manufacturing the structure of the present invention, first, a layer to be the first cladding layer is epitaxially grown on the substrate. The growth method used at this time is preferably a metal organic chemical vapor deposition method (MOCVD method). A stripe-shaped silicon nitride film is formed on the surface of the epitaxial wafer by using a patterning process such as a photolithography method. At this time, the stripe direction of the silicon nitride film is preferably the <110> direction. After that, by introducing an etching gas into the reactor for metal organic chemical vapor deposition (MOCVD) method, in-situ gas etching of the first cladding layer is performed using the silicon nitride film as a mask, and the tip is sharply pointed. Forming a V-groove,
The quantum wires and the second cladding layer are continuously grown in the V groove without exposing the substrate to the air as it is. At this time, HCl is a suitable etching gas.
Further, when this method is used, impurities are not left on the etching surface or an oxide film is not formed, so that a high-quality active layer can be obtained even if the active layer is directly grown on the etching surface. .
【0014】以下本発明を実施例を用いて更に詳細に説
明するが、本発明はその要旨を越えない限り、実施例に
限定されるものではない。 (実施例1)最初に、(100)GaAs基板上に、M
OCVD法にて、GaAs層(0.5μm)、Al0.5G
a0.5As(2μm)、GaAs層(20nm)をこの
順に形成した。このエピ基板の表面に、窒化シリコンを
PCVD法で成膜し、これをフォトリソグラフィー法で
[011]方向に伸びる幅1μmの窒化シリコン膜が、
1μmおきに並ぶ形状にマスクした。このマスク済のサ
ンプルを再びMOCVD装置にセットした。セット後、
アルシン(AsH3)雰囲気下で700℃まで昇温し、
それからHClガスを用いてエッチングを行い、{11
1}B面を両側側面に有するV溝を形成した。エッチン
グを停止した直後に温度を700℃に維持したまま、ト
リメチルガリウム(TMG)とトリメチルインジウム
(TMI)を供給し、V溝内にIn0.2Ga0.8As歪み
活性層を形成し、さらにTMGと共にトリメチルアルミ
ニウム(TMA)も同時に供給し、1μmのAl0.5G
a0.5Asクラッド層を作成し、再びアルシンとTMG
を供給し、0.1μmのGaAs層を形成した。この製
造プロセスの説明を図2に示す。このとき、{111}
B面上は、エピタキシャル成長が困難であるため、V溝
の側壁には成長が起こらず、結果としてV溝の底にGa
Asの量子細線が、自己整合的に形成される。又、成長
中にもHClをIII族原料と同モル程度の1sccm程
度供給することにより、窒化シリコン層上に、AlGa
Asの多結晶の析出を防いだ。この成長中にHClを供
給する手法は、特にGaAlAs層のアルミニウム組成
が0.4以上の時に好適に用いられ、そして高いアルミ
ニウム組成を有するAlGaAsの選択成長が可能とな
るので、活性層へのキャリアの閉じ込めに効果がある。Hereinafter, the present invention will be described in more detail with reference to examples, but the present invention is not limited to the examples as long as the gist thereof is not exceeded. (Example 1) First, on a (100) GaAs substrate, M
GaAs layer (0.5 μm), Al 0.5 G by OCVD method
Then, a 0.5 As (2 μm) and a GaAs layer (20 nm) were formed in this order. A silicon nitride film is formed on the surface of this epitaxial substrate by the PCVD method, and a silicon nitride film with a width of 1 μm extending in the [011] direction is formed by the photolithography method.
Masks were formed in a shape of lining every 1 μm. The masked sample was set again in the MOCVD apparatus. After setting
In an arsine (AsH3) atmosphere, raise the temperature to 700 ° C,
Then, etching is performed using HCl gas, and {11
A V groove having 1} B faces on both side faces was formed. Immediately after the etching was stopped, while maintaining the temperature at 700 ° C., trimethylgallium (TMG) and trimethylindium (TMI) were supplied to form an In 0.2 Ga 0.8 As strained active layer in the V groove, and trimethylgallium (TMG) and trimethylindium were further formed together with TMG. Aluminum (TMA) is also supplied at the same time and 1 μm Al 0.5 G
a 0.5 As clad layer is formed, and arsine and TMG are used again.
Was supplied to form a 0.1 μm GaAs layer. An explanation of this manufacturing process is shown in FIG. At this time, {111}
Since it is difficult to grow epitaxially on the B surface, the growth does not occur on the sidewall of the V groove, and as a result, Ga is formed on the bottom of the V groove.
As quantum wires are formed in a self-aligned manner. Also, during the growth, by supplying HCl at about 1 sccm, which is about the same mole as the Group III source material, AlGa is deposited on the silicon nitride layer.
The precipitation of polycrystalline As was prevented. This method of supplying HCl during growth is suitable for use especially when the aluminum composition of the GaAlAs layer is 0.4 or more, and it enables selective growth of AlGaAs having a high aluminum composition, so that carriers for the active layer can be obtained. Is effective in confining
【0015】こうして成長させたサンプルをSEM観察
した。この様子を図1に模式的に示す。窒化シリコンの
マスクの下にエッチングが広がるアンダーエッチング現
象は起こっておらず、またV溝の先端部は非常にシャー
プに尖ったV溝が形成された。そしてこのV溝の底の部
分だけに、In0.2Ga0.8Asの細線が埋め込まれてい
た。平坦な基板上に成長させた場合、歪量子井戸の厚み
が20nm以上になると急激に積分PL強度が低下した
のに対して、細線の場合、高さ40nmまでは積分PL
強度が低下しなかった。これらの結果は、損傷の少ない
高品質な量子細線を簡単に得ることができたことのみな
らず、臨界膜厚を増加させることができることを示して
いる。The sample thus grown was observed by SEM. This state is schematically shown in FIG. The under-etching phenomenon in which the etching spreads under the silicon nitride mask did not occur, and the V-groove had a sharp V-groove at the tip. Then, a fine wire of In 0.2 Ga 0.8 As was embedded only in the bottom portion of the V groove. When grown on a flat substrate, the integrated PL intensity sharply decreased when the strained quantum well thickness became 20 nm or more, whereas in the case of a thin wire, the integrated PL intensity up to 40 nm was obtained.
The strength did not decrease. These results indicate that not only a high-quality quantum wire with little damage could be easily obtained, but also the critical film thickness could be increased.
【0016】(実施例2)埋め込みクラッド層の組成を
Al0.3Ga0.7Asにした以外は、実施例1と同様のサ
ンプルを作成し、77KでPL発光強度を調べたとこ
ろ、図3に示すようにIn0.2Ga0.8As歪み量子細線
(横幅40nm、高さ20nm)からの明瞭な発光ピー
クがみられ、前記実施例1のサンプルに対して発光強度
の増加が認められた。これは、V溝の中のキャリアが、
V溝側壁にエネルギー障壁があるため、V溝の外に出ら
れず、V溝の底にある活性層に集中した結果であると考
えられる。このような効果は、レーザ素子等を作成する
場合、有利であると考えられる。Example 2 A sample similar to that of Example 1 was prepared except that the composition of the buried cladding layer was changed to Al 0.3 Ga 0.7 As, and the PL emission intensity was examined at 77 K. As shown in FIG. A clear emission peak was observed from the In 0.2 Ga 0.8 As strained quantum wire (width 40 nm, height 20 nm), and an increase in emission intensity was observed in the sample of Example 1. This is because the carrier in the V groove is
Since there is an energy barrier on the side wall of the V-groove, it is considered that it is a result of being unable to go out of the V-groove and being concentrated on the active layer at the bottom of the V-groove. Such an effect is considered to be advantageous when manufacturing a laser device or the like.
【0017】[0017]
【発明の効果】本発明により、品質のよい歪を有する量
子細線を、容易に得られ、又、半導体装置の効率をも向
上させることができる。According to the present invention, a quantum wire having a high-quality strain can be easily obtained, and the efficiency of a semiconductor device can be improved.
【図1】図1は本発明の、実施例1にて作成した1態様
を示す説明図である。FIG. 1 is an explanatory diagram showing one mode created in Example 1 of the present invention.
【図2】図2は本発明の、実施例1に用いた製造プロセ
スの説明図である。FIG. 2 is an explanatory diagram of a manufacturing process used in Example 1 of the present invention.
【図3】図3は本発明の、実施例1にて作成したサンプ
ルの室温でのPL発光の状態を示す図である。FIG. 3 is a diagram showing a state of PL light emission at room temperature of the sample prepared in Example 1 of the present invention.
【図4】図4は、従来の量子細線を用いた素子の典型を
示した説明図である。FIG. 4 is an explanatory diagram showing a typical example of a device using a conventional quantum wire.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 後藤 秀樹 茨城県牛久市東猯穴町1000番地 三菱化学 株式会社筑波事業所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hideki Goto 1000, Higashihuinana-cho, Ushiku-shi, Ibaraki Mitsubishi Chemical Corporation Tsukuba Plant
Claims (5)
エピタキシャル成長層の少なくとも一部に断面がV字に
なる溝を有し、該V字になる溝の底の部分に歪を有する
活性層を設け、該活性層が、クラッド層により埋め込ま
れた構造を有する半導体装置。1. A semiconductor substrate or an epitaxial growth layer grown on a semiconductor substrate has a groove having a V-shaped cross section in at least a part thereof, and an active layer having a strain at the bottom of the V-shaped groove. A semiconductor device having a structure in which the active layer is provided and is filled with a clad layer.
1記載の半導体装置。2. The semiconductor device according to claim 1, wherein the active layer has a quantum well structure.
造の内側と外側のクラッド層を有し、該外側のクラッド
層のエネルギーギャップが、該内側のクラッド層のエネ
ルギーギャップより大きくなっている構造を有する請求
項1乃至2のいずれかに記載の半導体装置。3. An inner and outer clad layer having a V-shaped structure in contact with the slope of the V-shaped groove, wherein the energy gap of the outer clad layer is greater than the energy gap of the inner clad layer. The semiconductor device according to claim 1, wherein the semiconductor device has an enlarged structure.
である請求項1乃至3のいずれかに記載の半導体装置。4. The semiconductor device according to claim 1, wherein the slope of the V-shaped groove is a {111} B plane.
形成された請求項1乃至4のいずれかに記載の半導体装
置。5. The semiconductor device according to claim 1, wherein the V-shaped groove is formed by vapor phase etching.
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26283894A JPH08125277A (en) | 1994-10-26 | 1994-10-26 | Semiconductor device having V-groove structure |
DE69525128T DE69525128T2 (en) | 1994-10-26 | 1995-10-26 | Semiconductor light emitting device and manufacturing method |
EP95307641A EP0709902B1 (en) | 1994-10-26 | 1995-10-26 | Light-emitting semiconductor device and method for manufacturing the same |
US08/970,145 US6265733B1 (en) | 1994-10-26 | 1997-11-13 | Semiconductor device and method for manufacturing the same |
US09/785,428 US6744066B2 (en) | 1994-10-26 | 2001-02-20 | Semiconductor device and method for manufacturing the same |
US09/867,440 US6589807B2 (en) | 1994-10-26 | 2001-05-31 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26283894A JPH08125277A (en) | 1994-10-26 | 1994-10-26 | Semiconductor device having V-groove structure |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH08125277A true JPH08125277A (en) | 1996-05-17 |
Family
ID=17381326
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP26283894A Pending JPH08125277A (en) | 1994-10-26 | 1994-10-26 | Semiconductor device having V-groove structure |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH08125277A (en) |
-
1994
- 1994-10-26 JP JP26283894A patent/JPH08125277A/en active Pending
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