JPH0811343A - Printer head driving signal generating circuit - Google Patents

Abstract

PURPOSE:To provide a printer head driving signal generating device constituted so as to perform the gradation control of an image without increasing a circuit scale. CONSTITUTION:The data D4 of MSB corresponding to one line transmitted to one-bit shift registers 1-n are latched at the same time at the rising edge of a strobe pulse by one-bit latch circuits 11-1n before a D4 scanning period and supplied to gate circuits 21-2n. An enable signal with a pulse width of 8t is supplied to the gate circuits 21-2n during the D4 scanning period and, when the data D is '1', output having the pulse width set to 8t is generated and a printer head is driven and, when the data D4 is '0', output of an 'L' level is generated and the printer head is not driven. Hereinbelow, the same operation is performed during a D or D1 scanning pariod to drive the printer head.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printer head drive signal generation circuit for driving a printer head used for printing an image on a light-sensitive medium,
It is particularly suitable for downsizing a printer.

[0002]

2. Description of the Related Art A cathode electrode which emits electrons, and an anode electrode which is arranged so as to face the cathode electrode,
Light emitted from the phosphor is provided with a phosphor that is deposited on the anode electrode and emits light when electrons collide with it, and a control electrode that controls the movement of electrons emitted from the cathode to the anode electrode. Has developed a printer that prints an image by exposing photographic paper or the like.

FIG. 5 shows a principle diagram of a color printer (see Japanese Patent Laid-Open No. 5-92622) previously proposed by the present applicant, in which 101 is red (R), green (G), blue ( B)
The printer head 102 that emits light of the three primary colors is a SELFOC lens array for irradiating the photographic paper 103 with the light emitted from the printer head 101.

As shown in the sectional structure of FIG. 6, the printer head 101 has a filament FIL which is a cathode for emitting electrons into a vacuum container (glass), and first and second control electrodes G _1. , G ₂ and a plurality of strip-shaped anode electrodes An (1, 2 ... 12) coated with a predetermined dot pattern by a phosphor are encapsulated, and by the image signal applied to the control electrode G _1. By controlling the arrival of the electrons at the strip-shaped anode electrode An, the emission of the phosphor dots deposited on the anode electrode An to which the voltage is applied at a predetermined timing is turned on / off. ing.

Further, on the upper surface of each strip-shaped anode electrode An, for example, among the lights output from the phosphor dots which are divided into groups corresponding to the three primary colors and are deposited on one set of anode electrodes An, Filters Fr, Fg, and Fb that pass R, G, and B that are the three primary colors are provided. Therefore, image data for one line in the horizontal direction that forms a print image for one frame is sequentially applied to the control electrode G ₁ , and a driving voltage is sequentially supplied to the anode electrode An at a predetermined timing, or the photographic paper 103 or the printer head. Still image color printing can be performed by moving any one of the combination of 101 and SELFOC lens array 102 in the vertical direction (main scanning direction).

FIG. 7 shows a conventional configuration of a printer head drive signal generation circuit capable of generating a printer head drive signal capable of controlling the gradation of an image in such a printer. The printer head drive signal generating circuit shown in this figure has a time width T ₀ , where electrons are emitted toward the anode electrode in accordance with the grayscale data in the scanning period of one horizontal line as shown in FIG. T ₂ , T ₃ ...
・ Changes in 16 ways like T ₁₅ . As a result, the amount of light emitted from the phosphor on the anode electrode is given 16 different changing steps so that 16 different gradations can be obtained in the printed image.

To explain this operation concretely, the grayscale data is 4 bits, and the grayscale data for each pixel is provided for each pixel of one line in the horizontal direction. 4-bit shift registers SR1 to SRn Are respectively shifted by the shift clock. In this case, the 4-bit shift registers SR1 to SRn are connected in cascade. Next, a strobe pulse is applied to the 4-bit latch circuits L1 to Ln, and 4-bit grayscale data is latched in the latch circuits L1 to Ln provided corresponding to the shift registers SR1 to SRn, respectively.

The 4-bit count data value obtained by counting the gradation control clock by the counter CO and the gradation data for each pixel latched by the latch circuits L1 to Ln are respectively compared by the comparators COMP1 to COMPn. By being compared, the comparators COMP1 to COM
A drive signal for each pixel having a pulse width as shown in FIG. 8 is output from Pn for one line in accordance with the gradation data. In this case, the tone data is set to "1111", is a drive signal of a pulse width to be output over one scanning period as shown as T ₁₅ in FIG. 8, the grayscale data is the "0011" If so, the drive signal has a pulse width as indicated by T ₃ in FIG. The counter CO and the comparators COMP1 to COMPn are cleared by the clear pulse each time the output of one line is completed.

[0009]

However, according to the conventional printer head drive signal generation circuit capable of gradation control, in order to perform gradation control, a 4-bit shift register for each pixel, a 4-bit latch circuit, and a comparison circuit are provided. In order to control the gradation of an image composed of a large number of pixels, the circuit scale becomes large, so that a large storage space is required and the cost becomes high. . Further, even when the driver IC is used to form the printer head drive signal generation circuit, the driver I requires the 4-bit shift register, the 4-bit latch circuit, and the comparator for each pixel as described above.
There is a problem that the chip size of C becomes large and the IC becomes expensive.

Therefore, it is an object of the present invention to provide a printer head drive signal generation circuit capable of controlling the gradation of an image without increasing the circuit scale.

[0011]

In order to achieve the above object, a printer head drive signal generating circuit according to the present invention is provided with a 1-bit shift register provided in the same number as the number of pixels in one line, and the 1-bit shift. 1 stored in the register
The number of latch means provided is equal to the number of pixels of one line for latching bit data, and the number of pixels of one line to which the 1-bit data latched by the latch means is supplied as one input, respectively. A number of gate circuits provided in an equal number to each of the gray scale data indicating the gray scale of each pixel on one line, and each of the gray scale data of each pixel has one or more digits. Are sequentially shifted to the 1-bit shift register, and the enable is weighted by a power of 2 in accordance with any digit of the grayscale data supplied to one input of the gate circuit. A signal is supplied to the other input of the gate circuit.

Further, in the printer head drive signal generating circuit of the present invention, specifically, the shift register is shifted by 1-bit data of each digit from the MSB to the LSB of the gradation data, and the enable signal is enabled. The pulse width of the signal is set to be a pulse width sequentially divided by a power of 2 according to the digit of the shifted 1-bit data.

[0013]

According to the present invention, the gradation control of the image to be printed can be performed by the configuration of only the 1-bit shift register, the 1-bit latch means and the gate circuit for each pixel. The circuit scale can be reduced to a fraction, and an inexpensive printer head drive signal generation circuit can be obtained. Even when the driver IC is used to form the printer head drive signal generating circuit, as described above, only one bit shift register, one bit latch means and gate circuit are required for each pixel. Can be made as small as a few times, and it becomes possible to configure using an inexpensive IC.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a principle diagram of a printer head drive signal generating circuit of the present invention. In this figure, 1 to n are 1-bit shifts in which 1 bit of a specific digit of grayscale data consisting of a plurality of bits is shifted and a number of n stages equal to the number n of pixels for one line is provided in the horizontal direction. Register, 11
˜1n is a 1-bit latch circuit provided in the same number n stages as the 1-bit shift registers 1-n for latching 1-bit data shifted to the 1-bit shift registers 1-n, and 21-2n are 1-bit latch circuits The gate circuits are provided in the same number n stages as the 1-bit latch circuits 11 to 1n to which the 1-bit data latched by 11 to 1n are supplied and the enable signal is supplied.

FIG. 2 shows the timing of various signals applied to the printer head drive signal generating circuit configured as described above. The pulse signal shown in FIG. 2A is a waveform of the enable signal supplied to the gate circuits 21 to 2n, and each period obtained by dividing one line scanning period into four is D.
_{When the 4} scanning period, the D ₃ scanning period, the D ₂ scanning period, and the D ₁ scanning period are used, the pulse signal is a rising signal having a width of 8t in the D ₄ scanning period and 4t in the D ₃ scanning period. The pulse signal has a rising period of ½ of the width, the pulse signal has a rising period of ¼ of 2t in the D ₂ scanning period, and the pulse signal has ⅛ period of 1t in the D ₁ scanning period. It is regarded as a rising pulse signal. That is, the weighted pulse width is sequentially halved for each of the four divided scanning periods.

Further, FIG. 3B shows the transfer timing of the gradation data transferred to the 1-bit shift registers 1 to n. For example, when the gradation data is composed of 4 bits, 1 line scanning period is divided into four as described above, D ₄ scanning period, D ₃ scanning period, D ₂ scanning period, D
_{In one} scan period, the gradation data from MSB to LS
Toward B, data of any digit of one line is transferred bit by bit to the 1-bit shift registers 1 to n. That is, in the D ₄ scanning period, 2 of the gradation data
Data D ₃ of the digit are transferred, D ₃ and data D ₂ of the 3 digit of the grayscale data is transferred in the scanning period, D ₂ of the LSB of the gradation data in the scanning period data D ₁ , And MSB data D ₄ of the gradation data of the next line is transferred in the D ₁ scanning period.

Further, FIG. 7C shows a strobe pulse for latching the transferred data as shown in FIG. 7B in the latch circuits 11 to 1n, which is a strobe pulse rising before the D ₄ scanning period. Data D ₄ (MSB) (not shown) is simultaneously latched by the latch circuits 11 to 1n at the rising edge. Similarly, the data D ₃ is simultaneously latched in the latch circuits 11 to 1n by the rising edge of the strobe pulse rising before the D ₃ scanning period, and the data D ₃ is changed by the rising edge of the strobe pulse rising before the D ₂ scanning period.
₂ is simultaneously latched in the latch circuits 11 to 1n, and the data D ₁ (LSB) is simultaneously latched in the latch circuits 11 to 1n by the rising edge of the strobe pulse rising before the D ₁ scanning period.

The shift clock shown in FIG. 3D is a shift clock for transferring grayscale data to the 1-bit shift registers 1 to n, and is a D ₄ scanning period obtained by dividing one line scanning period into four, In the D ₃ scan period, the D ₂ scan period, and the D ₁ scan period, 1, 2, 3, ...
-N shift clocks equal to the number of pixels in one line of n are generated.

The operation of the printer head drive signal generation circuit when various signals having the timings shown in FIG. 2 are applied will be described with reference to FIGS. 1 and 2. Before the series of operations, a clear pulse is generated. Is a 1-bit latch circuit 11
It is assumed that the voltage has been applied to 1n and cleared to the initial state. First, before the D ₄ scanning period, 1-bit shift registers 1 to n are driven by n shift clocks shown in FIG.
The n pieces of data D ₄ (not shown) transferred to
_The latch circuits 11 to 1n are simultaneously latched by the rising edge of the strobe pulse which rises prior to the _four scanning periods. Note that the n pieces of data D ₄ are 1
It is the MSB in the gradation data of each pixel of the line. Further, in this case, the 1-bit shift registers 1 to n are connected in series, and 1-bit data is sequentially transferred to the 1-bit shift registers 1 to n by n shift clocks, and 1 line is sequentially transferred. The data of any digit of the minute is transferred to the 1-bit shift registers 1 to n.

Then, during the D ₄ scanning period, n MSBs for one line latched by the latch circuits 11 to 1n
Data D ₄ is supplied to the gate circuits 21 to 2n.
At this time, since the enable signal having the pulse width of 8t shown in FIG. 2A is supplied to the gate circuits 21 to 2n, “1” is given.
In the output of the gate circuits 21 to 2n to which the data D ₄ is supplied, an output having a pulse width of which the period of the “H” level is 8t is generated, and the output drives the printer head. Further, the gate circuit 21~2n data D ₄ of "0" is supplied, the output of the "L" level is generated, the printer head is not driven.

In the D ₄ scanning period, the second digit data D ₃ of the grayscale data is set to 1 by n shift clocks.
The line data is transferred to the 1-bit shift registers 1 to n in the same manner as above, and the n pieces of data D ₃ are simultaneously transferred to the latch circuits 11 to 1n by the rising edge of the strobe pulse rising prior to the D ₃ scanning period. Latched. Next, in the D ₃ scan period, the n second digit data D _{3 for} one line latched by the latch circuits 11 to 1n are supplied to the gate circuits 21 to 2n. At this time, since the enable signal having a pulse width of 4t shown in FIG. 2 (a) is supplied to the gate circuit 21 to 2 n, the output of the gate circuit 21 to 2 n of data D ₃ is supplied a "1" , An output having a pulse width of which the period of the “H” level is 4t is generated, and the printer head is driven by this output. Further, the gate circuit 21~2n the data D ₃ of "0" is supplied, the output of the "L" level is generated, the printer head is not driven.

Further, in the D ₃ scanning period, the data D ₂ of the third digit of the gray scale data for one line is 1
The data is transferred to the bit shift registers 1 to n, and then the n pieces of data D ₂ are simultaneously latched by the latch circuits 11 to 1n by strobe pulses. And D
_{In the two} scanning periods, the n third digit data D _{2 for} one line latched by the latch circuits 11 to 1n are supplied to the gate circuits 21 to 2n.
Since the enable signal having the pulse width of 2t shown in (a) is supplied to the gate circuits 21 to 2n, the data D _{2 of} “1” is
Is supplied to the outputs of the gate circuits 21 to 2n,
An output having a pulse width of 2t for the "H" level period is generated, and the printer head is driven by this output. Further, the gate circuit 21~2n data D ₂ of "0" is supplied, the output of the "L" level is generated, the printer head is not driven.

In the D ₂ scan period, the LSB data D ₁ of the grayscale data is transferred to the 1-bit shift registers 1 to n for one line as in the above, and then n
The data D ₁ is latched by the strobe pulse 1
1 to 1n are simultaneously latched. And D ₁
In the scanning period, the data D ₁ of n LSBs for one line latched by the latch circuits 11 to 1n is supplied to the gate circuits 21 to 2n, and in this period,
Since the enable signal having a pulse width of 1t shown in (a) is supplied to the gate circuits 21 to 2n, the data D _{1 of} “1” is
Is supplied to the outputs of the gate circuits 21 to 2n,
An output having a pulse width of "t" for the "H" level period is generated, and the output drives the printer head. Further, the gate circuit 21~2n data D ₁ of the "0" is supplied, the output of the "L" level is generated, the printer head is not driven.

Since the printer head drive signal generation circuit operates in this way, the gradation data of a certain pixel is "101".
If it is “0”, a drive pulse of 8t is applied to the printer head corresponding to this pixel in the D ₄ scanning period and a 2t drive pulse is applied in the D ₂ scanning period, so that a total pulse of 10t is applied. It is driven by the width drive pulse. Therefore, the gradation of the pixel is relatively set to "10". Similarly, if the gradation data of a certain pixel is "1111," 8t-1
Since the pixel is driven by the sum of the driving pulses of t, the gradation of the pixel is relatively set to "15", and if the gradation data of a pixel is "0000", the driving pulse does not occur. Therefore, since the gradation of the pixel is relatively set to "0", an image of 16 gradations can be obtained comprehensively. Note that, as shown in FIG. 2A, about half of one scanning period is a rest period. Therefore, in order to obtain the same gray scale as in the conventional case, the emission brightness of the printer head is approximately doubled. There is a need to.

Next, FIG. 3 shows the configuration of the control circuit for producing the various signals described above. In the figure, 40 is a buffer for temporarily storing image data with gradation, 41 is a selector for selecting and outputting any digit data of the gradation data which is, for example, 4 bits, and 42 is from the buffer 40. Is a frame memory for storing image data of the CPU, and 43 is a microprocessor (CP which controls the control circuit).
U), 44 is a memory control circuit that controls writing and reading of the memory 42, 45 is a pulse generator that generates a clock for generating the operating clock of the CPU 43 and various timing signals, and 46 is various timings that receive the clock. A timing controller that creates a signal, 47 is a counter 1 that creates a select signal, and 48 is a counter 2 that creates an enable signal together with a decoder 49.

Explaining the operation of this control circuit, the CPU
Under the control of 43, the memory control circuit 44 writes the gradation-added image data input via the buffer 40 into the frame memory 42 for one frame. The frame memory 4 is set by the memory control circuit 44 at a predetermined timing.
The image data of one line read out from the 2 is input to the selector 41, one of the digits of the data of the data D ₄ to D ₁ is output as binary data one line by a select signal from the counter 1 . For example, when the data D _{4 of} MSB is selected by the selector 41, the data D ₄ of MSB for one line is used as serial data by the selector 4
It is output from 1.

As described above, since the selector 41 selects the data of any digit of the 4-digit data, 2 bits are required as the select signal, so that the counter 1 has 2 bits.
It is used as a stage counter and outputs 2 bits. The counter 1 receives the clock from the pulse generator 45 and counts the strobe pulses generated by the timing controller 46 every ¼ period of one line scanning period. D ₄ scan period or D ₁ obtained by dividing the line scan period into 4
The signal has a timing corresponding to the scanning period.

The timing controller 46 also generates a light emission time control pulse and supplies it to the counter 2.
The counter 2 counts with this light emission time control pulse as a reference, and outputs a 3-bit weighted pulse width of 8t to 1t, so that a 3-bit count value is supplied to the decoder 49. The decoder 49 is supplied with a select signal from the counter 1, that is, a signal indicating which scanning period is currently in progress. The decoder 49 receives this signal and weights 8t to 1 according to the scanning period.
An enable signal having a pulse width of t is generated. In addition,
The timing controller 46 also generates n necessary shift clocks for each scanning period.

Next, FIG. 4 shows an example in which a printer head drive signal generating circuit is constructed using a driver IC. In this figure, 30 to 33 are driver ICs, for example, n
/ 4-stage shift registers 30-1 to 33-1 and n / 4
It is composed of latch circuits 30-2 to 33-2 in stages. 34 to 37 are, for example, ICs of n / 4-stage gate circuits, and have a total of n outputs 1, 2, 3, ...
n is connected to each of n printer heads.
The gate circuits IC34 to IC37 are driver I
You may make it IC integrated with C30-33.

The operation of the printer head drive signal generating circuit constructed as described above is similar to that shown in FIG. 1 and will be briefly described. Binary data for one line at any digit of the grayscale data output from the selector 41 shown in FIG. 3 is supplied to the shift clocks supplied to the cascade-connected shift registers 30-1 to 33-1. Transfers are synchronized. As a result, at the end of each scanning period divided into four, one line of binary data,
For example, the MSB data D ₄ for one line is transferred to the shift registers 30-1 to 33-1.

This binary data is latched by the strobe pulse generated between the nth shift clock and the first shift clock of the next n groups.
33-2 are latched respectively, and the latch outputs are supplied to the gate circuits 34-37.
The gate circuits 34 to 37 are supplied with the enable signal shown in FIG. 2A, and the latch circuits 30-2 to 30-2.
Depending on the binary data latched in 33-2, the drive pulse having the same width as the enable signal is output as described above, or the drive pulse is controlled not to be output. The drive signals output from the gate circuits 34 to 37 to the n output lines 1, 2, 3, ... N are supplied to the respective n printer heads.

As a result, the n printer heads are respectively driven by the drive signals having the pulse widths of "0" to "15", and the printer head scans the photosensitive medium such as photographic paper for one frame. Sometimes it becomes possible to obtain an image with 16 gradations on the medium. In addition,
It is also possible to obtain a color image on the medium by using the image data as R, G, B color image data and the printer head as a color printer head capable of emitting R, G, B light.

[0033]

Since the present invention is configured as described above, the gradation control of the image to be printed can be controlled by the configuration of only the 1-bit shift register, the 1-bit latch means and the gate circuit for each pixel. As a result, the circuit scale can be reduced to a fraction of that of the conventional one, and an inexpensive printer head drive signal generation circuit can be obtained. Even when the driver IC is used to form the printer head drive signal generating circuit, as described above, only one bit shift register, one bit latch means and gate circuit are required for each pixel. Can be made as small as a few times, and it becomes possible to configure using an inexpensive IC.

[Brief description of drawings]

FIG. 1 is a diagram showing the principle of a printer head drive signal generation circuit of the present invention.

FIG. 2 is a diagram showing timings of various signals supplied to a printer head drive signal generation circuit of the present invention.

FIG. 3 is a block diagram of a control circuit that generates various signals to be supplied to the printer head drive signal generation circuit of the present invention.

FIG. 4 is a block diagram of a printer head drive signal generation circuit of the present invention configured by an IC.

FIG. 5 is a principle diagram of a conventional printer.

FIG. 6 is a diagram showing a configuration of a printer head used in a conventional printer.

FIG. 7 is a block diagram of a conventional printer head drive signal generation circuit.

FIG. 8 is a diagram showing the timing of a gradation-controlled printer head drive signal.

[Explanation of symbols]

 1 to n 1 bit shift register 11 to 1n 1 bit latch circuit 21 to 2n gate circuit 30 to 33 driver IC 34 to 37 gate IC 40 buffer 41 selector 42 frame memory 43 CPU 44 memory control circuit 45 pulse generator 46 timing controller 47, 48 counter 49 decoder

Claims (2)

[Claims] 1. A 1-bit shift register provided in a number equal to the number of pixels in one line, and a number equal to the number of pixels in one line for respectively latching 1-bit data stored in the 1-bit shift register. Latching means and 1-bit data latched by the latching means,
A number of gate circuits equal to the number of pixels in one line supplied as one input, and gradation data indicating the gradation of each pixel in one line is composed of a plurality of digits of bits. Of the gray scale data are sequentially shifted to the 1-bit shift register, and any one of the gray scale data is supplied to one input of the gate circuit. A printer head drive signal generation circuit, wherein an enable signal weighted by a power of 2 according to a digit is supplied to the other input of the gate circuit. 2. The shift register shifts the 1-bit data of each digit from the MSB to the LSB of the grayscale data, and the enable signal corresponds to the digit of the shifted 1-bit data. And a pulse width that is sequentially divided by a power of two.