JPH08111093A - Semiconductor storage device - Google Patents

Abstract

PURPOSE: To obtain a DRAM in which reduction of the area and speed-up of the operation are realized and the data in not damaged at the time of a readout operation with a simple constitution. CONSTITUTION: An auxiliary read amplifier 11 and an auxiliary write amplifier 12 are provided for every plural number of sense-amplifiers 51a and are connected to respective sense-amplifiers 51a by a pair of sub-input/output lines sub I/O, (#subI/O). Moreover, plural auxiliary read amplifiers 11 and auxiliary write amplifiers 12 share a pair of global input/output lines GI/O, (#GI/O). In a precharge state, sub-input/output lines subI/O, (#subI/O) and global input/output lines GI/O, (#GI/O) are set to be H, Levels and L, Levels, respectively. Consequently, the auxiliary readout amplifier 11 is activated only when data are generated in sub-input/output lines subI/O (#subI/O). Further, the auxiliary write amplifier 12 is activated only when the data are generated in the global input/ output lines GI/O, (#GI/O).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a dynamic RAM (DRAM).

[0002]

2. Description of the Related Art FIG. 18 is a block circuit diagram showing a structure of a conventional DRAM. The memory cell array 50 includes a large number of memory cells 50a that hold data. In addition, each memory cell array 50 is provided with a sense amplifier row 51 including a plurality of sense amplifiers 51a. Then, the memory cell 5 in the memory cell array 50
0a and one sense amplifier 51 in the sense amplifier row 51
and a are connected by a bit line BL.

Each array block including the memory cell array 50 and the sense amplifier row 51 is connected to a column decoder YD by a common column address selection line YS. In addition, the memory cell array 50 has a large number of word lines.
WL is connected and its word line WL is controlled by the word line driver WD. And each sense amplifier row 5
Each sense amplifier 51a in 1 is connected to the main amplifier 53 via a sub data bus 52. Further, the main amplifier 53 is connected to an input / output circuit (not shown) via a data bus 54.

In FIG. 18, in order to avoid making the drawing complicated, one word line WL, one bit line BL, one memory cell 50a, one sense amplifier 51a, one column. Only the address selection line YS is shown. Further, the bit line BL is composed of two inverted bit lines #BL (not shown) whose levels are inverted and which are paired. When reading data from the DRAM configured as described above, first, a desired memory cell 50a from which data is to be read is selected by the word line WL (and bit line BL).

Then, by raising the column address select line YS corresponding to the desired memory cell 50a, the data held in the memory cell 50a is amplified by the sense amplifier 51a and transferred to the sub data bus 52. It Sub data bus 52 to main amplifier 53
Is further amplified by the main amplifier 53 and output to the input / output circuit via the data bus 54. In such a DRAM, there is a problem that the operation is slow because the load capacity of the sub data bus 52 is larger than the load driving capacity of the sense amplifier 51a. Further, since the load capacitance of the sub-data bus 52 is larger than that of the bit line BL, the potential difference between the bit line pair between the bit line BL and the inverted bit line #BL is reduced when reading data (generally, "data There is also a problem called "destruction".

In order to improve this, in recent years, a DRAM provided with an auxiliary amplifier 61 as shown in FIG. 19 has been proposed. In this DRAM, one auxiliary amplifier 61 is provided for the sense amplifier array 51, and one main amplifier 62 is provided for the plurality of auxiliary amplifiers 61.
For example, 512 pairs of bit lines connected to each of the 512 sense amplifiers 51a (that is, bit line BL
And inverting bit line #BL totaled 1024)
The sub data bus 63 is formed by dividing each pair into 16 sets. An auxiliary amplifier 61 is connected to each sub-data bus 63, and 16 auxiliary amplifiers 61 are connected to one main amplifier 62 via a common global input / output line GI / O.

When reading data from the DRAM configured as described above, first, the word line WL (and the bit line WL
Desired memory cell 5 whose data is to be read by BL)
Select 0a. Then, by raising the column address selection line YS corresponding to the desired memory cell 50a, the data held in the memory cell 50a is
It is amplified by the sense amplifier 51 a and transferred to the sub data bus 63.

The data sent from the sub data bus 63 to the auxiliary amplifier 61 is amplified by the auxiliary amplifier 61 and transferred to the main amplifier 62 via the global input / output line GI / O. Then, the data is amplified by the main amplifier 62 and output to the input / output circuit (not shown) via the data bus 64. That is, in the DRAM shown in FIG. 18, data transfer is performed in array block units, whereas in the DRAM shown in FIG. 19, a plurality of sense amplifier units are transferred.

FIG. 20 shows the DR shown in FIGS. 18 and 19.
It is a circuit diagram which shows the sense amplifier 51a of AM. N-channel MOS transistors N51, N52 and P-channel M
The OS transistors P53 and P54 form a cross-coupled latch type sense amplifier 51a. The drains of the transistors N51 and P53 are connected to the bit line BL, and the drains of the transistors N52 and P54 are connected to the inverted bit line #BL.

The gates of the transistors N51 and P53 are connected to the inverted bit line #BL,
The gates of 52 and P54 are connected to the bit line BL.
The sources of the transistors N51 and N52 are connected to another sense amplifier 51a by a common source line VSN, and the sources of the transistors P53 and P54 are connected to another sense amplifier 51a by a common source line VSP.

The bit line BL and the input / output line I / O are connected via an N-channel MOS transistor N55.
The inverted bit line #BL and the inverted input / output line # I / O are N
It is connected through the channel MOS transistor N56. The gates of the transistors N55 and N56 are connected to the column address selection line YS. here,
Stray capacitors Ca and Cb are present in the input / output line I / O and the inverted input / output line # I / O, respectively. Further, stray capacitors C1 and C2 are present on the bit line BL and the inverted bit line #BL, respectively.

The sense amplifier 51a configured as described above
Column address select line YS
Is selected, the selected column address selection line
The transistors N55 and N56 connected to YS are turned on. Then, the turned-on transistor N55 (N56)
Via bit line BL (inverted bit line #BL) and I / O line
Capacitively coupled with I / O (inverting I / O line # I / O).

The capacitance of the input / output line pair of the input / output line I / O and the inverted input / output line # I / O (that is, the stray capacitor Ca,
The capacitance of Cb is the capacitance of the bit line pair of the bit line BL and the inverted bit line #BL (that is, the stray capacitors C1 and C).
If it is larger than 2), unless a sufficient potential difference is generated in the bit line pair, there is a possibility that the potential difference between the bit line pair is reduced (that is, the data in the bit line pair is destroyed) due to capacitive coupling between the two. There is.

Here, the sub data bus 52 shown in FIG.
The sub data bus 63 shown in FIG. 19 and FIG. 19 are configured by the input / output line I / O and the inverted input / output line # I / O shown in FIG. 20, respectively. However, as described above, the sub data bus 63 is connected to the sense amplifier 51a.
The wiring length is shorter than that of the sub-data bus 52 and the load capacity is also reduced due to the smaller number.

Therefore, the capacitance of the input / output line pair in the DRAM shown in FIG. 18 is several times the capacitance of the bit line pair, while the capacitance of the input / output line pair in the DRAM shown in FIG. 19 is the capacitance of the bit line pair. There is no big difference. Therefore, data destruction can be prevented in the DRAM shown in FIG. Further, in the DRAM shown in FIG. 18, it is necessary to wait until the potential difference of the bit line pair becomes sufficiently large before reading so that the data is not destroyed, whereas in the DRA shown in FIG.
M does not require this, and the read operation can be speeded up.

Further, in the DRAM shown in FIG. 19, a data bus (global input / output line) is formed on the memory cell array 50.
GI / O), the pattern area of the bus line can be reduced, which is effective for area saving, especially when many internal buses are required (for example, multi-bit DRAM).
FIG. 21 is a circuit diagram showing a sense amplifier and its peripheral circuit in a DRAM having a read gate improved to prevent data destruction. In this DRAM, the bit line
A read gate 71 and a write gate 72 are provided between BL and the inverted bit line #BL.

The read gate 71 is composed of MOS transistors TR1 to TR4. That is, the read data bus RDB is connected to the series circuit of the transistors TR1 and TR2, and the inverted read data bus #RDB is connected to the series circuit of the transistors TR3 and TR4. The gates of the transistors TR1 and TR3 are connected to the read auxiliary amplifier selection line YR. The gate of the transistor TR2 is connected to the bit line BL, the gate of the transistor TR4 is connected to the inversion bit line #BL, and the sources of the transistors TR2 and TR4 are grounded. Then, from the read auxiliary amplifier selection line YR, a control signal for activating the read gate 71 is given in synchronization with the read operation.

On the other hand, the write gate 72 has the same structure as the conventional gate. That is, write data bus WDB
The MOS transistor TW1 is connected between the bit line BL and the bit line BL, and the inverted write data bus #WDB and the inverted bit line #BL are connected.
And a MOS transistor TW2 is connected between and. The gates of the transistors TW1 and TW2 are connected to the write auxiliary amplifier selection line YW. Then, a control signal for activating the write gate 72 is given from the write auxiliary amplifier selection line YW in synchronization with the write operation.

Further, between the bit line BL and the inverted bit line #BL, the sense amplifier 5 having the same structure as shown in FIG. 20 is formed.
1a is connected. And word line WL and bit line
A memory cell 50a including an N-channel MOS transistor N61 and a capacitor Cm is connected to BL. The memory cell 50a connected to the inverted bit line #BL is not shown.

In the DRAM thus constructed, the read gate 71 amplifies the data of the bit line pair by one stage, so that the data destruction can be prevented. That is, this DRAM can be said to be a data amplification type data non-destructive read method of a bit line pair.
By the way, in this method, it is necessary to provide the read gate 71 and the write gate 72 for each sense amplifier 51a, so that the pattern area of the sense amplifier row 51 becomes large, which is disadvantageous in area saving.

Therefore, the read gate 71 shown in FIG.
There have been proposed various methods of providing the auxiliary amplifier 61 for each bit line pair (that is, for each sense amplifier 51a). FIG. 22 is a circuit diagram of a main part of one of the systems in which the read gate 73 and the write gate 74 are provided for each auxiliary amplifier 61 and is disclosed in “VLSI SYMPOSIUM ON CIRCUITS, 1991”.

The read gate 73 is composed of MOS transistors TR11 to TR15. That is,
A series circuit of transistors TR11 and TR12 is connected to the local input / output line LI / O, and a series circuit of transistors TR13 and TR14 is connected to the inverted local input / output line # LI / O. Then, each of the transistors TR12 and TR14 is connected to the transistor TR1.
Grounded through 5. The gate of the transistor TR15 is connected to the read auxiliary amplifier selection line YR.

The gates of the transistors TR11 and TR13 are connected to the section selection line SS for selecting the read gate 73. Furthermore, the transistor TR12
Is connected to the bit line BL, and the gate of the transistor TR14 is connected to the inverted bit line #BL. Then, a control signal for activating the read gate 73 is given from the read auxiliary amplifier selection line YR in synchronization with the read operation.

On the other hand, the write gate 74 is composed of MOS transistors TW11 and TW12. That is, the connection between the transistors TR11 and TR12 and the bit line BL
, And a transistor TW11 is connected between the transistor TW11 and the inverted bit line #BL. The gates of the respective transistors TW11 and TW12 are write auxiliary amplifier selection line YW.
It is connected to the. And write auxiliary amplifier select line
From YW, write gate 74 is synchronized with the write operation.
A control signal for activating the is provided.

Further, between the bit line BL and the inverted bit line #BL, as in FIG. 20, the transistors N55 and N5 are provided.
The sense amplifier 51a is connected via the switch 6. The read gate 73 and the write gate 74 configured as described above are provided not for each sense amplifier 51a but for each auxiliary amplifier 61. For example, "VLSI SYMPOSIUM
ON CIRCUITS, 1991 ”has eight sense amplifiers 51
One auxiliary amplifier 61 is provided for a. Therefore, the DRAM shown in FIG. 22 can save area compared to the DRAM shown in FIG.

Also, FIG. 23 shows one of the systems in which a read gate and a write gate are provided for each auxiliary amplifier 61, and the "1992 IEICE Spring Conference C-631"
FIG. 7 is a circuit diagram of a main part of the system disclosed in “DRAM array configuration suitable for high speed”. In this case, the sense amplifier 51a and the auxiliary amplifier 61 are connected to the sub input / output line subI / O and the inverted sub input / output line # which form the sub data bus 63.
Connected by subI / O.

The auxiliary amplifier 61 is provided in the word line lining portion (word line shunt portion) of the memory cell array 50. That is, in recent years, it has been required to reduce the wiring resistance of the word line WL and operate the DRAM at high speed. However, the word line WL is generally used by extending the gate of the MOS transistor, and if the line width of the word line WL is widened to reduce the wiring resistance, the pattern area becomes large, which is against the area saving.

Therefore, as shown in FIG. 24, the word line WL
A metal line ML made of aluminum or the like is formed on the upper part of the above, and the metal line ML and the word line WL are connected by a contact hole CH provided at a predetermined interval. For example, a sense amplifier row 51 is composed of 64 sense amplifiers 51a,
A contact hole CH is provided for each sense amplifier row 51.

In the memory cell array 50, a portion where the contact hole CH is provided is a portion generally called "word line lining portion" or "word line shunt portion". No memory cell 50a, bit line BL, or inverted bit line #BL is provided in this word line lining portion. Further, the sense amplifier 51 is not provided in the sense amplifier row 51 portion of this portion, and in the past, it was a so-called "vacant land". The auxiliary amplifier 61 is provided in this "vacant lot" portion, and the global input / output line GI / O and the inverted global input / output line # GI / O are provided to effectively use the space.

As shown in FIG. 23, the sense amplifier 51a
The configuration of is the same as that shown in FIG. Word line WLi
And bit line BL (and word line WL next to word line WLi
i + 1 and the inversion bit line #BL) each have a memory cell 50a including a transistor N61 and a capacitor Cm.
Is connected. The electrodes of the capacitors Cm on the side opposite to the side connected to the transistor N61 are
It is connected to the power line VCP. The power supply line VCP always has a voltage (= Vint / 1/2) of the internal power supply voltage Vint.
2) is being applied. The precharge voltage VBLP of the bit line BL and the inverted bit line #BL is also the internal power supply voltage Vin.
It is set to 1/2 the voltage of t (VBLP = VCP = V
int / 2).

The bit line BL and the sub input / output line subI / O are connected via the transistor N55, and the inverted bit line #BL and the inverted sub input / output line #sub I / O are connected to the transistor N55.
It is connected via 56. The auxiliary amplifier 61 is composed of six N-channel MOS transistors N71 to N76. That is, the transistors N71, N72, N73 are connected in series between the sub input / output line subI / O and the ground, and the transistors N74, N74, N74 are connected between the inverted sub input / output line #sub I / O and the ground. N75 and N76 are connected in series. The gate of the transistor N73 whose source is grounded is connected to the sub input / output line subI / O, and the gate of the transistor N76 whose source is grounded is connected to the inverted sub input / output line #sub I / O. . The gates of the transistors N71 and N74 are connected to the write auxiliary amplifier selection line YW, and the transistors N72 and N7 are connected.
The gate of 5 is connected to the read auxiliary amplifier selection line YR. Then, from the read auxiliary amplifier selection line YR, an H level control signal is given in synchronization with the read operation. On the other hand, from the write auxiliary amplifier selection line YW, an H level control signal is given in synchronization with the write operation. Further, the connection portion of each transistor N71, N72 is connected to the global input / output line GI / O, and each transistor N74,
The connection portion of N75 is connected to the inverted global input / output line # GI / O.

Next, the read operation of the DRAM thus constructed will be described with reference to the time chart shown in FIG. Since the operations of the memory cell 50a and the sense amplifier 51a are known, detailed description thereof will be omitted. Before performing read operation, sub I / O line subI
/ O, inverted sub I / O line # sub I / O, global I / O line
GI / O and inverted global I / O line # GI / O are all precharged to H level.

Then, when the desired word line WLi is raised to the H level, the bit line pair of the bit line BL and the inverted bit line #BL is set in accordance with the state of the memory cell 50a connected to the word line WLi. Voltage changes. The sense amplifier 51a amplifies the change in the voltage of the bit line pair and causes the bit line pair to fully swing between the internal power supply voltage Vint and the ground level (= 0V).

Here, for example, it is assumed that the bit line BL is at L level and the inverted bit line #BL is at H level. Then, when the desired column address selection line YS is raised to the H level, the transistors N55 and N56 connected to the column address selection line YS are turned on. Then, the sub input / output line subI / O is discharged from the H level to the L level, and the inverted sub input / output line # subI / O is held at the H level.

When the levels of the sub input / output line sub I / O and the inverted sub input / output line #sub I / O are fixed, an H level control signal is applied from the read auxiliary amplifier selection line YR to turn on the transistors N72 and N75. . Then, the transistor N76 remains on and the transistor N73 remains off. Therefore, the turned-on transistors N75 and N7
The inverted global input / output line # GI / O is discharged from H level to L level via 6. On the other hand, the global input / output line GI / O is kept at H level.

As described above, the global input / output line GI / O (inverted global input / output line # GI / O) is supplied to the discharged sub input / output line subI / O (inverted sub input / output line #sub I / O). ) Remains unchanged and the H level in the precharged state is maintained. On the other hand, for the discharged sub I / O line sub I / O (reverse sub I / O line #sub I / O), the inverted global I / O line # GI / O (global I / O line GI / O)
O) is discharged to L level.

As a result, the auxiliary amplifier 61 amplifies the data from the sub input / output line sub I / O and the inverted sub input / output line #sub I / O to generate the global input / output line GI / O and the inverted global input / output line. # Can be transferred to GI / O. Also,
As a technique similar to the conventional technique shown in FIG. 23, a technique in which only a part of a read auxiliary amplifier is shared with a plurality of memory cells is described in Japanese Patent Application Laid-Open No. 1-185896.

FIG. 26 is a simplified description of the diagram shown in this publication. That is, the read auxiliary amplifier includes transistors Q14, Q15, Q16, Q1.
7, Q18, Q19, of which transistors Q14, Q15 are shared by a plurality of bit line pairs BL, #BL. When the sense amplifier is driven, the bit line
BL and the inverted bit line #BL are activated, and the signal of this bit line pair is input to the transistors Q16 and Q17. Further, the transistors Q18 and Q19 are selected by the control signal. Thus, the transistors Q14 to Q19 as the read auxiliary amplifier are activated.

That is, the signals of the bit line pair BL, #BL are
Transistors Q14 to Q1 as auxiliary read amplifiers
It is amplified by 9 and transferred to the data line pair OLm, #OLm via the data line pair OLs, #OLs.

[0040]

In the conventional example shown in FIG. 23, each transistor N7 is in the precharged state.
When N2 and N75 are turned on, each transistor N73 and N7
Since 6 is already turned on, each transistor N turned on
72, N73 and the transistors N75, N76 form conductive paths. Then, both the global I / O line GI / O and the inverted global I / O line # GI / O become L level, and it becomes impossible to precharge to H level.

For the same reason, the sub input / output line su
If each of the transistors N72 and N75 is turned on before the level of the bI / O and the inverted sub input / output line # subI / O is sufficiently determined, a malfunction may occur. Therefore, the control signal from the read auxiliary amplifier selection line YR must be accurately synchronized with the column address selection line YS.

Further, the global input / output line GI / O and the inverted global input / output line # GI / O are connected to a plurality of auxiliary amplifiers 61.
It is shared with. Therefore, the auxiliary amplifier 61 of the inactive memory cell array 50 must be separated from the global input / output line GI / O and the inverted global input / output line # GI / O.
In the precharge state described above, each transistor N7
2, N75 is turned on, and the same problem as in the case where the conduction path is formed occurs. Therefore, the auxiliary amplifier 61 of the inactive memory cell array 50 is connected to the global input / output line GI / O.
And the inverted global input / output line #G I / O, and the control signal from the read auxiliary amplifier select line YR needs to be controlled with care.

As a result, the circuit for controlling the read auxiliary amplifier selection line YR becomes complicated, and an operation margin for operating at various timings described above is required, which impedes high speed operation. Further, the read auxiliary amplifier selection line YR must be provided for each auxiliary amplifier 61, and the pattern area occupied by all the read auxiliary amplifier selection lines YR becomes considerably large. After all, D of the method shown in FIG.
In the RAM, when the read auxiliary amplifier selection line YR is provided to control the auxiliary amplifier 61, area saving is hindered and sufficient speed cannot be realized.

By the way, in the DRAM of the system shown in FIG. 23, not only is there a problem with the read auxiliary amplifier select line YR, but there is a similar problem with the write auxiliary amplifier select line YW. That is, write auxiliary amplifier select line YW
The circuit for controlling the write operation becomes complicated, and various timings must be optimally adjusted in the write operation. Further, the write auxiliary amplifier selection line YW must be provided for each auxiliary amplifier 61, and the pattern area occupied by all the write auxiliary amplifier selection lines YW becomes considerably large. Therefore, even when the write auxiliary amplifier selection line YW is provided to control the auxiliary amplifier 61, the area saving is hindered and the high speed operation cannot be sufficiently realized.

Also in the DRAM of the system shown in FIG. 22, since the read auxiliary amplifier selection line YR and the write auxiliary amplifier selection line YW are provided, the DR of the system shown in FIG.
It will cause the same problem as AM. Further, in the conventional example shown in FIG. 26, the transistors Q16 to Q1 which are a part of the read auxiliary amplifier are provided for each bit line pair BL, #BL.
Since 9 is required, there is a problem that the number of circuit elements increases correspondingly, and the area saving is obstructed as in the conventional example described above.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor memory device which can realize area saving and high speed operation and which does not cause data destruction during a read operation. It is to provide by an extremely simple structure.

[0047]

According to the first aspect of the present invention,
A plurality of memory cell arrays, a column address selection line shared by each memory cell array, and a plurality of sense amplifiers provided in each of the memory cell arrays are connected to the respective sense amplifiers by a pair of sub input / output lines. An auxiliary read amplifier, a pair of global input / output lines shared by the respective auxiliary read amplifiers, and a main read amplifier connected to the global input / output line. In the semiconductor memory device which is amplified by the auxiliary read amplifier and transfers the amplified data to the main read amplifier via the global input / output line, the auxiliary read amplifier is supplied from the sub input / output line. The point is that the drive is controlled based on only the data.

According to a second aspect of the present invention, in the semiconductor memory device according to the first aspect, the auxiliary read amplifier has a drain connected to each of the pair of global input / output lines, and the pair of sub input / output lines. Of a pair of IGFETs whose gates are connected to each
The gist is that the source voltage of the GFET is made equal to the precharge voltage of the pair of sub input / output lines.

According to a third aspect of the present invention, in the semiconductor memory device according to the second aspect, the source voltage of the IGFET of the auxiliary read amplifier in the activated memory cell array is supplied to the sense amplifier in the inactive memory cell array. The gist is that the precharge voltage of the connected bit line is made equal. According to a fourth aspect of the present invention, in the semiconductor memory device of the second aspect, the precharge voltage of the sub input / output line in the activated memory cell array is changed to the precharge voltage of the sub input / output line in the inactivated memory cell array. Is set to a different voltage value, and only the source voltage of the IGFET of the auxiliary read amplifier in the activated memory cell array is changed so as to follow the precharge voltage of the sub input / output line to which the IGFET is connected. This is the gist.

According to a fifth aspect of the present invention, in the semiconductor memory device of the second aspect, the precharge voltage of the activated sub-I / O line in the memory cell array is changed to the inactive sub-I / O line in the memory cell array. A voltage value different from the precharge voltage is set, and the source voltage of all the IGFETs of the auxiliary read amplifiers is set to a voltage value equal to the precharge voltage of the sub input / output line in the activated memory cell array and activated. The gist of the invention is to activate only the auxiliary read amplifier in the memory cell array.

That is, the auxiliary read amplifier is activated based on only the data generated in the sub input / output line. Therefore, it is possible to omit a complicated control signal for controlling the auxiliary read amplifier, which requires an operation margin. as a result,
The speed can be increased by the operation margin of the control signal of the auxiliary read amplifier. Further, the area can be saved by the area occupied by the signal line of the control signal and the circuit that generates the control signal. Further, since the data read out to the sub input / output line is once amplified by the auxiliary read amplifier and then transferred to the global input / output line, the data is not destroyed during the read operation.

In particular, according to the second aspect of the invention, the above can be realized with a simple structure without using any special control means. Further, in the inventions of claims 3 to 5, in addition to the effect of claim 2, no special source voltage is required, so there is no need to provide a separate source voltage generating circuit,
The circuit configuration is simple and contributes to area saving.

[0053]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) A first embodiment of the present invention will be described below with reference to FIGS. In the present embodiment, the same components as those in the conventional example shown in FIGS. 18 to 25 have the same reference numerals, and detailed description thereof will be omitted. The block circuit diagram of the DRAM of the present embodiment is the same as the conventional example shown in FIG.

FIG. 6 is a plan view showing an arrangement example on the actual semiconductor chip 1 of the 16-megabit DRAM of the present embodiment shown in FIG. Four 4-megabit memory blocks 2 are arranged on the semiconductor chip 1. A row selection signal #RA is provided above and below the outer periphery of the semiconductor chip 1.
Various pads 3 for S, column selection signal #CAS, write signal #WE, output signal #OE, input / output signal I / O, address Address, and power supplies VCC and VSS are arranged.

Further, a main clock 4 is arranged in the center of the semiconductor chip 1. A row decoder 5 including a word line driver WD is arranged between the upper and lower memory blocks 2, and a column decoder YD is arranged between each memory block 2 and the main clock 4. Further, a main amplifier row 62a including a plurality of main amplifiers 62 is arranged between each column decoder YD and the main clock 4.

By the way, as shown in FIG. 6, each of the column decoders YD includes the semiconductor chip 1 with the main clock 4 interposed therebetween.
It is located in the center of. Then, by using the second metal line for the column address selection line YS, one column address selection line YS is provided between different memory cell arrays 50.
Are shared. In this case, the column address selection line YS
I is composed of the transistors N55 and N56 as they are.
There is a method of connecting to the / O gate (hereinafter referred to as method 1). Further, the signal line for selecting each memory cell array 50 and the column address selection line YS are logically operated, and the column address selection line YS of the activated memory cell array 50 is selected.
There is also a method of turning on only the I / O gate (that is, each of the transistors N55 and N56) corresponding to (indicated as GYS in FIGS. 1, 2, and 4) (hereinafter referred to as method 2). .

Method 2 is used in the first embodiment. That is, in the first embodiment, the activated memory cell array 5
0 sub I / O line subI / O and inverted sub I / O line #subI
Only / O is connected to the corresponding bit line BL and inverted bit line #BL according to the column address select line YS. Therefore, in the read operation, only the sub input / output line sub I / O and the inverted sub input / output line #sub I / O connected to the auxiliary read amplifier 11 to be selected have a voltage different from the precharge voltage VP. .

For other sub input / output lines sub I / O and inverted sub input / output line #sub I / O, the precharge voltage V
It remains P. Therefore, each transistor P1, P2
If the gate voltage (= precharge voltage VP) and the source voltage VS are equal (VP = VS), the voltage may be the internal power supply voltage Vint or the voltage Vint / 2 (= VCP = VBLP).

FIG. 1 is a circuit diagram of a main part of the DRAM of this embodiment. In FIG. 1, only the configuration of the auxiliary amplifier 61 is different from the conventional example shown in FIG.
However, the sources of the transistors N51 and N52 are connected to the common source line VSN, and the N-channel MOS
It is connected to the drain of the transistor N62. The source of the transistor N62 is grounded, and the gate is connected to the control signal line SN.

This is to speed up the sensing operation by reducing the load on the common source line VSN during the sensing operation of the sense amplifier 51a. That is, the common source line VSN falls to the L level during the sensing operation, but at that time, the control signal line SN rises to the H level to turn on the transistor N62. As a result, the sources of the transistors N51 and N52 are grounded via the turned-on transistor N62, which reduces the load on the common source line VSN.

As shown in FIG. 1, the auxiliary amplifier 61 of this embodiment includes an auxiliary read amplifier 11 and an auxiliary write amplifier 12.
Composed of and. The auxiliary read amplifier 11 is IGF
P-channel MOS as ET (Insulated Gate FET)
It is composed of transistors P1 and P2. That is, the gate of the transistor P1 is connected to the sub input / output line subI / O, and the gate of the transistor P2 is connected to the inverted sub input / output line # subI / O. Also, the transistor P1
Is connected to the global I / O line GI / O, and the drain of the transistor P2 is inverted global I / O line #GI.
Connected to / O. Then, the transistors P1 and P
The internal power supply voltage Vint is applied to the source of 2.

On the other hand, the auxiliary write amplifier 12 is an IGFET
Of N channel MOS transistors N1 and N2. That is, the gate of the transistor N1 is connected to the global input / output line GI / O,
The gate of 2 is connected to the inverted global input / output line # GI / O. The drain of the transistor N1 is connected to the sub input / output line subI / O, and the drain of the transistor N2 is connected to the inverted sub input / output line # subI / O. And
The sources of the transistors N1 and N2 are grounded.

Next, the read operation of the DRAM thus constructed will be described with reference to the time chart shown in FIG. Since the operations of the memory cell 50a and the sense amplifier 51a are known, detailed description thereof will be omitted. Before performing read operation, sub I / O line subI
/ O and inverted sub input / output line #sub I / O are precharged to H level, and global input / output line GI / O and inverted global input / output line # GI / O are precharged to L level. Then, the gate voltage of each of the transistors P1 and P2 (that is, the precharge voltage VP of the sub input / output line subI / O and the inverted sub input / output line #sub I / O) and the source voltage VS (that is, the internal power supply voltage Vint) are Will be equal.
At this time, since the transistors P1 and P2 are off, the auxiliary read amplifier 11 becomes inactive.

Then, when the desired word line WLi is raised to the H level, the bit line pair of the bit line BL and the inverted bit line #BL is set according to the state of the memory cell 50a connected to the word line WLi. Voltage changes. The sense amplifier 51a amplifies the change in the voltage of the bit line pair and causes the bit line pair to fully swing between the internal power supply voltage Vint and the ground level (= 0V).

Here, for example, it is assumed that the bit line BL is at L level and the inverted bit line #BL is at H level. When the desired column address selection line GYS is raised to H level, the transistors N55 and N56 connected to the column address selection line GYS are turned on. Then
The sub input / output line sub I / O is discharged from the H level to the L level, and the inverted sub input / output line #sub I / O is held at the H level.

Therefore, the transistor P1 of the auxiliary read amplifier 11 remains on and the transistor P2 remains off. Then, the internal power supply voltage Vint is applied to the global input / output line GI / O through the turned-on transistor P1 and is charged from the L level to the H level. on the other hand,
The inverted global input / output line # GI / O is maintained at the L level.

As described above, the global input / output line GI / O (inverted global input / output line # GI / O) is supplied to the sub input / output line subI / O (reversed sub input / output line #sub I / O) which is not discharged. Does not change and the L level in the precharged state is held. On the other hand, for the discharged sub I / O line sub I / O (reverse sub I / O line #sub I / O), the inverted global I / O line # GI / O (global I / O line GI / O)
O) is charged to H level.

As a result, the auxiliary read amplifier 11 amplifies the data from the sub input / output line subI / O and the inverted sub input / output line #sub I / O, and the global input / output line GI / O and the inverted global input / output. Can be transferred to line # GI / O.
Here, since the other sub input / output line sub I / O and the inverted sub input / output line #sub I / O in the same memory cell array 50 remain in the precharged state, all the connected auxiliary read amplifiers 11 are deactivated. Has become. Further, the auxiliary read amplifier 11 in another inactive memory cell array 50 is also inactive. That is, in the precharged state, all the auxiliary read amplifiers 11 connected to the same global input / output line GI / O and inverted global input / output line # GI / O are inactive.

During the read operation, only the auxiliary read amplifier 11 selected by the desired column address selection line GYS is activated, and the same global input / output line GI / O is selected.
Also, all the other auxiliary read amplifiers 11 connected to the inverted global input / output line # GI / O remain inactive and do not operate. FIG. 3 is a time chart during a read operation in another inactive memory cell array 50.

Therefore, the auxiliary read amplifier 1 of the present embodiment
1, it is not necessary to provide the read auxiliary amplifier selection line YR unlike the conventional auxiliary amplifier 61 shown in FIGS. 22 and 23. Therefore, read auxiliary amplifier select line
It is not necessary to control the control signal from YR, and the circuit for controlling the read auxiliary amplifier selection line YR is not necessary.

The activation of the memory cell array 50 means that the sense amplifier 51a in the memory cell array 50 is activated.
Are activated, and the memory cells 50a selected by the word line WL are charged / discharged for every bit line pair in the memory cell array 50. Further, the word line lining portion provided with the auxiliary amplifier 61 originally has an n-well, and if the n-well which has not been used in the conventional example shown in FIG. 23 is used, a P-channel MOS transistor is used. It is easy to form P1 and P2.

Next, the write operation of the DRAM thus configured will be described with reference to the time chart shown in FIG. Since the operations of the memory cell 50a and the sense amplifier 51a are known, detailed description thereof will be omitted. Even before performing the write operation, as before performing the read operation, the sub input / output line sub I / O and the inverted sub input / output line #sub I / O are precharged to the H level.
The global I / O line GI / O and the inverted global I / O line # GI / O are precharged to the L level.

At this time, since the transistors N1 and N2 are off, the auxiliary write amplifier 12 is inactive. Then, when the desired word line WLi is raised to the H level, the memory cell 5 connected to the word line WLi
The voltage of the bit line pair of the bit line BL and the inverted bit line #BL changes according to the state of 0a. The sense amplifier 51a amplifies the change in the voltage of the bit line pair, and the internal power supply voltage V
The bit line pair is fully swung between int and the ground level (= 0V).

Here, for example, it is assumed that H level data is written to the global I / O line GI / O and L level data is written to the inverted global I / O line # GI / O. Then, the transistor N1 of the auxiliary write amplifier 12 turns on and the transistor N2 remains off. Therefore, the sub I / O line su
bI / O is discharged from H level to L level, and the inverted sub input / output line #sub I / O is maintained at H level.

Then, a desired column address selection line GYS
Rises to H level, the column address selection line
The transistors N55 and N56 connected to YS are turned on. Then, the bit line BL becomes L level and the inversion bit line #BL becomes H level, and the data corresponding to the levels of the bit line BL and the inversion bit line #BL is written in the memory cell 50a.

As described above, the sub input / output line subI / O (inverted sub input / output line #sub I / O) is supplied to the L level global input / output line GI / O (inverted global input / output line # GI / O). ) Remains unchanged and the H level in the precharged state is maintained. On the other hand, the inverted sub input / output line # subI / O (sub input / output line sub I / O) is discharged to the H level global input / output line GI / O (inverted global input / output line # GI / O). It becomes L level.

As a result, the auxiliary write amplifier 12 outputs the global input / output line GI / O and the inverted global input / output line #GI.
The data from / O can be amplified and transferred to the sub input / output line sub I / O and the inverted sub input / output line #sub I / O.
Here, in the precharge state, the auxiliary write amplifier 1 connected to another sub input / output line sub I / O and inverted sub input / output line #sub I / O in the same memory cell array 50.
All 2 are inactive. In addition, the auxiliary write amplifier 12 in another inactive memory cell array 50 is also inactive. That is, in the precharge state, the auxiliary write amplifier 12 connected to the same global input / output line GI / O and inverted global input / output line # GI / O
Are all inactive.

Then, during the write operation, only the auxiliary write amplifier 12 selected by the desired column address selection line GYS is activated, and the same global input / output line GI / O
Also, all the other auxiliary write amplifiers 12 connected to the inverted global input / output line # GI / O remain inactive and do not operate. FIG. 5 is a time chart during a write operation in another inactive memory cell array 50.

Therefore, the auxiliary write amplifier 1 of this embodiment
2, it is not necessary to provide the write auxiliary amplifier selection line YW unlike the conventional auxiliary amplifier 61 shown in FIGS. 22 and 23. Therefore, write auxiliary amplifier select line
It is not necessary to control the control signal from YW, and the circuit for controlling the write auxiliary amplifier selection line YW is also unnecessary.

As described above, in this embodiment, the auxiliary read amplifier 11 is driven and controlled by the read data from the sub input / output line subI / O and the inverted sub input / output line # subI / O. The auxiliary write amplifier 12 is driven and controlled by the write data from the global I / O line GI / O and the inverted global I / O line # GI / O. That is, the auxiliary amplifier 61 of the present embodiment is capable of completely data-driven data transfer in both the read operation and the write operation. Therefore, in the present embodiment, it is possible to omit the control signals (control signals from the read auxiliary amplifier selection line YR and the write auxiliary amplifier selection line YW) that are complicated and require an operation margin for controlling the auxiliary amplifier 61.

Further, the auxiliary amplifier 61 of the present embodiment has a simpler structure than the auxiliary amplifier 61 of the conventional example shown in FIGS. 22 and 23, and therefore can be easily embodied.
Further, in the present embodiment, as shown in FIG. 6, an extra data bus (and the main amplifier 53 in FIG.
It is not necessary to route a control signal line) for controlling the above on the semiconductor chip 1. That is, the data bus 64 shown in FIG. 19 may be arranged at the portion of the main clock 4, and since there is no data bus in the peripheral portion of the semiconductor chip 1, the area can be saved.

Therefore, in this embodiment, all the advantages of the conventional DRAM shown in FIG. 23 can be provided and all the problems of the prior art can be solved. (Second Embodiment) On the other hand, in the case of Method 1, I corresponding to the column address selection line YS of the inactive memory cell array 50
The / O gate also turns on. Therefore, the inactive (that is, precharged) bit line BL and inverted bit line #BL are connected to the sub input / output line subI / O and inverted sub input / output line #sub I / O.

Therefore, in the case of the method 1, the precharge voltage VBLP of the bit line BL and the inverted bit line #BL and the precharge voltage VP of the sub input / output line subI / O and the inverted sub input / output line #sub I / O. And must be equal. In this case as well, the gate voltage (= precharge voltage VP) and the source voltage VS of the transistors P1 and P2 must be equal (VBLP = VP = VS).

However, in the method 1, unlike the method 2, it is not necessary to take the logic between the signal line for selecting each memory cell array 50 and the column address selection line YS. Therefore, in the method 1, it is not necessary to provide a signal line for selecting each memory cell array 50 or a circuit for taking a logic,
Area saving can be achieved by the method 2. FIG. 7 is a circuit diagram of a main part of a DRAM according to the second embodiment which embodies the method 1. Note that, in FIG. 7, only the following is different from the first embodiment shown in FIG. Therefore, in the present embodiment, the same components as those in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. Further, in the present embodiment, description of the same operation as that of the first embodiment will be omitted.

The source voltage VS of each of the transistors P1 and P2 of the auxiliary read amplifier 11 is not the internal power supply voltage Vint but the precharge voltage VBLP of the bit line BL and the inverted bit line #BL. Sub I / O line sub I / O and inverted sub I / O line #sub I / O
A clamper (precharge) 13 is provided at O.

The clamper 13 is composed of P channel MOS transistors P3 and P4. That is, the sources of the transistors P3 and P4 are the sub input / output lines su.
It is connected to bI / O and inverted sub I / O line #sub I / O, and the gate is grounded. In addition, the transistors P3 and P
The drain of 4 has a bit line BL and an inverted bit line #BL.
The precharge voltage VBLP is applied.

Therefore, the turned-on transistors P3 and P
4, the precharge voltage VBLP of the bit line BL and the inverted bit line #BL is applied to the sub input / output line sub I / O and the inverted sub input / output line #sub I / O. Therefore, the precharge voltage VP of the sub input / output line sub I / O and the inverted sub input / output line #sub I / O, the bit line BL, and the inverted bit line #BL
Becomes equal to the precharge voltage VBLP.

In the write operation, the sub input / output line
In order to write H level data to the sub I / O or the inverted sub input / output line #sub I / O, each of the transistors P3 and P4 must be a normally-on type. That is, in this embodiment, the clamper 13 can be regarded as a pull-up circuit at the time of write operation, and the auxiliary write amplifier 12 can be regarded as a pull-down circuit at the time of write operation.

It is also possible to apply a control signal to the gates of the transistors P3 and P4 to control the read and write operations. However, in this case, since it is necessary to provide a control signal to be provided to the gates of the transistors P3 and P4 and a control signal line thereof, complete data-driven data transfer as described above cannot be performed.

FIG. 2 is a time chart during a read operation in the activated memory cell array 50.
FIG. 8 is a time chart during a read operation in another inactive memory cell array 50. FIG. 4 is a time chart during a write operation in the activated memory cell array 50. FIG. 9 is a time chart during a write operation in another inactive memory cell array 50.

(Third Embodiment) In Method 1 (that is, the sub input / output line subI of the inactive memory cell array 50)
/ O and inverted sub input / output line #sub I / O precharge voltage VP is made equal to precharge voltage VBLP of bit line BL and inverted bit line #BL), activated sub input / output line of memory cell array 50 Only the voltage of sub I / O and inverted sub I / O line #sub I / O is set to precharge voltage VBLP.
There is a method (hereinafter, referred to as method 3) of doing the above.

That is, in the method 3, the gain of the auxiliary read amplifier 11 is apparently increased, so that the read operation can be made faster. FIG. 10 is a circuit diagram of a main part of a DRAM according to the third embodiment which embodies the method 3.
Note that, in FIG. 10, only the following is different from the second embodiment shown in FIG. 7. Therefore, in the present embodiment, the same components as those in the second embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. Further, in the present embodiment, description of the same operation as that of the second embodiment will be omitted.

The sources of the transistors P1 and P2 of the auxiliary read amplifier 11 are connected to the common source line VSP. The drains of the transistors P3 and P4 of the clamper 13 are connected to the common source line VSP. In the inactive memory cell array 50, the voltage of the common source line VSP is the precharge voltage VBL of the bit line BL and the inverted bit line #BL.
It is equal to P and deactivates the sense amplifier 51a (VS = VP = VSP = VBLP).

On the other hand, in the activated memory cell array 50, the voltage of the common source line VSP is the internal power supply voltage Vint.
However, the condition of (VS = VP = VSP) is still maintained, and no inconvenience occurs in the operation. FIG.
9 is a time chart during a read operation in the activated memory cell array 50. FIG. 8 is a time chart during a read operation in another inactive memory cell array 50. FIG. 12 is a time chart during a write operation in the activated memory cell array 50. FIG. 9 is a time chart during a write operation in another inactive memory cell array 50.

(Fourth Embodiment) FIG. 13 is a circuit diagram of an essential part of a DRAM according to a fourth embodiment in which the method 3 is embodied.
Note that, in FIG. 13, the transistor N of the auxiliary write amplifier 12 is different from that of the third embodiment shown in FIG.
It is only that the sources of 1, N2 are connected to the common source line VSN. Therefore, in the present embodiment, the same components as those in the third embodiment have the same reference numerals, and detailed description thereof will be omitted. Further, in the present embodiment, description of the same operation as that of the third embodiment will be omitted.

In the inactive memory cell array 50,
The voltage of the common source line VSP is equal to the precharge voltage VBLP of the bit line BL and the inverted bit line #BL,
The sense amplifier 51a is deactivated (VS = VP =
VSN = VBLP). Therefore, the auxiliary light amplifier 12 also stops operating. In the inactive memory cell array 50, the sub input / output line subI / O or the inverted sub input / output line #sub
No data is written to the I / O. Therefore, even if bit line BL or inverted bit line #BL and sub I / O line subI / O
Or, even if the inverted sub I / O line #sub I / O is connected, unnecessary data can be transferred to the bit line BL and the inverted bit line #BL.
The unnecessary operation of writing to is stopped.

FIG. 11 is a time chart during a read operation in the activated memory cell array 50. FIG. 8 is a time chart during a read operation in another inactive memory cell array 50. Figure 14
6 is a time chart during a write operation in the activated memory cell array 50. Incidentally, "VrS" indicates the source voltage VrS of each of the transistors P1 and P2 of the auxiliary read amplifier 11, and "VwS" indicates the source voltage VwS of each of the transistors N1 and N2 of the auxiliary write amplifier 11. FIG.
[FIG. 6] is a time chart during a write operation in another inactive memory cell array 50.

(Fifth Embodiment) FIG. 16 is a circuit diagram of a main part of a DRAM according to a fifth embodiment of the method 3.
16 is different from that of the fourth embodiment shown in FIG. 13 in that each transistor P of the auxiliary read amplifier 11 is different.
N-channel MOS transistor N is connected to the sources of 1, P2.
An appropriate voltage such as the internal power supply voltage Vint (however,
The voltage is higher than the precharge voltage VBLP of the bit line BL and the inverted bit line #BL.
The gate of the transistor N3 is connected to the control signal line SN. Therefore, in the present embodiment, the same components as those in the fourth embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. Further, in the present embodiment, description of the same operation as that of the third embodiment will be omitted.

Only in the activated memory cell array 50, the voltage of the control signal line SN is at H level. Therefore, only the transistor N3 of the activated memory cell array 50 is turned on, and only the auxiliary read amplifier 11 of the activated memory cell array 50 is activated (VS =
VP = Vint). Therefore, in the present embodiment, the load on the common source line VSP can be reduced as compared with the third embodiment, and the speeding up of the sensing operation is not hindered.

FIG. 11 is a time chart during a read operation in the activated memory cell array 50. FIG. 8 is a time chart during a read operation in another inactive memory cell array 50. Figure 14
6 is a time chart during a write operation in the activated memory cell array 50. FIG. 15 is a time chart at the time of a write operation in another inactive memory cell array 50.

(Sixth Embodiment) FIG. 17 is a circuit diagram of an essential part of a DRAM of the sixth embodiment. In addition, in FIG.
The difference from the second embodiment shown in FIG.
(Ie, pull-up circuit) transistors P3,
It is only that the gates of P4 are connected to the global I / O line GI / O and the inverted global I / O line # GI / O, respectively.

In this embodiment, in the write operation,
Similarly to the auxiliary write amplifier 12 (that is, the pull-down circuit), the clamper 13 is also driven by the global input / output line GI / O and the inverted global input / output line # GI / O. With respect to other operations, the present embodiment and the second embodiment are all the same, so description thereof will be omitted.

FIG. 2 is a time chart during a read operation in the activated memory cell array 50.
FIG. 8 is a time chart during a read operation in another inactive memory cell array 50. FIG. 4 is a time chart during a write operation in the activated memory cell array 50. FIG. 9 is a time chart during a write operation in another inactive memory cell array 50.

The present invention is not limited to the above embodiments, but may be carried out as follows. 1) The P-channel MOS transistors P1 and P2 of the auxiliary read amplifier 11 are replaced with N-channel MOS transistors, and the N-channel MOS transistors N1 and N2 of the auxiliary write amplifier 12 are replaced with P-channel MOS transistors.

In this case, the level of each input / output line in the precharged state is opposite to that in each of the above-mentioned embodiments. That is, the sub input / output line subI / O and the inverted sub input / output line #sub
I / O is precharged to L level, and global I / O line GI / O and inverted global I / O line # GI / O are precharged to H level. 2) Each P-channel MOS transistor P of the clamper 13
3 and P4 are replaced with N-channel MOS transistors.

3) Instead of connecting the drains of the transistors P1 and P2 of the auxiliary read amplifier 11 to the global input / output line GI / O and the inverted global input / output line # GI / O, respectively, the inverted global input / output line # GI / O and global I / O line Connect to GI / O. At the same time, the gates of the transistors N1 and N2 of the auxiliary write amplifier 12 are not connected to the global input / output line GI / O and the inverted global input / output line # GI / O, but are inverted global input / output line # GI / O. Connect to O and global I / O line GI / O.

In this case, the sub input / output line subI / O and the inverted sub input / output line # subI / O and the global input / output line GI / O and the inverted global input / output line # GI / O are mutually transferred. The data will be at the same level. That is, the sub input / output line subI / O is at H level (inverted sub input / output line #subI
If / O is L level), the global I / O line GI / O also becomes H level (the inverted global I / O line # GI / O is also L level).

4) The internal power supply voltage Vint is changed to the external power supply voltage Vint.
Replace with CC. 5) Auxiliary read amplifier 11 or auxiliary write amplifier 12
Are carried out independently. Further, the connection method of the auxiliary read amplifier 11 or the auxiliary write amplifier 12 of each of the above-described embodiments is carried out in a combination different from the above.

[0109]

As described in detail above, according to the first to fifth aspects of the present invention, it is possible to completely perform data drive type data transfer in the read operation, and it is necessary to select the read auxiliary amplifier which is conventionally required. No lines are needed. Therefore,
According to the present invention, it is possible to provide a semiconductor memory device having an extremely simple structure, which is capable of realizing area saving and speeding up, and which does not cause data destruction during a read operation.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a main part of a DRAM according to a first embodiment.

FIG. 2 is a time chart during a read operation in the activated memory cell array 50 in the first, second, and sixth embodiments.

FIG. 3 is a time chart during a read operation in another inactive memory cell array 50 in the first embodiment.

FIG. 4 is a time chart during a write operation in the activated memory cell array 50 in the first, second, and sixth embodiments.

FIG. 5 is a time chart during a write operation in another inactive memory cell array 50 in the first embodiment.

FIG. 6 is a plan view showing an actual arrangement of a DRAM of each embodiment on a semiconductor chip.

FIG. 7 is a circuit diagram of a main part of a DRAM according to a second embodiment.

FIG. 8 is a time chart during a read operation in another inactive memory cell array 50 in the second to sixth embodiments.

FIG. 9 is a time chart during a write operation in another inactive memory cell array 50 in the second, third and sixth embodiments.

FIG. 10 is a circuit diagram of essential parts of a DRAM of a third embodiment.

FIG. 11 is a time chart during a read operation in the activated memory cell array 50 in the third, fourth and fifth embodiments.

FIG. 12 is a time chart during a write operation in the activated memory cell array 50 in the third embodiment.

FIG. 13 is a circuit diagram of a main part of a DRAM of a fourth embodiment.

FIG. 14 is a time chart during a write operation in the activated memory cell array 50 in the fourth and fifth embodiments.

FIG. 15 is a time chart during a write operation in another inactive memory cell array 50 in the fourth, fifth and fifteenth embodiments.

FIG. 16 is a circuit diagram of an essential part of a DRAM of a fifth embodiment.

FIG. 17 is a main-portion circuit diagram of the DRAM of the sixth embodiment.

FIG. 18 is a block circuit diagram showing a configuration of a conventional DRAM.

FIG. 19 is a block circuit diagram showing a configuration of a conventional DRAM.

20 is a circuit diagram showing a sense amplifier 51a of the DRAM shown in FIGS. 18 and 19. FIG.

FIG. 21 is a circuit diagram showing a sense amplifier and its peripheral circuit in a conventional DRAM.

FIG. 22 is a circuit diagram of a main part of a conventional DRAM.

FIG. 23 is a circuit diagram of a main part of a conventional DRAM.

FIG. 24 is a plan view of a semiconductor chip for explaining a word line backing portion.

25 is a time chart during a read operation of the DRAM shown in FIG.

FIG. 26 is a circuit diagram of a main part of another conventional DRAM.

[Explanation of symbols]

11 ... Auxiliary read amplifier 12 ... Auxiliary write amplifier 50 ... Memory cell array 51a ... Sense amplifier 61 ... Auxiliary amplifier 62 ... Main amplifier YS, GYS ... Column address selection selection line subI / O ... Sub input / output line # subI / O ... Inversion sub I / O line GI / O ... Global I / O line # GI / O ... Inverted global I / O line P1, P2 ... P-channel MOS transistor as IGFET N1, N2 ... N-channel MOS transistor as IGFET

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kuniyuki Tani, 2-5-5 Keihan Hondori, Moriguchi City, Osaka Prefecture Sanyo Electric Co., Ltd. (72) Inventor, Hiroshi Takano 2-5 Keihan Hondori, Moriguchi City, Osaka Prefecture No. 5 Sanyo Electric Co., Ltd.

Claims (5)

[Claims] 1. A plurality of memory cell arrays, a column address selection line shared by each memory cell array, a plurality of sense amplifiers provided in each memory cell array, and a pair of sub-inputs for each sense amplifier. An auxiliary read amplifier connected by an output line, a pair of global input / output lines shared by the auxiliary read amplifiers, and a main read amplifier connected to the global input / output line are provided. In the semiconductor memory device in which the read data is amplified by the auxiliary read amplifier and the amplified data is transferred to the main read amplifier via the global input / output line, the auxiliary read amplifier is A semiconductor memory device characterized by being driven and controlled only based on data given from an output line 2. The semiconductor memory device according to claim 1, wherein the auxiliary read amplifier has a drain connected to each of the pair of global input / output lines and a gate connected to each of the pair of sub input / output lines. A pair of I
A semiconductor memory device comprising a GFET, wherein a source voltage of the pair of IGFETs is made equal to a precharge voltage of the pair of sub input / output lines. 3. The semiconductor memory device according to claim 2, wherein the source voltage of the IGFET of the auxiliary read amplifier in the activated memory cell array is set to the bit line connected to the sense amplifier in the inactivated memory cell array. A semiconductor memory device characterized in that it is made equal to a precharge voltage. 4. The semiconductor memory device according to claim 2, wherein a precharge voltage of an activated sub input / output line in the memory cell array is different from a precharge voltage of an inactivated sub input / output line in the memory cell array. Set to the value,
A semiconductor memory device characterized in that only a source voltage of an IGFET of the auxiliary read amplifier in the activated memory cell array is changed so as to follow a precharge voltage of the sub input / output line to which the IGFET is connected. . 5. The semiconductor memory device according to claim 2, wherein a precharge voltage of an active sub input / output line in the memory cell array is different from a precharge voltage of an inactive sub input / output line in the memory cell array. And the source voltage of the IGFETs of all the auxiliary read amplifiers is set to a voltage value equal to the precharge voltage of the sub input / output line in the activated memory cell array, and the auxiliary voltage in the activated memory cell array is set. A semiconductor memory device characterized in that only a read amplifier is activated.