JPH08115947A - Bonding structure for semiconductor device - Google Patents

Abstract

PURPOSE: To reduce thermal resistance at the time of flip-chip connection. CONSTITUTION: A semiconductor element 11 is bonded through solder bumps 13 with a circuit board 15. An insulating film, i.e., an oxide film 14, is formed around the bump 13 at the time of bonding the semiconductor element to the circuit board or thereafter. The periphery of the solder bump 13 is filled with a low melting point metal 17 for lowering the thermal resistance and the heat dissipation performance is enhanced between the semiconductor element 11 and the circuit board 15. Since the gap between the semiconductor element 11 and the circuit board 15 is filled compactly with a material having high thermal conductivity, thermal resistance is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a bonding structure suitable for reducing the thermal resistance of flip chip connection.

[0002]

2. Description of the Related Art A conventional device is provided with a solder bump and a low melting point brazing material for electrically connecting a semiconductor element and a circuit board as described in JP-A-6-45401. The low melting point brazing material was electrically held at the ground potential or the power supply potential. This has the effect of reducing crosstalk noise and the like. The solder bumps and low melting point brazing material were used to reduce the thermal resistance. However, it is necessary to provide a space for insulating the solder bump and the low melting point brazing material.

[0003]

As described above, the above-mentioned conventional technique has a high thermal resistance because of the voids. Therefore, there is a problem that the temperature of the semiconductor element exceeds the normal operating temperature range during the operation of the semiconductor element.

An object of the present invention is to reduce the thermal resistance between a semiconductor device and a circuit board so that the device operates within a normal operating temperature range during operation.

[0005]

The above object can be achieved by forming an insulating film on the surface of a bump and filling a gap between a semiconductor element and a circuit board with a conductive material without any gap.

As a method of forming the conductive material, it is considered that the conductive material is filled with anisotropic conductive material, low melting point solder is formed by the dip method, or metallization is performed by the plating method. For forming the insulating film, a method of forming a thick oxide film on the surface of the solder bump by leaving it in an oxidizing furnace at a high temperature, or a method of forming CV on the surface of the gold bump is used.
There is a method of forming a SiO ₂ film or a Si ₃ O ₄ film using a D device.

[0007]

Since the insulating film formed around the bumps electrically insulates the bumps from the filling material, the filling material can be filled into the voids around the bumps without any gap. As a result, the thermal resistance between the semiconductor element and the circuit board is improved, and the temperature rise of the semiconductor element can be reduced. Further, by holding the filling material at the ground potential, it is possible to reduce crosstalk noise that has occurred between the signal lines. Furthermore, by matching the thermal expansion coefficients of the bumps of the connection portion and the filler, stress concentration is less likely to occur at the connection portion, and the connection reliability is increased. Similarly, since the connecting portion is hermetically sealed, only a simple sealing structure is required and it can be manufactured at low cost.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is an overall view of the first embodiment of the present invention. FIG. 2 is an enlarged view of a main part of FIG. Semiconductor device 10
Reference numeral 1 denotes a semiconductor element 11, a circuit board 15 on which the semiconductor element 11 is mounted, electrode pads 12 facing each other between the semiconductor element 11 and the circuit board 15, solder bumps 13 formed between the electrode pads 12, and the semiconductor element 11 And the metallization 16 arranged so as to surround the opposing electrode pad 12 of the circuit board 15, and the low melting point metal 17 filled between the metallization 16.
And an insulating film 14 for electrically insulating the low melting point metal 17 and the solder bump 13.

The low melting point metal 17 is held in the gap by being fixed to the metallization 16. Since the insulating film 14 formed around the solder bumps 13 electrically insulates the bumps 13 and the filling material 17, the filling material 17 can be filled in the voids around the solder bumps 13 without any gap. As a result, the thermal resistance between the semiconductor element 11 and the circuit board 15 is improved,
The temperature rise of the semiconductor element 11 can be reduced.

Further, since the filling material 17 is made of a conductive material, it can be held at the ground potential, and has an effect of reducing crosstalk noise generated between signal lines such as the bumps 13. The effect can also be obtained by holding the conductive material at the power supply potential. Bump 1
3, the insulating film 14 and the low melting point metal 17 have substantially the same thermal expansion coefficient at the connection portion, and therefore no stress is applied to the respective portions. As a result, in terms of connection reliability, the solder cracks that have conventionally occurred do not occur, so that the connection reliability is increased. Further, since the filler seals the connection portion, the semiconductor device 101 can maintain the connection reliability for a long period of time with simple sealing.

Next, a manufacturing process of the semiconductor device 101 will be described. First, the solder bumps 13 are formed on the electrode pads 12 of both the semiconductor element 11 and the circuit board 15. In order to facilitate the formation of the solder bumps 13, the electrode pads 12 have gold formed on the surface thereof, and nickel for barriering the solder is formed under the gold, and the underlying circuit board 15 and the semiconductor element 11 are formed under the gold. Titanium is formed to enhance the adherence with the.

Next, the semiconductor element 11 and the electrode pads 12 on the circuit board 15 facing each other are aligned with each other. afterwards,
The semiconductor element 11 and the circuit board 15 are accurately aligned and connected by self-alignment of the solder bumps 13 formed by melting the solder bumps 13 formed on the electrode pads 12 using flux. After connection, the flux is washed and removed with an organic solvent so that there is no residue.

After cleaning the flux, the solder bumps 13 connecting the semiconductor element 11 and the circuit board 15 are formed with an oxide film 14 at an appropriate thickness on the periphery thereof using an electric furnace in an oxygen atmosphere. The oxide film 14 was formed in a thickness of about 0.1 μm by leaving it in an oxygen atmosphere at 400 ° C. for 2 hours.

After forming the oxide film 14, the solder bumps 13 are formed.
Pour into a solder bath in which low melting point solder lower than
Metallization 1 in which semiconductor element 11 and circuit board 15 face each other
A low melting point metal 17 is formed between 6 and 6. Gold is formed on the surface of the metallization 16 so that the solder, which is the low melting point metal 17, can be easily wetted, and nickel is used as a barrier metal in the intermediate layer, and titanium is used to make a good connection with the base. is there.

The semiconductor device 101 thus formed
Has a large heat conduction path between the semiconductor element 11 and the circuit board 15, and the heat resistance is reduced by using a material having high heat conductivity. Further, by holding the low melting point metal 17 at the ground potential, the crosstalk noise generated from the signal line can be reduced. As described above, the low-melting-point solder is used as the low-melting-point metal 17, but the same effect can be obtained by filling the anisotropic conductive material or depositing and depositing the metal by plating.

FIG. 3 is a sectional view taken along line AA of FIG. A counter electrode 12 (not shown) is provided on the circuit board 15, and solder bumps 13 are connected to the counter electrode 12. The semiconductor element 11 (not shown) is connected to the upper surface of the solder bump 13. The periphery of the solder bump 13 is insulated from the periphery by an oxide film 14 which is an insulating layer. The periphery of the oxide film 14 is filled with a low melting point metal 17 without any gap. The filled low melting point metal 17 has an effect of reducing the thermal resistance between the semiconductor element 11 (not shown) and the circuit board 15. Further, by holding the outer low melting point metal 17 at the ground potential, the solder bump 13 This has the effect of reducing crosstalk noise generated from signal lines such as.

Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 4 is an overall view of the second embodiment of the present invention. FIG. 5 is an enlarged view of the main part of FIG. The semiconductor device 102 includes a semiconductor element 11, a circuit board 15 on which the semiconductor element 11 is mounted, electrode pads 12 facing the semiconductor element 11 and the circuit board 15, gold bumps 18 formed between the electrode pads 12, and a gold bump 18. An insulating film 20 that insulates the bumps 18 from the surroundings, a metallization layer 19 formed on the insulating film 20, and a low melting point metal 17 formed on the metallization layer 19.
It consists of

Insulating film 20 formed around gold bumps 18
Is formed by a CVD apparatus, so that not only the gold bumps 18 but also the surfaces of the semiconductor elements 11 and the circuit board 15 are similarly deposited. A metallization layer 19 is formed on the surface of the insulating film 20. This is to facilitate the formation of the filling material 17 between the semiconductor element 11 and the circuit board 15.

The semiconductor device 20 formed in this way
No. 1 has a reduced thermal resistance between the semiconductor element 11 and the circuit board 15, and has a higher speed and a larger heat generation amount.
Can be used. Further, as in the first embodiment, holding the filler 20 at the ground potential has an effect of reducing crosstalk noise generated from the signal line.
Further, mechanically, the problem of stress concentration that has conventionally occurred at the connecting portion was relieved by the fact that the bumps were held by the filler. Further, since the filler seals the connection portion, the semiconductor device can maintain the connection reliability for a long period of time with simple sealing.

Next, a process of forming the semiconductor device 102 of the second embodiment will be described. Gold bumps 18 are formed by gold plating on the electrode pads 12 on the semiconductor element 11 or the circuit board 15. After forming the gold bumps 18, the electrode pads 12 are aligned with each other and gold bonding is performed. Alternatively, the electrode pads 12 on the semiconductor element 11 and the electrode pads 12 on the circuit board 15 are aligned in advance,
Selective gold plating is performed to form gold bumps 18. The gold bumps 18 are gradually formed in the vertical direction and are automatically joined at the intermediate portion.

In order to form the insulating film 20 around the gold bumps 18 joining the semiconductor element 11 and the circuit board 15 which have been connected in this way, they are put into a CVD apparatus,
An oxide film SiO ₂ is formed at 450 ° C. The oxide film formed by the CVD device is also deposited on the back surfaces of the semiconductor element 11 and the circuit board 15. The oxide film in the excess portion is masked and then deposited by a CVD apparatus, or the oxide film in the unnecessary portion is removed by etching the oxide film.

Next, a metallization 19 is formed on the oxide film SiO ₂ by using electroless plating. The unnecessary portion is removed by using the mask used for forming the oxide film after forming the plating film. Next, the semiconductor device 201 was put into a solder bath in which the low melting point solder was melted, and the gap between the semiconductor element 11 and the circuit board 15 was filled with the low melting point solder. In the above-described process, the bump 18 is made of gold, but a metal having a high melting point that facilitates connection can be used to form the bump 18. Although solder is used to form the low melting point metal 17, the same effect can be obtained by filling the anisotropic conductive material or depositing the metal by plating. Further, although the oxide film SiO ₂ is used as the insulating film, the same effect can be obtained with respect to the thermal resistance and the crosstalk noise by forming the nitride film Si ₃ N ₄ which also has an insulating property.

FIG. 6 shows the result of comparison of the thermal resistances of the semiconductor devices manufactured as described above. In FIG. 6, the horizontal axis represents the ratio of the chip area A0 to the total connection area A1, and the vertical axis represents the thermal resistance ratio. When the thermal resistance of the semiconductor device shown in the example was set to 1, the ratio of the connection areas of the semiconductor elements was 95%. In the conventional connection method, the connection area ratio was 12%, and the thermal resistance was 8 times that of this example. For this reason, the connection method of the present embodiment makes it possible to use a semiconductor element having a heat generation amount eight times that of the conventional semiconductor element.

[0024]

By increasing the connection area, the thermal resistance can be reduced to 1/8 of that of the conventional one.

By setting the low melting point metal portion to the ground potential, the crosstalk noise that has been conventionally generated can be reduced.

By using a material having a thermal expansion coefficient close to that of the filler, stress concentration is less likely to occur and the connection reliability is increased.

Since the connecting portion of the semiconductor device containing the filler is hermetically sealed, the reliability is maintained for a long time with a simple sealing structure.

[Brief description of drawings]

FIG. 1 is a sectional view of a first embodiment of the present invention.

FIG. 2 is an enlarged view of a main part of FIG. 1 which is a first embodiment.

FIG. 3 is a sectional view taken along line AA in FIG. 1 of the first embodiment of the present invention.

FIG. 4 is a sectional view of a second embodiment of the present invention.

FIG. 5 is an enlarged view of a main part of FIG. 4 which is a second embodiment.

FIG. 6 is a graph showing the relationship between the connection area ratio and the thermal resistance ratio.

[Explanation of symbols]

11 ... Semiconductor element, 12 ... Electrode pad, 13 ... Solder bump, 14 ... Oxide film, 15 ... Circuit board, 16 ... Metallization, 17 ... Low melting point metal.

Claims (8)

[Claims] 1. A semiconductor element, a circuit board on which the semiconductor element is mounted, bumps formed between opposing electrode terminals of the board and the semiconductor element, and a filling material for filling a void portion around the bump. In the semiconductor device including, the filling material is made of a conductive material, an insulating film is formed on the surface of the bump, and the bump and the filling material are electrically insulated by the insulating film. Semiconductor device. 2. A semiconductor device in which the filling material according to claim 1 is made of a metal material. 3. A semiconductor device in which the filling material according to claim 2 is formed by electroless plating or electrolytic plating. 4. A semiconductor device formed by immersing the filling material according to claim 2 in a solder bath. 5. A semiconductor device according to claim 1, 2, 3, or 4, wherein the insulating film is an oxide film formed by being kept in an oxygen atmosphere. 6. A semiconductor device in which the bump according to claim 5 is formed of solder. 7. A semiconductor device according to claim 1, 2, 3 or 4, wherein the insulating film is formed by a CVD device. 8. A semiconductor device in which the bump according to claim 7 is formed of gold.