JPH08102745A - Exchange, exchange method and network system - Google Patents

Abstract

PURPOSE: To select one line among the plural lines capable of performing transmission to a discriminated transmission destination based on the data characteristics of a hierarchy higher than a specified hierarchy by discriminating the transmission destination of a data frame based on the transmission destination identification information of the specified hierarchy among the plural hierarchies. CONSTITUTION: By the information for respective transmission functions of virtual discrimination VPI and virtual channel discrimination VRI of a user network interface UNI in the data frame of an ATM cell, communication to which the cell belongs is discriminated and user information is discriminated by a payload PT. An information field AAL is constituted of a header, the payload and a trailer and the destination of the cell is specified by the transmission destination address DA of the payload. Also, by the data DEST in the header of a TCP layer higher than an AAL layer, the level of security required for the data frame is judged. In the case of detecting the DEST of the TCP included in the received ATM cell in an address processor 102, a CPU 121 selects the output line of the appropriate security from the features of the respective lines stored in a RAM 123 and sets it in an SEU 111.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention receives a data frame assembled based on a communication protocol composed of a plurality of layers, and based on a destination address of a specific layer in the data frame, the data frame is received. The present invention relates to an exchange, an exchange method, and a network system for identifying a destination of a message.

[0002]

2. Description of the Related Art An exchange selects a line based on destination identification information. Here, the "destination identification information" includes, for example, the VPI and VC of the ATM header in the ATM network.
I, Ethernet type or DA (destination address) in data frame of IEEE802.3, TCP / IP
DEST (destination address) included in the IP header of
This corresponds to the ISDN number of the other party on the SDN line. A network system in which multiple routes are connected to the same destination has also been put into practical use. In such a network system, when some lines are congested, the line not congested is selected.

The conventional multi-path lines that can be selected by the exchange are guaranteed to have sufficient security, communication speed, bandwidth (transmission capacity), and quality. Further, the fee charged to the user is constant regardless of which line is selected. In this application,
Such high security, communication speed, bandwidth (transmission capacity), quality, charges, etc. are called "features" of the line.

[0004]

In recent years, internetworking for connecting a plurality of networks to each other has been promoted. A data frame may be transmitted from a specific source to a specific destination via networks of many vendors. In the future, even when a data frame is transmitted from a specific transmission source to a specific transmission destination, it depends on which line of which vendor is used to transmit the data, that is, by the transmission route. It is considered that there may be cases where the security level, delay, charges, etc. of the communication differ. In this case, if the exchange arbitrarily selects the route of the line, high security of communication, delay, charge, etc. cannot be guaranteed.

On the other hand, in a data frame transmitted to a network such as an ATM network in which moving images, voices, data transmission, etc. are made one-dimensional, there are data frames that do not require high reliability like moving images, Data frames that require high reliability such as data transmission are mixed.
In addition, there are mixed data frames such as call data that are severe in data delay and data frames that are not severe in data delay such as data transmission. In this case, if high security and a short delay time are guaranteed for all data frames, it is not possible to fully utilize a plurality of line paths. In addition, it may be uneconomical to select an expensive communication path more than necessary.

At the time of call setup, a call setup sequence that requires a required communication quality is also used. However, in the future, it is considered that lines with extremely diverse "features" will be connected to each other, so it will be difficult to select an appropriate communication line only by such a sequence that requires quality. .

Further, since it is necessary to select a line to which a received frame is to be sent at a high speed, it has been conventionally difficult to select an appropriate line each time a data frame is received.

[0008]

In order to achieve such an object, the invention according to claim 1 receives a data frame assembled based on a communication protocol composed of a plurality of layers, and In the exchange that identifies the transmission destination of the data frame based on the transmission destination identification information in the specific layer among the plurality of layers described in the data frame, there are a plurality of lines that can be transmitted to the transmission destination. The plurality of lines are connected based on the data of the hierarchy higher than the specific hierarchy included in the data frame and representing the characteristic of the data content of the hierarchy higher than the higher hierarchy. 1 in
It is characterized in that a selection means for selecting one line is provided.

The invention according to claim 2 is the exchange according to claim 1, further comprising means for storing data representing characteristics of each of the plurality of lines, and the selecting means further includes the characteristics. One line is selected from the plurality of lines based on the data representing

The invention according to claim 3 is the exchange according to claim 1 or 2, wherein the data frame is an AT.
M cells, the specific layer is an ATM layer, the destination identification information is VPI and VCI, the layer higher than the specific layer is a TCP layer, and the data of the upper layer is a TCP header. It is characterized by being a medium DEST.

The invention according to claim 4 is the exchange according to claim 3, wherein the data frame is an ATM cell of AAL type 3/4 and a VPI of a reception ATM cell,
First search means for searching a destination line associated with VCI and MID, and if the destination line is not searched by the first search means, and the received ATM cell is a BOM cell Second search means for searching a destination line associated with the DA in the BOM cell,
When there are a plurality of destination lines searched by the second searching unit, a selecting unit that selects one destination line based on the DEST and the destination line selected by the selecting unit ATM cell VPI, VC
The receiving ATM is stored in the storing means for storing in the first searching means in association with I and MID, and in the destination line searched by the first searching means or the destination line selected by the selecting means. And a means for transferring cells.

The invention as defined in claim 5 is defined by claim 1 through claim 4.
The exchange according to any one of claims 1 to 3, wherein the data representing the characteristics is data based on the security level of each of the plurality of lines.

The invention as defined in claim 6 is from claim 1 to claim 5.
The exchange according to any one of the items,
Means for storing position information indicating the position of the destination identification information in the data frame in advance, and means for selecting the identification information from the data string based on the position information,
Means for searching the destination of the data string using the selected identification information, and storing start position information indicating in advance what number of data in the data frame has been input. And a means for outputting a search start means for starting a search by the search means when the data indicated by the start position information is input, and a means for outputting information indicating the searched destination. It is characterized by having.

According to a seventh aspect of the present invention, in a switching system for switching ATM cells, a first search for searching for a destination line associated with a VPI and a VCI of a received ATM cell is performed. Means, the destination line does not exist, and the received ATM cell is AAL
In the case of a type 3/4 BOM or SSN, a second searching unit that searches for a destination line associated with the DA in the BOM or SSN, and the destination searched by the second searching unit. Storage means for storing a line in the first search means in association with the VPI and VCI of the received ATM cell; and the first search means or the second search means.
Means for transferring the received ATM cell to the destination line searched by the searching means.

According to the invention described in claim 8, a data frame assembled based on a communication protocol composed of a plurality of layers is received, and a specific one of the plurality of layers described in the data frame is received. In the exchange method for identifying the destination of the data frame based on the destination identification information in the layer, when there are a plurality of lines that can be transmitted to the destination, the specific layer included in the data frame Data of the upper hierarchy,
It is characterized in that one of the plurality of lines is selected based on the data representing the characteristics of the data contents of the upper layer.

The invention according to claim 9 is the exchange method according to claim 8, further comprising means for storing data representing characteristics of each of the plurality of lines, and the selecting means:
Further, the exchange is characterized in that one line is selected from the plurality of lines based on data representing the feature.

The invention according to claim 10 is the switching method according to claim 8 or 9, wherein the data frame is an ATM cell, and the specific layer is an ATM layer,
The transmission destination identification information is VPI and VCI, a layer higher than the specific layer is a TCP layer, and data of the higher layer is DEST in a TCP header.

According to the eleventh aspect of the present invention, a data frame assembled based on a communication protocol composed of a plurality of layers is received, and a specific one of the plurality of layers described in the data frame is received. In a network system including a switch that identifies a destination of the data frame based on destination identification information in a hierarchy,
A plurality of lines capable of transmitting to the destination are connected to at least one of the exchanges, and the exchange is data of a layer higher than the specific layer included in the data frame, It is characterized in that it has a selecting means for selecting one of the plurality of lines on the basis of data representing the characteristics of the data contents of a higher layer than the upper layer.

The invention according to claim 12 is the network system according to claim 11, wherein the at least one exchange further has means for storing data representing characteristics of each of the plurality of lines. The selecting means further selects one of the plurality of lines based on the data representing the feature.

The invention according to claim 13 is the network system according to claim 11 or 12, wherein the data frame is an ATM cell, the specific layer is an ATM layer, and the destination identification information. Is VPI and V
CI, a layer higher than the specific layer is a TCP layer, and data of the higher layer is D in a TCP header.
It is characterized by being EST.

[0021]

According to the present invention, the exchange receives a data frame assembled on the basis of a communication protocol composed of a plurality of layers, and describes the data frame.
The destination of the data frame is identified based on the destination identification information in a specific layer of the plurality of layers. When a plurality of lines capable of transmitting to the destination are connected, the data of the layer higher than the specific layer included in the data frame, and the data of the layer higher than the upper layer. One of the plurality of lines is selected based on the data representing the characteristic of the content.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings.

[First Embodiment] (1) Configuration of Network System In FIG. 1, 10 is an ATM network as an example of the network system of the present invention, and 11 to 17 are ATM exchanges as an example of the exchange of the present invention. The network system of the present invention may include exchanges other than the exchange of the present invention. 21 to 23 are terminals for transmitting and receiving ATM cells. Reference numerals 31 and 32 are IWUs (Inter Working Units), which convert connectionless type data received from a LAN using TCP / IP into ATM cells to convert the ATM network 1
0 to the ATM cell received from the ATM network
Convert to CP / IP data frame and send to LAN. Reference numerals 44 to 49 are LAN terminals.

(2) Hardware Configuration of ATM Switch FIG. 2 is a hardware block diagram of the ATM switch 11. The ATM exchanges 12 to 17 also have the same configuration.
In FIG. 2, 301 is a network terminator (N
T), which performs insulation between the ATM line 150 and the device, serial / parallel conversion, and data buffering. The NT 301 has a CPU bus and a data transfer bus. The CPU bus is connected to the CPU 121.

Reference numerals 101 and 102 denote address processors (AP) as an example of a search device for an exchange.
The input data is searched, and the search result is output according to a preset sequence. In this embodiment, NT
Address processor (AP) for transferring cell data from 301 to switching element unit 111
101 and 102 are used. Switching element 11
The data output from 1 is directly transferred to the NT 301 by the DMAC 103 without passing through the APs 101 and 102. The data buses and write signals of the input ports of AP 101 and 102 are connected to each other, and NT to A
Data can be transferred to P101 and P102 simultaneously.

Reference numeral 103 denotes a direct memory access controller (DMAC), which is NT301, AP10.
Data is transferred between the first and second switching elements unit (SEU) 111. DMAC
103 has a CPU bus and a data transfer bus, and the CPU bus is connected to the CPU 121. The data transfer bus is a data transfer bus of NT301, AP101, 102.
Input and output ports, and SEU111
Connected to the port.

Reference numeral 111 denotes a switching element unit (SEU), which has a plurality of data ports (simply called ports) and one control port. SEU11
1 connects the ports according to the data input from the control port. 121 is a CPU that controls the entire ATM switching device, 122 is a ROM that stores programs executed by the CPU 121, and 123 is a RAM. A timer (TIMER) 124 interrupts the CPU 121 at every set time. 12
Reference numeral 5 is an input device for inputting various settings and the like to the ATM switching device, and is typically composed of a keyboard and a mouse. Reference numeral 126 is a display device that displays the operating state of the device. 150 is an ATM line.
160 is AT by the network terminator 301
An ATM data bus isolated from the M line 150.
170 is a CPU bus.

(3) Configuration of Address Processor (AP) The hardware configuration of the AP 102 will be described with reference to FIG. Like many programs, this device can be easily produced and used by those skilled in the art by clarifying specifications. Therefore, the specifications of the port configuration, CAM array configuration, register configuration, etc. of this device will be described in detail below. AP101 is also AP
It has the same configuration as 102.

(3-1) Port Configuration As shown in FIG. 3, the AP 102 has an input port (INPUT PO
It has an RT) 210, an output port (OUTPUT PORT) 220, and a CPU port 230.

(3-1-1) Input Port The input port 210 is a port for inputting search key data. The port width is 32 bits but can be set so that only 16 or 8 bits are valid. The data (ID: 0 to 31) needs to be input in synchronization with the WR pulse. The extreme positive of WR can be set to positive logic or negative logic.

In FIG. 3, the IPB of the input port 210
The USY terminal is a terminal that outputs a signal indicating whether data can be input to the input port, and outputs LOW when another port (output port or CPU port) is operating and does not accept data input to the input port. To be done.

The input data input to the input port 210 is combined (compounded) by the data formatter 211 in accordance with a pre-defined input port sequence to become 32-bit data (comparand data). Processing such as search is performed according to the comparand data.

(3-1-2) Output Port The output port (OUTPUT PORT) 220 is a port for outputting data such as search results. The data width is 32 bits, but it can also be set so that only 16 or 8 bits are valid. Output data (OD) is output by inputting a LOW pulse (RD pulse) to the RD terminal of the output port 220 while LOW is input to the OE terminal of the output port 220.

The OPBUSY terminal of the output port 220 is
It is a terminal that outputs a signal that indicates whether or not data can be output from the output port, and the other port (input port or CPU
Port) is operating and data cannot be output from the output port, LOW is output.

(3-1-3) CPU Port The CPU port is a 16-bit input / output data bus for interfacing with the host processor. Data width is 1
It has 6 bits and an address width of 8 bits. The address is
It is used to specify the addresses of various registers in the AP. The following operations can be performed from the CPU port.

(3-1-3-1) Reading / Writing Registers Data can be written in and read from various registers in the chip.

(3-1-3-2) CAM table writing / reading CAM table writing / reading is performed by Memory_A
This is done via access to the R, Memory_HHA, and Memory_HEA registers.

(3-1-3-3) Execution of various commands Commands are executed by writing execution commands in the command register. For example, when a search execution instruction is written, the AP 102 does not require CPU intervention,
Input data from the input port and output the result from the output port according to the defined sequence. The definition of the search condition performed before writing the search execution instruction is also the CPU bus 2
Start from 30.

(3-1-3-4) Search It is also possible to search through the CPU port. The command is executed by writing an operation code in the IP command register.

(3-2) Configuration of CAM Array The CAM array 250 has 2048 CAM basic words shown in FIG. In FIG. 4, empty bit 2
51 indicates whether or not valid table data is written in the word. Set to 0 when valid data is being written. The hit / miss hit flag 255 indicates whether or not the search result is a hit.
The access bit 256 indicates whether or not there is a hit or a miss hit in the past search.

The logical configuration of the CAM array 250 will be described with reference to FIG. As shown in FIG. 5, the CAM array 25
0 has a logical configuration of row (horizontal row in FIG. 5) × column (vertical column in FIG. 5). The row and column sizes are shown in Figure 5.
Is defined by the segment number bit 253 and the boundary bit 252 of the. These bits are AP10
2 is pre-written before starting execution.

The segment bits shown in FIG. 4 are 3 bits, and the value of 000 to 111 indicates the segment number. The segment number represents the position in the column direction. If the segment bit value is from 000 words to 111 words, the table column size is 8, and if the segment bit 253 value is only 000 words, the table column size is 1. . Thus, the column size of the table is defined by the value written in the segment bit.

A word with a segment bit of 000 indicates that a new row in the CAM table begins.
1 is written in the boundary bit (see FIG. 4) of this word. The column size n and the row size m of the CAM table must satisfy n × m ≦ 2048. The remaining words defined by 2048-nxm cannot be used. Search is
Do this for each column of the table. One segment 254 in the same column is used by using one comparand data.
Refer to times.

When the definition of the table is completed, the segment 254 of each basic word is transferred to the segment 254 through the CPU port 230.
You can write data. The CPU port 2 determines whether the data written in each segment is used as search data (key data) and whether it is used as target data to be output when the search hits.
It is defined by the CPU 121 via 30. The data written in each segment can be used as both key data and target data. Also, a different number of segments for each column can be used as search data or target data. C after power on
Since the values in the AM table are indefinite, the CAM table is set by writing the boundary bits in all the segments (2048 segments) of the CAM.

(3-3) Register Configuration AP 102 is a control register, CUT register, SEARCH register, HHA register, 16 comparand registers, 16 CS registers, 16 mask registers, 32 AOC registers. , 32 AOSC registers and address registers.
The CS register and the mask register are divided into 8 channels each for A channel and B channel. The AOC register and the AOSC register are divided into 16 A channels and 16 B channels.

The data width of the input data is set by the control register. Input data used for search is set by the CUT register. The SEARCH register sets the condition for executing the search. The HHA register has
The address of the hit CAM data is stored. 16
Up to 16 comparand data are stored in each comparand register. Arbitrary comparand data stored in the comparand register can be stored in any word in the CAM array by an append instruction from the CPU port. 16 CS registers,
Set the number of bytes to shift comparand data when performing each search. The masked bits of each comparand data are set in the 16 mask registers.

A sequence of output data is set by 16 AOC registers of each channel. That is, the output data set in the 1st to 16th AOC registers are sequentially output from the output port. When it is defined that the CAM table data is output by the AOC register, the segment number of the CAM table to be output is set by the AOSC register corresponding to the AOC register. The address register sets the address of the CAM accessed from the CPU port. The setting contents of these registers are described in detail in “(3-4) Input sequence setting method” and “(3-5) Output sequence setting method”.

(3-4) Input Sequence Setting Method Two types (A channel and B channel) of data input sequences (capture of data on input port, masking of comparand data, etc.) should be set in the AP 102. Can be done.

The maximum input sequence for each channel is 64.
It can be set for each input data. Up to 6
Which of the four pieces of input data is taken into the AP is set by the 64-bit CUT register. That is, each bit of the CUT register is made to correspond to each input data, 1 is set to the bit corresponding to the fetched data, and 0 is set to the bit corresponding to the non-fetched input data.

The 16-bit and 8-bit input data are combined (compounded) in the AP and treated as a maximum of 16 32-bit wide data (called comparand data). 32-bit input data is 32 as is
Handled as bit-width comparand data. The comparand data is stored in 16 comparand registers.

The maximum amount of data that can be used for a search by the input sequence of one channel among the data taken in the comparand register is the maximum column size of the CAM table, that is, eight. Therefore, when the effective input data width is 32 bits, 16 bits, and 8 bits, 8, 16, and 32 pieces of input data can be used for the search, respectively.

The input data set by the CUT register when it is taken into the AP is sequentially A-synchronized with the WR pulse.
It is stored in the accumulation buffer of P102.
64-bit SEAR which input data should be searched when stored in the accumulation buffer
Set in CH register. That is, each bit of the SEARCH register corresponds to each of 64 input data, and the bit of the SEARCH register corresponding to the input data to be searched is set to 1. The search can be executed even when the 4-byte data is not stored in the comparand register. In this case, the value of the comparand data of the field in which no data is input is set to 0.

When executing the search, 1 to 3 bytes of the input data stored in the previous comparand register can be shifted to the comparand register to be searched. The number of bytes to be shifted when performing each search is set in the 2-bit shift amount field in the CS register. Further, the 3-bit segment designation field in the CS register is used to set the number of the segment in the CAM array to search for the input data. Eight CS registers are provided for each channel, and the shift amount and the segment to be searched can be set for each of the eight searches.
When the shift is not performed, the shift amount field is set to 0 as the default.

When a part of the comparand data is masked when executing the search, the bit corresponding to the bit to be masked in the mask register corresponding to the search is set to 0. Set 1 to the bits that are not masked. In the AP, the value of the masked bit is masked to 0 by calculating the logical product (AND) of the mask register value and the comparand data when executing the search.

The input sequence advances one by one by inputting a WR pulse. Also, LOW for the SQRST pin
The input sequence returns to the beginning by inputting a pulse or an SQRST command from the CPU port.

(3-5) Output Sequence Setting Method When the search is executed, the register address of the hit data in the CAM table (CAM table data that matches the input data) is stored in the HHA register. When a plurality of segments are searched by the AND condition of a plurality of comparand data, the lowest addresses of the plurality of hit segments are stored in the HHA register.

After executing the search, data can be output from the comparand register, the HHA register, and the CAM table to the output port. The output data and the output order are determined by the output sequence. Two output sequences (A channel and B channel)
Can be set. For each channel
The following settings can be made.

Which of the 16 comparand registers, the HHA register, and the data of the hit row in the CAM table is to be output is set to 16 AO.
Set in each of the C registers. By setting the AOC register, the logical OR of the value of the comparand register and the value of the data of the hit row in the CAM table can be output. The data set in the first AOC register to the data set in the 16th AOC register are sequentially output from the output port. By setting the AOC register to output only the data of the comparand register, the data input to the input port 210 can be output from the output port 220 as it is.

The data of each segment of the hit row in the CAM table is irrespective of whether it is used for retrieval or not.
It can be output arbitrarily. The segment number of the output CAM table data is set in 16 AOSC registers associated with each of the 16 AOC registers. The output sequence advances one by one by the input of the RD pulse. Also, LOW for the SQRST pin
The output sequence returns to the beginning by inputting a pulse or an SQRST command from the CPU port.

(3-6) Execution of Search When the SWIOP command is input after the search conditions have been set, the AP (AP) 102 is in the input / output mode (IOP
Mode), and the search is executed according to the input from the input port 210. Which of the A channel and the B channel is used for each of the input sequence and the output sequence is set by a command from the CPU port.

However, the A channel or B channel may be selected based on the first input data from the input port.

(3-7) Search from CPU Port Search data can also be input from the CPU port 210. The input search data is set in the CPU input register. After that, if you enter SRCH command, AP
102 executes a search.

The search result can be output from the CPU port. The address of the hit CAM data is HH
Read from A register. The CAM data of the segment address set in the address register can be read by reading the Memory_AR register.

(4) Structure of Data Frame Using FIG. 6, the AT as an example of “data frame”
The data structure of the M cell will be described. As shown in FIG. 6 (A), an ATM cell has a cell header of 5 octets and 48 octets.
It is composed of octet information fields. UNI (User Net) used between users and networks
work interface) and NN used between networks
The structure of the cell header in I (Network Network Interface) is shown in FIGS. 6 (B) and 6 (C).

In FIGS. 6B and 6C, the VPI
Is a virtual path identification, and VCI is a virtual channel identification. The VPI and VCI identify which communication the cell belongs to. VPI and VCI
Corresponds to the "destination identification information" in the present invention.
The values of VPI and VCI are usually set when an ATM connection is established and held until the ATM connection is released. PT is a payload type and indicates whether the information contained in the information field of the cell is user information or network information.

FIG. 7 shows A in the ATM information field.
The data format of the AL layer is shown. As shown in FIG. 7B, the ATM information field is 2 octets AA.
It consists of an L header, a 44-octet payload, and a 2-octet trailer. As the format of the AAL layer, data formats of types 1 to 5 are defined. Connectionless type data used for LAN etc. is A when it is transmitted to the ATM network.
Converted to AL type 3/4 ATM cells. When one frame of connectionless type data does not fit in a single ATM cell, it is divided into a plurality of ATM cells.
In this case, the first cell is BOM, the last cell is EOM,
A cell sent between the BOM and the EOM is called COM.
An ATM called SSN when a connectionless data frame in a LAN or the like enters a single ATM cell
Include the data frame in the cell. In FIG. 7 (C),
The data format of type 3/4 is shown. In the figure, ST is a segment type (segment division identifier)
And the cell is BOM, COM, EOM, or S
Indicates which of the SNs. MID is a multiplexing identifier, and BOM, COM, or EO on the same communication line
If there are multiple types of M, which BOM and COM are B
Indicates whether the cell is a cell following the OM.

FIG. 8 shows the data formats of BOM, EOM, COM, and SSN. In FIGS. 9B and 9E, DA is a destination address, and the destination of the cell in the ATM network is specified by the DA. DA is included only in BOM and SSN, not in COM and EOM. When a TCP / IP data frame is transferred by ATM, TCP / IP data is stored in the BOM, EOM, COM, and SSN data fields. TCP is a layer above IP, IP is A
The upper layer of the AL layer, AAL is the upper layer of the ATM layer.

FIG. 9 shows the data structure of a TCP data frame. In FIG. 9, the data of the upper layer of the TCP layer is stored in the information field of the TCP layer. DEST
Indicates that the TCP data is based on, for example, FTP, NFS, transaction (application), mail, or telnet. A data frame belonging to a transaction (application) usually requires very high security. Data frames belonging to the telnet usually do not require very high security. Therefore, the DEST of the TCP layer makes it possible to judge the level of security required for the data frame. DEST
Corresponds to data indicating “characteristics” of TCP data in the present invention.

(5) Address process in this embodiment
Initial Setting of Server 102 (5-1) Setting of CAM Array FIG. 10A shows the definition (table structure) of the CAM array 250 of the address processor 102. In this embodiment, the column size is set to 4. This setting is used when the power of the ATM switching device is turned on or when the definition change is input from the input device 125.
1 does.

The VPI and VCI used in the receiving side line to which each AP is connected are stored in the segment 0, and the VPI and VCI used in the transmitting side line are stored in the segment 3. As shown in FIG. 6, since VPI and VCI are not displayed in the lower 4 bits in the upper 4 octets of the ATM header, 0 is displayed in the lower 4 bits of segments 0 and 3.
To store. Also, as shown in FIG.
VPI and VCI are not stored in the upper 4 bits of the M cell header. Therefore, 0 is stored in the upper 4 bits of the segment storing the VPI and VCI of the UNI. The segment 1 stores the MID of the received ATM cell, and the segment 2 stores the cell output port number.

(5-2) Input Sequence Setting The CPU 121 selects the A channel input sequence,
The control register sets the effective data width of the input data to 8 bits, which is the same as the width of the NT output data. In this embodiment, the first octet to the 19th octet of the ATM cell are transferred from the NT 301 to the AP 101, 102. VPI and VCI are transferred to AP A
The TM cell is displayed in the 1st to 4th octets, and the MID is displayed in the 6th and 7th octets of the ATM cell. Therefore, the CPU 121 sets the 0th bit to the 3rd bit, the 5th bit and the 6th bit of the CUT register corresponding to these octets to 1 and sets the other bits to 0. The 4-byte data of the first octet to the fourth octet are combined in the AP 102 to become the first comparand data and stored in the comparand register. The 2-byte data of the sixth octet and the seventh octet is stored in the second comparand register.

Next, the third and sixth bits of the SEARCH register are set to 1 and the other bits are set to 0. Thus, the search is executed when the input data corresponding to the third bit and the sixth bit, that is, the fourth and seventh input data are input. The PT and CLP displayed in the lower 4 bits of the fourth input data are not used for the search. Therefore, the lower 4 bits of the mask register (first mask register) corresponding to the first search are set to 0, and the other bits are set to 1. As a result, the lower 4 bits of data are masked to 0. By setting bits other than the lower 10 bits of the second mask register to 0, data other than the lower 10 bits of the second input data is masked. Since the first comparand data is not shifted, 0 is set in the shift amount field of the first CS register corresponding to the first search. Since the second comparand data is shifted to the right by 2 bytes, 2 is set in the shift amount field of the second CS register corresponding to the second search.

(5-3) Setting of output sequence The output sequence of the A channel is selected, and the effective data width of the output data is set to 8 bits which is the same as the input data width of NT by the control register. Next, the sequence of output data is set by the AOC register. In this embodiment, VPI and V in the output side network
PT and CLP in the input data are combined and output to CI. Therefore, the first AOC register receives the logical O of the CAM data and the value of the first comparand register.
Set the AOC register to output R. Since the VPI and VCI in the output network are stored in the segment 3, the segment 3 is set in the first AOSC register.

When these settings are completed, the CPU 121
Issues a SWIOP command to the address processor 102 to transition the address processor 102 to the input / output mode.

(6) Address process in this embodiment
Initial Setting of Server 101 (6-1) Setting of CAM Array FIG. 10B shows the definition (table configuration) of the CAM array 250 of the address processor 101. Set the column size to 4. This setting is performed by the CPU 121 when the power of the ATM switching device is turned on or when the definition change is input from the input device 125. In addition, 1 bit in ST indicating BOM or SSN in advance is set to segment 0, DA is set to segments 1 and 2, and the DA is set to segment 1.
The port number of the transmission destination corresponding to is stored in the segment 3. If there are multiple destination port numbers corresponding to the DA, the same ST and DA are stored in multiple rows,
The port number is stored in each segment 3 of the plurality of rows.

(6-2) Input Sequence Setting The CPU 121 selects the A channel input sequence,
The control register sets the effective data width of the input data to 8 bits, which is the same as the width of the NT output data. In this embodiment, the first octet to the 19th octet of the ATM cell are transferred from the NT 301 to the AP 101, 102. As shown in FIG. 7, ST is the sixth ATM cell.
The BOM DA is displayed in the 12th to 19th octets of the ATM cell as shown in FIG. In this embodiment, these data are stored in the address processor 101. So CPU121
Sets the 5th bit and 11th to 18th bits of the CUT register to 1 and the other bits to 0.

After the data of the sixth octet is transferred, the data is shifted by 3 bytes in the comparand register, so that 3 is stored in the first CS register. The next 8-byte data input is combined in 4-byte units in the address processor to form the second and third comparand data, which are stored in the second and third comparand registers. The 6th bit, the 14th bit and the 18th bit of the SEARCH register are set to 1 and the other bits are set to 0. As a result, the search is executed when the 7th, 15th, and 19th input data are input. Since only one bit in ST is used in the first search, 0 is set to the bit of the mask register corresponding to the other bits. The AP 101 issues an interrupt to the CPU 121 when all of the three searches hit the same row.

(6-3) Setting of output sequence No data is output from the output port of the address processor 101. Therefore, it is set not to output data to all the AOC registers.

When these settings are completed, the CPU 121
Issues a SWIOP command to the address processor 102 to transition the address processor 102 to the input / output mode.

(7) Search Operation of ATM Switching Device With reference to FIG. 11, the search operation of the exchange of the present invention after the initialization of each AP 101, 102 is completed and the mode is changed to the input / output mode will be described.

(7-1) Data input to AP 101, 102 When the data of 1 cell is stored in the internal FIFO, the NT 301 determines whether the received information is network information or user information depending on the value of PT. Is determined (S120). If the received cell is network information, an interrupt is issued to the CPU 121. Then, the CPU 121 moves from the NT 301 to the AT.
Data in the M information field (see FIG. 6) is read, and necessary processing is performed according to the read data (S13).
0). If the receiving cell is user information, NT301
1 to AP 101, 102 for DMAC 103
Requests data transfer of 9 bytes. DMAC103 is
Address signal (AD
R), read signal (RD) and chip select signal (CS) are output to read data, and AP101, 1
Data is transferred by outputting a write signal (WT) to the 02 input port and writing the data (S1).
40).

Since the APs 101 and 102 have transited to the input / output mode, when the WT signal is input from the input port, the data on the input port is read according to a preset input sequence and a search is performed.

VP of ATM cell received by AP 102
If I, VCI, and MID are registered, AP10
2 finds the row by searching and issues an interrupt to the CPU 121. When an interrupt occurs (S15
0), the CPU 121 reads the segment address of the hit segment from the HHA register of the address register of the AP 102 (S160). Next, a value obtained by adding 2 to the read segment address is written in the address register of the AP 102 to specify the port address of the hit data (S170). Then Memory_
The value of the output port is read from the AR register (S18
0), the connection from the port to which the AP is connected to the read output port is set to the SEU 111 (S1)
90). The CPU 121 further sets bits other than the lower 4 bits of the first comparand register of the AP 102 to 0.
(S200). However, when connected to the UNI, bits other than the lower 4 bits and the upper 4 bits are rewritten to 0.

(7-2) Data Output from AP 102 Next, the CPU 121 sets the 4-byte data transfer from the AP 102 to the SEU 111 in the DMAC 103 (S
210). The DMAC 103 outputs the output enable signal (OE) and R to the output port 220 of the AP 102.
Data is transferred by outputting D and reading the data and outputting CS and WR to the SEU 111 and writing the data.

When the RD signal is input to the output port, AP 102 outputs data from the output port according to a predetermined output sequence. That is, the VPI and VCI values of the output side line stored in segment 2,
Logical OR with the value of the first comparand register (O
R) is calculated, and the obtained 32-bit data is output every 8 bits. Since PT and CLP of the input data are stored in the lower 4 bits of the first comparand register and the other bits are set to 0, AP
From the output port of the NN in the line on the output side of FIG.
Information of the 1st octet to the 4th octet of I is output. When connected to the UNI, the GFC of the received ATM cell is stored in the output ATM cell.

When the 4-byte data transfer from the AP is completed, the DMAC 103 issues an interrupt to the CPU 121. Then, the CPU 121 continues to
Data transfer of 48 bytes from 1 to SEU111 is set (S220). As a result, the ATM cell shown in FIG. 5 is input to the SEU 111.

The cell data input to the SEU111 is
The data is transferred to the output port, and is transferred to the output port NT301 by the output port DMAC 103 based on the setting from the CPU 121 (S230). The output port NT 301 converts the transferred data into serial data and sends it to the output AT network 150. As a result, the ATM input to the ATM switching device is
Cell transfer can be done. When the transfer is completed, C
The PU 121 issues an SQRST command to the AP 102 and returns the input / output sequence to the beginning (S24
0).

(7-3) Setting VPI and VCI If no interrupt is generated from the address processor 102 in S150, the VPI and VCI of the received ATM cell are set.
And the MID is not registered in the address processor 102. Such ATM cells are typically BOM or S
It is SN. Received BOM or SSN DA is AP1
If it is registered in 01, the AP 101 finds the row by searching and issues an interrupt to the CPU 121. When an interrupt occurs (S300), the CPU 121 performs call setting processing (S500). If no interrupt is generated from the AP 101 (S300), necessary exception processing is performed (S400).

FIG. 12 shows details of the call setting process (S500). The CPU 121 reads the segment address of the hit segment from the HHA register of the address register of the AP 101 (S510). Next, the value obtained by adding 3 to the read segment address is written in the address register of the AP 101 to specify the port address of the hit data (S515). Then Memo
Read the value of the output port from the ry_AR register (S5
20). There are multiple ports A on the transmission line corresponding to the DA.
If registered in P101, the search hits on multiple rows. Therefore, the processes of S510 to S520 are repeated until the output port values of all the hit rows are read (S525). If there is a hit at multiple ports (S530), TC is set in the ATM information field.
It is determined whether the P DEST is included (S54
0), if not included, set the ATM cell to NT301
(S550), and the process of S500 ends.

T is set in the information field of the received ATM cell.
If CP DEST is included (S540), D
The output line is selected by EST (S560). For example, since a transaction (application) requires high security, if DEST indicates a transaction (application), a line with high security is selected. Further, for example, a data frame belonging to the telnet usually does not require very high security. Therefore, if DEST indicates telnet, a line with low security is selected. The data characteristics required for each DEST value and the characteristics of each line are stored in the RAM 123, and the CPU 121 selects an appropriate line according to the data.

Next, the VPI and VCI used in the selected line are determined (S570), and the V of the received ATM cell is set.
The PI / VCI and MID are written to the unused row segments 0 and 1 of the AP 102, the port number of the selected line is written to the segment 2 of the AP 102, and the selected VPI and VCI are written to the AP 10.
Write to segment 3 of 2 (S580). Next, the processing of the received ATM cells is returned to the head of the queued ATM cells, and the search processing shown in FIG. 11 is performed again on these received ATM cells (S590). The VPI, VCI, and MID of the queued ATM cell are already A
Since it is registered in P102, the search hits in AP102, and the queued ATM cell can be transferred.

[Other Embodiments] In the first embodiment, the CPU 121 selects one transmission line among a plurality of transmission lines based on the data stored in the RAM 123. But S
In addition to T and DA, various values of DEST are stored in the CAM of AP 101 as search conditions, and one suitable line is A
You may search by P101.

The network system shown in FIG. 1 and the exchange shown in FIG. 2 can be applied to an exchange that performs switching using an Ethernet type data frame and a network using such an exchange. FIG.
Shows an Ethernet type data frame. In FIG. 13, DA is a destination address and corresponds to the destination identification information of the present invention. In the CAM array of AP 102, DA is used instead of VPI, VCI, and MID of the first embodiment.
And TYPE are stored. The CAM setting of the AP 101 is the same as that in the first embodiment.

The present invention can also be applied to an exchange that performs switching using an IEEE802.3 data frame and a network that uses such an exchange. FIG. 14 shows the data structure of an IEEE802.3 data frame. DA corresponds to the destination identification information. In this case, the CAM array includes the VPI, VCI,
And, instead of MID, the IEEE802.3 DA and SNAP TYPE are stored. CAM of AP101
Is the same as that in the first embodiment.

The present invention can also be applied to an exchange that performs switching using a TCP / IP data frame and a network system that uses the exchange.
FIG. 15 shows the structure of the IP data frame. In FIG. 15, PROT indicates a protocol used above IP. DEST is a destination address and corresponds to the destination identification information of the present invention. In this case, DEST and PROT are stored instead of the VPI, VCI, and MID of the first embodiment. The CAM setting of the AP 101 is the same as that in the first embodiment.

[0096]

As described above, according to the present invention, an exchange identifies a transmission destination of a data frame based on transmission destination identification information of a specific layer among a plurality of layers described in the data frame. Then, one of the plurality of lines that can be transmitted to the identified destination can be selected based on the characteristics of the data in the layer above the specific layer. Therefore, even when lines of various networks provided by a plurality of vendors are connected to the exchange, the exchange can select a line having appropriate characteristics according to the information to be transmitted.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a configuration of a network system of the present invention.

FIG. 2 is a hardware block diagram of the exchange of the present invention.

FIG. 3 is a hardware block diagram of an address processor (AP).

FIG. 4 is an explanatory diagram showing a structure of a CAM basic word.

FIG. 5 is an explanatory diagram showing a configuration of a CAM array.

FIG. 6 is an explanatory diagram showing the structure of an ATM cell.

FIG. 7 is an explanatory diagram showing a data structure of AAL.

FIG. 8 is an explanatory diagram showing a data structure of BOM, EOM, COM, and SSN.

FIG. 9 is a flowchart showing details of call setting processing.

FIG. 10 is an explanatory diagram showing a data structure of a TCP header.

FIG. 11 is an explanatory diagram showing setting of CAM arrays of AP 101 and AP 102.

FIG. 12 is a flowchart showing a search operation by the address processor (AP) of the present invention.

FIG. 13 is an explanatory diagram of an Ethernet type data frame.

FIG. 14 is an explanatory diagram of a data frame of IEEE802.3.

FIG. 15 is an explanatory diagram of an IP data frame.

[Explanation of symbols]

10 ATM Network 11-17 ATM Switch 21-24 Terminal 31 IWU 44-46 LAN Terminal 101, 102 Address Processor (AP) 103 Dynamic Memory Access Controller (D
MAC) 104 bus arbiter 111 switching element unit (SEU) 121 CPU 122 ROM 123 RAM 124 timer 125 input device 126 display device 131-134 address processor 150 ATM communication line 160-161 ATM data bus 170 CPU bus 210 input port 211 data formatter 212 Input port sequencer 220 Output port 222 Output port sequencer 230 CPU port 231 Flag logic 250 CAM array 251 Empty bit 252 Boundary bit 253 Segment number bit 254 Segment 255 Hit / miss hit flag 256 Access bit 301-308 Network terminator (NT)

Claims (13)

[Claims] 1. A data frame assembled on the basis of a communication protocol composed of a plurality of layers is received,
In the exchange that identifies the destination of the data frame based on the destination identification information in the specific layer among the plurality of layers described in the data frame, the line that can transmit to the destination is A plurality of connected data, which are data of a higher layer than the specific layer included in the data frame, and based on data representing characteristics of data contents of a higher layer than the upper layer, An exchange having a selecting means for selecting one of the lines. 2. The exchange according to claim 1, further comprising means for storing data representing characteristics of each of the plurality of lines, wherein the selecting means further includes data representing the characteristics, An exchange characterized by selecting one of the plurality of lines. 3. The exchange according to claim 1, wherein the data frame is an ATM cell, the specific layer is an ATM layer, and the destination identification information is VPI and VCI. TC is higher than a specific layer
An exchange which is the P layer, wherein the data of the upper layer is DEST in the TCP header. 4. The exchange according to claim 3, wherein the data frame is an AAL type 3/4 ATM cell, and a destination line associated with a VPI, VCI, and MID of a received ATM cell is searched. And a first search means that does not search the destination line by the first search means and the received ATM cell is a BOM or SSN, and is associated with the DA in the BOM or SSN. Second search means for searching for a destination line, and selecting means for selecting one destination line based on the DEST when there are a plurality of destination lines searched by the second search means. Storing means for storing the destination line selected by the selecting means in the first searching means in association with the VPI, VCI and MID of the receiving ATM cell; And a means for transferring the received ATM cell to the destination line searched by the searching means or the destination line selected by the selecting means. 5. The exchange according to claim 1, wherein the data representing the characteristic is data based on the security level of each of the plurality of lines. 6. The exchange according to claim 1, wherein the selection unit stores in advance position information indicating a position in the data frame of the transmission destination identification information, Means for selecting the identification information from the data string based on position information, means for searching the destination of the data string using the selected identification information, and inputting in advance what number data in the data frame And a means for storing start position information indicating whether to perform the search, and a search start means for starting the search by the search means when the data indicated by the start position information is input. An exchange having a communication semiconductor device provided with means for outputting information indicating the destination. 7. A switching device for switching an ATM cell, comprising: first searching means for searching whether or not there is a destination line associated with the VPI and VCI of the received ATM cell; and the destination line. And a received ATM cell is an AAL type 3/4 BOM or SSN, second search means for searching a destination line associated with the DA in the BOM or SSN. , The destination line searched by the second searching means,
The receiving ATM is stored in the storing means for storing in the first searching means in association with the VPI and VCI of the receiving ATM cell, and in the destination line searched by the first searching means or the second searching means. An exchange equipped with means for transferring cells. 8. A data frame assembled on the basis of a communication protocol composed of a plurality of layers is received,
In the exchange method of identifying the transmission destination of the data frame based on the transmission destination identification information in a specific layer among the plurality of layers described in the data frame, a line that can be transmitted to the transmission destination. When there are a plurality of, the data of the higher hierarchy than the specific hierarchy included in the data frame, based on the data representing the characteristics of the data content of the higher hierarchy than the higher hierarchy, the plurality of A switching method characterized by selecting one of the lines. 9. The switching method according to claim 8, further comprising means for storing data representing a characteristic of each of the plurality of lines, wherein the selecting means is further based on the data representing the characteristic. A switching method, characterized in that one of the plurality of lines is selected. 10. The exchange method according to claim 8, wherein the data frame is an ATM cell, the specific layer is an ATM layer, and the destination identification information is VPI and VCI. The upper layer than the specific layer is TC
An exchange method, which is a P layer, wherein the upper layer data is DEST in a TCP header. 11. A data frame assembled on the basis of a communication protocol composed of a plurality of layers is received, and destination identification information in a specific layer among the plurality of layers is described in the data frame. On the basis of,
In a network system including an exchange that identifies a transmission destination of the data frame, at least one of the exchanges is connected to a plurality of lines capable of transmitting to the transmission destination, and the exchange is connected to the data frame. One of the plurality of lines is selected on the basis of the data of the upper layer included in the specific layer, the data indicating the characteristic of the data content of the upper layer higher than the upper layer. A network system having selection means. 12. The network system according to claim 11, wherein the at least one exchange further comprises means for storing data representing characteristics of each of the plurality of lines, and the selection means further comprises: A network system, wherein one line is selected from the plurality of lines based on data representing the feature. 13. The network system according to claim 11, wherein the data frame is an ATM cell, the specific layer is an ATM layer, and the destination identification information is VPI and VCI. The upper layer than the specific layer is TC
A network system characterized in that it is a P layer, and the data of the upper layer is DEST in a TCP header.