JPH0797754B2 - Encoding transmission device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a coding transmission device for compressing and transmitting the number of bits per pixel of an image signal such as a digital television signal.

[Outline of Invention]

The present invention provides a background memory for storing background information on each of a transmitting side and a receiving side in an encoding transmission system applied to band-compress and transmit an image signal such as a digital television signal. By checking the motion state between consecutive frames of a predetermined cycle and holding fixed background information in these background memories, it is possible to form transmission data with a reduced number of bits compared to the number of bits of the original data. , By encoding only the necessary frames, the redundancy in the time direction can be removed, and a large compression rate can be realized.
Further, it is possible to solve the problem of missing image information (uncovered background noise) at the previous position when the moving object moves.

[Conventional technology]

As a method of encoding a television signal, there are known some methods for reducing the average number of bits per pixel or the sampling frequency for the purpose of narrowing the transmission band.

As an encoding method that lowers the sampling frequency, the image data is thinned to 1/2 by subsampling, and the position of the subsampling point and the subsampling point used at the time of interpolation are shown (that is, either above or below the interpolation point or left and right And a flag indicating whether to use the data of the sub-sampling point) has been proposed.

DPCM (differential PCM) is known as one of encoding methods for reducing the average number of bits per pixel. DPCM focuses on the fact that the correlation between pixels of a television signal is high and the difference between adjacent pixels is small, and the difference signal is quantized and transmitted.

As another encoding method for reducing the average number of bits per pixel, the screen of one field is subdivided into minute blocks, and the deviation of the pixel at the representative point and the level distribution of the data in the block is calculated for each block. There is something to transmit.

[Problems to be solved by the invention]

An encoding method that attempts to reduce the sampling frequency by using subsampling has a possibility that aliasing distortion may occur because the sampling frequency is halved.

DPCM has a problem that a coding error propagates to subsequent coding.

The method of encoding in block units has a drawback that block distortion occurs at boundaries between blocks.

An object of the present invention is to provide a coded transmission apparatus that does not have the problems of the above-mentioned conventional techniques such as the generation of aliasing distortion, the propagation of errors, and the occurrence of block distortion.

The applicant of the present application obtains a dynamic range defined by the maximum value and the minimum value of a plurality of pixels included in a two-dimensional block, as described in Japanese Patent Application No. 59-266407, and determines the dynamic range as the dynamic range. We have proposed a coded transmission system that performs adaptive coding. The present invention relates to an improvement of a coded transmission method using a two-dimensional block,
It is an object of the present invention to provide a coding transmission device which obtains a dynamic range for a three-dimensional block and adapts the dynamic range to code a digital television signal.

Still another object of the present invention is to introduce a background memory as described in Japanese Patent Application No. 58-237371, store background information in the background memory, and use a frame (or field) different from the background information. It is an object of the present invention to provide a coding transmission device that can realize a large compression rate and reduce the influence of uncovered background noise by compressing and coding only ().

[Means for solving problems]

The present invention relates to a blocking means for blocking input image data into blocks at a predetermined cycle over a plurality of temporally consecutive fields (or frames), and a coding for compressing and coding image data for each block and outputting a coded signal. Means, a background storage means for storing background image data, and the blocked image data are input, and it is determined whether or not there is a change in the data of the corresponding image position within a predetermined period,
The stopping determination means that outputs a determination code indicating the determination result is compared with the blocked image data and the image data of the corresponding image position read from the background storage means, and a match / mismatch is determined for each predetermined cycle. The comparing means for outputting the background code shown, and the discrimination code and the background code, the data of the corresponding image position does not change within a predetermined cycle, and the blocked image data and the background storing means of the corresponding image position. When the stored image data does not match, the output unit which outputs an update code for instructing the update of the image data stored in the background storage unit, and the encoding unit, which corresponds to the encoding unit, decodes the encoded signal. And the decoding means for outputting the decoded image data and the image data stored in the background storage means based on the update code as the decoded image data. Update control means for updating, and transmission means for transmitting the encoded signal, the background code and the update code, the encoding means is stored in the background storage means of the blocked image data and its corresponding image position The coding transmission device is characterized in that it is controlled by a background code so as to prohibit the output of a coded signal when it matches the existing image data.

Further, the present invention is a coding transmission and decoding device for receiving the data coded as described above, wherein the coding signal, the background code and the update code transmitted from the coding transmission means are received. Receiving means, corresponding to the encoding means, receiving side decoding means for decoding the encoded signal and outputting the decoded image data, and background storage means, corresponding to the receiving means for receiving the decoded image data from the receiving side decoding means Side background storage means, reception side update control means for updating the image data stored in the reception side background storage means with the decoded image data from the reception side decoding means based on the transmitted update code, and the transmitted background From the decoding image data from the decoding device on the receiving side and the decoding receiving device having a selecting device for selectively outputting the decoded image data stored in the background storage device on the receiving side based on the code. A coded transmission and decoding apparatus according to claim Rukoto.

[Action]

An image signal such as a television signal has a three-dimensional correlation in the horizontal direction, the vertical direction, and the time direction. Therefore, in the stationary portion, the pixel data included in the same three-dimensional block has a strong correlation. Therefore, it is easy to perform compression coding of data in units of blocks.

For example, the minimum level MI shared by pixel data in a block
Even if the dynamic range of the data DTI after removing N is quantized with a quantization bit number smaller than the original quantization bit number, quantization distortion hardly occurs. By reducing the number of quantization bits, the data transmission bandwidth can be made narrower than the original transmission bandwidth.

Further, a background memory is provided, and it is checked whether or not the two-dimensional area of each field (or frame) forming the block matches that of the corresponding position of the background memory. When they match, the transmission of the encoded code in the area is omitted. In this case, when all the two-dimensional areas in the block are the same as the fixed background stored in the background memory in this case, it is not necessary to encode and transmit one image, and a high compression rate can be realized. Furthermore, the background information stored in the background memory can solve the problem of uncovered background noise in which the background information at the previous position disappears after the moving object moves.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. This description will be given in the following order.

a. Configuration of transmission side b. Configuration of reception side c. Block and blocking circuit d. Encoder block e. Quantization circuit f. Modified example a. Configuration of transmission side FIG. 1 shows the configuration of the transmission side of the present invention. Is shown as a whole. For example, an NTSC digital television signal in which one sample is quantized into 8 bits is input to an input terminal indicated by 1. This digital television signal is supplied to the blocking circuit 2.

The block circuit 2 converts the input digital television signal into a continuous signal for each block which is a unit of encoding. The output signal of the blocking circuit 2 is supplied to the stationary determination circuit 3. The stillness determination circuit 3 checks whether or not the corresponding pixels in the two-dimensional area included in each of the four frames in the three-dimensional block match each other, and outputs the 1-bit determination code SS indicating the match or mismatch as the pixel. It is a circuit that is generated for each. If they match, the discrimination code SS becomes high level. The stillness determination circuit 3 detects the absolute value of the difference between pixels at corresponding positions in two two-dimensional regions belonging to different frames, and when the absolute value of this difference is sufficiently small, the two pixels are the same. To be judged.

Reference numeral 4 denotes a background memory composed of a frame memory, and the output data of the update control circuit 5 is written in the background memory 4. The background data read from the background memory 4 is supplied to the comparison circuit 6. The input television signal from the blocking circuit 2 is supplied to the comparison circuit 6.

The comparison circuit 6 is a background code for each two-dimensional area of the block.
The SB and the pixel-based background code SP are generated. The background code SB for each 2D area indicates whether or not each of the 2D areas included in each of the 4 frames in the 3D block matches the background information at the corresponding position stored in the background memory 4. It is a 4-bit signal. That is, each of the 4 bits represents a match / mismatch for each two-dimensional area. The pixel-based background code SP is a 1-bit signal indicating whether or not the input pixel data and the corresponding pixel data in the background memory 4 match. The background code SP is
It becomes high level when they do not match.

In the comparison circuit 6, four 2's in each frame of the same block are
The absolute value of the difference between the pixel data included in the dimensional area and the pixel data of the background memory 4 at the position corresponding to the two-dimensional area is detected, and when the absolute value of the difference is sufficiently small, it is determined that the two match.

The output data of the blocking circuit 2 is the encoder block 7
Is supplied to. The encoder block 7 encodes each block according to the dynamic range. That is, the encoder block 7 calculates the maximum level MAX, the minimum level MIN, and the dynamic range DR of each block. By dividing the dynamic range DR by the number of steps corresponding to the number of quantization bits, the quantization width Δ of 4 bits is determined and the representative minimum level L0 of 8 bits is detected. The quantization width Δ and the pixel data DTI after the minimum level removal are quantized. It is determined in which of the divided areas the pixel data DTI after the minimum level removal is included, and a 4-bit code DT for specifying the area is formed by quantization.

The output of the encoder block 7 is supplied to the framing circuit 9 via the gate circuit 8. Further, the output of the encoder block 7 is supplied to the decoder block 11. The decoder block 11 performs a decoding process that is the reverse of the process of the encoder block 7, and the decoded image data is generated at its output. This image data is supplied to the update control circuit 5.

The judgment code SS from the stationary judgment circuit 3 and the background code SP for each pixel from the comparison circuit 6 are supplied to the AND gate 12. The update code SR is generated at the output of the AND gate 12. Background memory 4 when this update code SR is high level
The corresponding data of is updated. That is, when the four corresponding pixels belonging to each of the four frames in one block match and the corresponding input pixel does not match the corresponding data in the background memory 4, the update code SR is set to high level and the background The decoded data corresponding to this input pixel is written in the memory 4.

The update code SR is supplied to the framing circuit 9 and the update control circuit 5. Background code for each block from the comparison circuit 6
SB is supplied to the gate circuit 8 and the framing circuit 9.
In this embodiment, the update code SR, the background code SB, the quantization width Δ, the representative minimum level L0, and the encoded code DT are transmitted. These data are supplied to the framing circuit 9 and converted into transmission data.

As the form of transmission data, update code SR, background code
SB, representative minimum level L0, quantization width Δ and coding code DT
It is possible to use the one in which an independent error correction code is encoded in each of the data portions consisting of, and the parity of each error correction code is added and transmitted. Further, each of the update code SR other than the coded code DT, the background code SB, the quantization width Δ, and the representative minimum level L0 may be coded as an independent error correction code. Furthermore, the parity may be added by encoding an error correction code common to both the update code SR, the background code SB, the quantization width Δ, and the representative minimum level L0.

The transmission data is taken out at the output terminal 10 of the framing circuit 9. Although not shown, the transmission data from the framing circuit 9 is transmitted (or recorded in a recording medium) as serial data.

When it is determined by the background code SB for each block that the two-dimensional area forming the block of input data and the corresponding two-dimensional area stored in the background memory 4 are the same,
The gate circuit 8 prohibits the transmission of the encoded data in the two-dimensional area. Only the output of the encoder two-dimensional area 7 of the block which is not the same as the image stored in the background memory 4 is supplied to the framing circuit 9 through the gate circuit 8 and transmitted.

The update control circuit 5 includes a subtraction circuit for subtracting the read data of the background memory 4 from the decoded data from the decoder block 11 for each corresponding pixel, and a multiplication circuit for multiplying the output of the subtraction circuit by a predetermined weight coefficient for each pixel. And an addition circuit for adding the output of the multiplication circuit and the read data of the background memory 4, and a weighting coefficient generation circuit for generating a predetermined weighting coefficient.

The output data from the update control circuit 5 is Yk, the output data of the background memory 4 of the previous frame is Yk-1, and the corresponding pixel data in the image data from the decoder block 11 is Xk.
Then, assuming that the weighting coefficient is Wk, the output data Yk is generated from the update control circuit 5 according to the following equation.

Yk = Yk-1 + Wk (Xk-Yk-1) = WkXk + (1-Wk) Yk-1 When the update code SR is at a low level and the update is not performed, writing to the background memory 4 is prohibited or (Wk
= 0), and the same data as before is written.

When the update code SR is at the high level, the data Yk processed according to the calculation of the above equation is written in the background memory 4.
In this case, a memory for storing the weighting coefficient for each pixel is provided, and the weighting coefficient is read at the time of updating. That is, at the first update, for example, (Wk = 1/8) is set, and thereafter, the weighting coefficient is sequentially doubled and changed to (1/4, 1/2, 1). In this way, by changing the weighting factor, it is possible to shorten the response time and prevent the influence of colored noise when the background is switched.

b. Configuration on the receiving side FIG. 2 shows the configuration on the receiving (or reproducing) side. Input terminal
The received data from 21 is supplied to the frame decomposing circuit 22. The frame decomposition circuit 22 separates the coded code DT, the additional codes Δ, L0, the background code SB, and the update code SR, and also performs error correction processing. These 4-bit encoded code DT and additional code are supplied to the decoder block 23.

The decoder block 23 is the encoder block 7 on the transmission side.
Performs the reverse process of. That is, the 8-bit minimum level-removed data DT1 is formed, and this data DT1 and the 8-bit representative minimum level L0 are added to obtain the original pixel data PD.
I is decrypted. The output data PDI of the decoder block 23 is supplied to the update control circuit 25 and the selector 26.

The read output from the background memory 24 is supplied to the update control circuit 25. Update code SR from frame disassembly circuit 22
This controls the update of the background memory 24. Update code
When SR is at the high level, the contents of the background memory 24 are replaced by the restored data from the decoder block 23.

One of the read output of the background memory 24 and the restored data of the decoder block 23 is selected by the selector 26. By the background code SB for each block, the same 2 as the background memory 24
For the dimensional area, the background memory 24 is used instead of the restored data.
Output is selected. The output of the selector 26 is supplied to the block decomposition circuit 27.

The block decomposing circuit 27 is a circuit for converting the decoded data in the order of blocks into the same order as the scanning of the television signal, contrary to the blocking circuit 2 on the transmitting side. The original television signal is decoded and output to the output terminal 28 of the block decomposition circuit 27.

b. Description of Block A block, which is a unit of encoding, will be described with reference to FIG. In FIG. 3, B indicates one block consisting of two-dimensional regions b1, b2, b3, b4 belonging to each of four frames, the solid line indicates the odd field line, and the broken line indicates the even field. Indicates a line. Regions b1, b2, b3, b4 of (8 lines × 8 pixels) are formed by eight pixels included in each of the eight lines of each frame. Therefore, one block is composed of (8 × 8 × 4 = 256) pixels.

The smaller the quantization bit number of the code DT is, the better the redundancy can be suppressed. However, in order not to increase the quantization distortion, the number of quantization bits should not be reduced too much. When the number of quantization bits is 8, the level of the television signal can be 256 (0 to 255). However, in the stationary part except the non-stationary part such as the contour of the object, the level distribution of the pixels of one block is concentrated in a fairly narrow level range. In the case of a television signal, each pixel in a three-dimensional one block has a correlation, so that the dynamic range DR does not become so large in the stationary portion, and if the maximum value is 128th place, Is enough. Therefore, even if the number of bits of the encoded code is 4 as in this embodiment, the quantization distortion can be prevented from increasing.

That is, the dynamic range DR is 128 in the worst case. Even in this case, when the number of quantization bits is 4, the unit of division level is 8 and the quantization distortion is 4. This degree of goodness distortion cannot be visually identified. On the other hand, in the non-steady-state portion, the change width becomes large, but in the present invention, the dynamic range DR is adaptively determined, so that the response does not deteriorate in the transient portion.

FIG. 4 shows an example of the configuration of the blocking circuit 2 described above. Frame memories 15, 16 and 17 are cascade-connected to the input terminal 1. The pixel data of the current frame F4 and the pixel data of the previous three frames F3, F2, F1 of the current field fetched from each of the frame memories 15, 16 and 17 are supplied to the scan conversion circuit 18. Output terminal 19 of scan conversion circuit 18
Corresponds to the two-dimensional area b1, b2, b3, b corresponding to 4 frames.
The respective pixel data of 4 are sequentially obtained. That is, as shown in FIG. 5, corresponding areas b1, b2, b3, b4 in four consecutive frames F1, F2, F3, F4 are output in the order shown by the numbers. In each area, data is output according to the scanning order.

d. Encoder block FIG. 6 shows an example of the configuration of the encoder block 7.
As described above, the block circuit 2 sequentially supplies the input terminal indicated by 31 with the image data of the region in which encoding is required for each block. The pixel data from the input terminal 31 is supplied to the delay circuit 32, the selection circuit 33, and the selection circuit 34. One selection circuit 33, between the pixel data of the input digital television signal and the output data of the latch 35,
The one with the higher level is selected and output. The other selection circuit 34 selects and outputs the smaller one of the pixel data of the input digital television signal and the output data of the latch 36.

The output data of the selection circuit 33 is supplied to the subtraction circuit 37 and taken in by the latch 35. The output data of the selection circuit 34 is supplied to the subtraction circuit 37 and the latch 39, and at the same time, latched.
Captured by 36. A latch pulse is supplied to the latches 35 and 36 from the control unit 40.

A sampling clock synchronized with the input digital television signal is supplied to the control unit 40 from a terminal 41. A synchronizing signal synchronized with the input digital television signal is supplied to the control unit 40 from the input terminal 42. The control unit 40 supplies the latch pulse to the latches 35 and 36 and the latches 38 and 39 at a predetermined timing.

At the beginning of each block, the contents of latches 35 and 36 are set. The latch 35 is initialized with all the data of "0", and the latch 36 is initialized with the data of all "1". The maximum level is stored in the latch 35 among the pixel data of the same block that are sequentially supplied. In addition, the minimum level is stored in the latch 36 among the pixel data of the same block that is sequentially supplied.

When the detection of the maximum level and the minimum level is completed for one block, the maximum level of the block is generated at the output of the selection circuit 33. On the other hand, the minimum level of the block occurs at the output of the selection circuit 34. When the detection for one block is complete, the latches 35 and 36 are reset again.

The output of the arithmetic circuit 37 is the maximum level MA from the selection circuit 33.
The dynamic range DR of each block is obtained by subtracting the minimum level MIN from X and the selection circuit 34. The dynamic range DR and the minimum level MIN are latched in the latches 38 and 39 by the latch pulse from the controller 40, respectively.

The dynamic range DR stored in the latch 38 is supplied to the ROM 43. The ROM 43 divides the dynamic range DR according to the number of bits of the encoded code to generate the quantization width Δ. In other words, an 8-bit address is supplied to this ROM 43, and 1/16 (in the case of 4-bit quantization)
The quantization width Δ (4 bits) of the rounded result is read from the ROM 43. This quantization width Δ is taken out to the output terminal 47, and the quantization circuit
Supplied to 50.

The minimum level MIN stored in the latch 39 is supplied to the adding circuit 46 and also to one input terminal of the subtracting circuit 51. The input digital television signal PD via the delay circuit 32 is supplied to the other input terminal of the subtraction circuit 51. Therefore, the data DTI after the minimum level removal is obtained at the output of the subtraction circuit 51, and this data DTI is supplied to the quantization circuit 50. The quantizing circuit 50 has a configuration described later, and the 4-bit encoded code DT is taken out from the output terminal 48 thereof.

The other input terminal of the adder circuit 46 is supplied with data of ½ of the quantization width Δ via the ½ multiplication circuit 45. The representative minimum level L0 generated at the output of the adder circuit 46 is the output terminal 49.
Taken out.

e. Quantization Circuit FIG. 7 shows an example of the configuration of the ROM 43 and the quantization circuit 50 described above. However, for simplification of description, the number of quantization bits is not 4 bits but 2 bits, and the dynamic range is divided into 4.

In FIG. 7, 51 indicates an input terminal to which the dynamic range DR is supplied, and 52 indicates data after the minimum level is removed.
Indicates the input terminal to which DTI is supplied. Dynamic range D
The R level is set to 1/4 by the ROM 43, and the quantization width Δ is read from the ROM 43.

The output of the ROM 43 is supplied to the multipliers 54 and 55. The output tripled by the multiplier 54 is supplied to one input terminal of the level comparator 56. The output doubled by the multiplier 55 is supplied to one input terminal of the level comparator 57. RO
The output of M43 is supplied to one input terminal of the level comparator 58. The data DTI after the minimum level is removed is supplied to the other input terminal of each of the level comparators 56, 57 and 58.

If the respective outputs of the level comparators 56, 57, 58 are C1, C2, C3, these outputs C1, C2, C3 are output according to the level of the data DTI.
Changes as follows.

(1) (3/4) When DR ≤ DTI ≤ DR C1 = "1", C2 = "1", C3 = "1" (2) (2/4) DR ≤ DTI <(3/4) DR When C1 = '0', C2 = '1', C3 = '1' (3) (1/4) DR ≦ DTI <(2/4) DR C1 = '0', C2 = '0' , C3 = '1' (4) When 0 ≦ DTI <(1/4) DR C1 = '0', C2 = '0', C3 = '0' Output of the above level comparators 56, 57, 58 C1, C2 and C3 are supplied to the priority encoder 59. 2-bit encoded code on output terminal 48 by priority encoder 59
DT is obtained. The priority encoder 59 generates the coded code of (11) in the case of the above (1), generates the coded code of (10) in the case of the above (2), and generates the coded code of the above (3). Generates a coded code of (01),
In the case of (4) above, a coded code of (00) is generated.

The pixel data PD including the minimum level MIN in one block is
As shown in Fig. 8, minimum level MIN to maximum level MAX
It belongs to the dynamic range DR up to. ROM43 is
A quantization width Δ obtained by evenly dividing the dynamic range DR into four is output. Which of the divided level ranges the data DTI after removal of the minimum level belongs to is judged by the comparators 56, 57 and 58, and is converted into a 2-bit encoded code DT corresponding to the level range. Also, the minimum level MIN is 1/2
The representative minimum level L0 is calculated by adding Δ. These quantization width Δ, representative minimum level L0, and coded code DT are transmitted.

In this embodiment, as is apparent from FIG. 8, the dynamic range is equally divided by the quantization width Δ, and the median values L0, L1, L2, L3 of each area are used as the values at the time of decoding. This encoding method can reduce quantization distortion.

On the other hand, pixel data having the minimum level MIN and the maximum level MAX always exist in one block. Therefore, in order to increase the number of encoded codes with zero error,
As shown in FIG. 9, the dynamic range DR is (2 ^m −
1) (where m is the number of quantization bits), the minimum level MIN may be the representative minimum level L0, and the maximum level MAX may be the representative maximum level L3.

When performing the quantization shown in FIG. 9, the minimum level MIN is directly output as the representative minimum level L0, and the ROM 43 (1/1
It is said that 5) is divided.

The quantizer 50 uses a digital divider in addition to the configuration shown in FIG. 7, supplies the quantization width Δ to the digital divider as a denominator input, and divides the data DTI after removal of the minimum level. It may be configured to supply it to the container as a molecular input. This divider produces a 2-bit output corresponding to a value obtained by rounding down fractions below the decimal point as an encoded code.

f. Modified example In the above description, the encoded code DT, the quantization width Δ, and the representative minimum level L0 are transmitted. However, the dynamic range DR may be transmitted as the additional code instead of the quantization width Δ, and the quantization width Δ or the dynamic range DR may be transmitted.
Alternatively, the representative maximum level may be transmitted.

In addition, one block of data is combined with a frame memory, a line delay circuit, and a sample delay circuit,
You may take out at the same time.

Further, by increasing the number of bits of the background code SB for each block, in addition to matching and non-matching with the information stored in the background memory, the information of the mutual relationship between the areas of each frame may be displayed. good. That is, four areas b1, b2, b
When 3, b4 match each other, but different from the information stored in the background memory, only the encoded output of one area is transmitted, and so on. If only the data is transmitted, further compression becomes possible.

〔The invention's effect〕

According to the present invention, the amount of data to be transmitted can be sufficiently reduced compared to the original data, and the transmission band can be narrowed. Further, the present invention has an advantage that the original pixel data can be almost completely restored from the received data in the stationary part where the change width of the pixel data is small, and the image quality is hardly deteriorated. Further, according to the present invention, since the dynamic range is determined corresponding to each block, the response at the transitional part such as the edge where the change width is large becomes good.

Further, according to the present invention, by providing the background memory, the redundancy in the time direction can be removed without deterioration of the image quality, so that high compression can be achieved. However, since the background information is stored in the background memory, it is not affected by the uncovered background.

[Brief description of drawings]

FIG. 1 is a block diagram of a transmitting side according to an embodiment of the present invention, FIG. 2 is a block diagram showing a configuration of a receiving side, and FIG. 3 is a schematic diagram used for explaining a block which is a unit of encoding processing. 4, FIG. 5 and FIG. 5 are schematic diagrams for explaining an example of the configuration of a block circuit, and FIG. 6 is a block diagram of an example of an encoder block, and FIG. 7 is a block diagram of an example of a quantization circuit. , FIG. 8 and FIG. 9 are schematic diagrams for explaining one example of quantization and another example. Description of main symbols in the drawings 1: Digital television signal input terminal, 2: Blocking circuit, 3: Stillness determination circuit, 4: Background memory, 5: Update control circuit, 7: Encoder block, 8: Gate circuit, 11: Decoder block.

Claims (2)

[Claims] 1. Blocking means for blocking input image data into blocks at a predetermined cycle over a plurality of temporally consecutive fields (or frames), and compressing and coding the image data for each block to output a coded signal. An encoding unit, a background storage unit that stores background image data, and the blocked image data are input, and it is determined whether or not there is a change in the data of the corresponding image position within the predetermined period, and The stillness determination means for outputting a determination code indicating the determination result is compared with the image data at the corresponding image position read out from the blocked image data and the background storage means, and coincides with each other at every predetermined cycle. There is no change in the data of the corresponding image position within the predetermined period from the comparing means for outputting the background code indicating the mismatch and the discrimination code and the background code. Further, when the block image data and the image data stored in the background storage unit at the corresponding image position do not match, update for instructing the update of the image data stored in the background storage unit Output means for outputting a code, decoding means corresponding to the encoding means for outputting the decoded image data by decoding the coded signal, and the decoded image data are inputted and the background based on the update code. Update means for updating the image data stored in the storage means with the decoded image data, and transmission means for transmitting the encoded signal, the background code and the update code, the encoding means, When the blocked image data and the image data stored in the background storage means at the corresponding image position match, the encoded signal is output. To prohibit, coded transmission apparatus characterized by being controlled by the background code. 2. Blocking means for blocking input image data in a predetermined cycle over a plurality of temporally continuous fields (or frames), and compressing and coding the image data for each block to output a coded signal. An encoding unit, a background storage unit that stores background image data, and the blocked image data are input, and it is determined whether or not there is a change in the data of the corresponding image position within the predetermined period. The stillness determination means for outputting a determination code indicating the determination result is compared with the image data at the corresponding image position read from the blocked image data and the background storage means, and coincides with each other at every predetermined cycle. There is no change in the data of the corresponding image position within the predetermined period from the comparing means for outputting the background code indicating the mismatch and the discrimination code and the background code. In addition, when the block image data and the image data stored in the background storage unit at the corresponding image position do not match, update for instructing the update of the image data stored in the background storage unit Output means for outputting a code, decoding means corresponding to the encoding means for outputting the decoded image data by decoding the encoded signal, and the decoded image data is inputted and the background based on the update code Update control means for updating the image data stored in the storage means with the decoded image data, and transmission means for transmitting the encoded signal, the background code and the update code, the encoding means, When the blocked image data and the image data stored in the background storage means at the corresponding image position match, the encoded signal is output. Encoding means for controlling by the background code so as to prohibit the above, and receiving means for receiving the encoded signal, the background code and the update code transmitted from the encoding transmission means, and the encoding A receiving side decoding means for decoding the coded signal and outputting decoded image data, and a receiving side background corresponding to the background storing means for storing the decoded image data from the receiving side decoding means. Storage means; reception side update control means for updating the image data stored in the reception side background storage means based on the transmitted update code with the decoded image data from the reception side decoding means; Selectively the decoded image data from the receiving side decoding means and the decoded image data stored in the receiving side background storage means based on the background code Coded transmission and decoding apparatus characterized by comprising a decoding receiving means having a selecting means for force.