JPH0795078A - A/d converter - Google Patents

Abstract

PURPOSE:To simplify the configuration and to attain multi-bit processing by using components of a comparator circuit in common for each comparator circuit. CONSTITUTION:A comparator circuit 211 corresponding to a reference voltage VR1 includes a selection means 221 and a 1-stage chopper circuit 231(1), a comparator circuit 212 corresponding to a reference voltage VR2 includes a selection means 222 and 2 stages of chopper circuits 232(1), 232(2),..., and a comparator circuit 21255 corresponding to a reference voltage VR255 includes a selection means 22255 and two-stage of chopper circuit 23255(1), 23255(2) Then some comparator circuit outputs having the two stages of chopper circuits are given to an input of a common chopper circuit 25 via a corresponding switch 24i, other comparator outputs are given to a control circuit 28 via latches 26, 27, from which a signal phiA used to turn on/off the switch 24i is outputted. Thus, some comparator circuits use chopper circuits of 3 and succeeding stages in common, then number of the chopper circuits is decreased to simplify the entire configuration and this A/D converter is useful for an application of 10-bits or over especially.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel type or serial-parallel type AD converter suitable for use in digital video equipment such as a digital video camera, and more particularly to a chopper type comparator circuit. The present invention relates to improvement of an AD converter.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing the principle of a chopper circuit. Reference numeral 1 denotes a CMOS inverter amplifier (hereinafter abbreviated as "amplifier") having a gain G, and the input of this amplifier 1 is passed through a capacitor 2 to a first voltage VA or a second voltage VB.
, And its input / output can be connected by the negative feedback switch 3.

Now, when the negative feedback switch 3 is turned on and the first voltage VA is applied, the capacitor 2 is charged with VA, and the output VO of the amplifier 1 becomes the threshold value V _T (V _{T of the} amplifier 1). Is approximately equal to 1/2 of the power supply voltage of the amplifier 1). Hereafter, this convergence operation is reset.
Say Next, the negative feedback switch 3 is turned off and the second
When the voltage VB is applied, the output VO of the amplifier 1 changes to VO ′, and the change width ΔVO is given by the following equation.

ΔVO = G (VA-VB) ... That is, if the second voltage VB is slightly higher than the first voltage VA, the output VO of the amplifier 1 becomes a low potential, and vice versa. If the voltage VB is even lower than the first voltage VA, the output VO of the amplifier 1 becomes high potential. Therefore,
It is possible to compare the magnitude of the second voltage VB with the first voltage VA as a reference.

FIG. 5 is an actual configuration diagram of a chopper type comparator (see, for example, Japanese Patent Laid-Open No. 63-51717). In this figure, VA is a first voltage, VB is a second voltage, and these two voltages VA and VB are synchronized with complementary clock signals φ and φ bar (φ bar is a reverse phase signal of φ). It is selectively selected by the first and second switches 10 and 11 which are turned on / off in reverse phase. The first and second switches 10 and 11 form a selection means 12.

A plurality of stages of chopper circuits 13, 14, 15, ... Are cascaded to the output of the selecting means 12,
These chopper circuits 13, 14 and 15 are similar to those shown in FIG. 4 in that the amplifier 1 _i , the capacitor 2 _i and the negative feedback switch 3 are provided.
It is composed of _i (i is 13, 14 or 15). Negative feedback switch ₃₁₃ in each stage, 3 _14, 3 _15, ... they are complementary clock signals phi, phi is turned on / off in opposite phases in synchronization with the bar. This is to reduce the power supply noise by making the reset operation of the amplifier 1 _i every other stage. That is, the amplifier 1 _i is a CM configured by connecting a pMOS transistor and an nMOS transistor in series between two power supplies (V _CC , V _DD ).
OS type inverter amplifier, pM at reset
This is because both the OS transistor and the nMOS transistor are turned on and a through current flows between the two power supplies. Further, the reason why they are turned on / off in reverse phase is that the comparison result of the first stage is sequentially transferred to the latter stage in synchronization with the clock signal to realize the pipeline operation as a whole.

The change widths ΔV ₁ , ΔV ₂ , ΔV ₃ of the output voltage of each stage of the chopper type comparator are given by the following equations (1) to ( ₃₎ , and the clock timing is t1 as shown in FIG.
→ ΔV ₁ , t2 → Δ2, t3 → ΔV ₃ . ΔV ₁ = G ¹ (VA-VB) ...... ΔV ₂ = G ² (VA-VB) …… ΔV ₃ = G ³ (VA-VB) …… G is the gain of the amplifier 1 _i . If all amplifiers 1 _i have the same gain, ΔV ₁ in the first stage is G times and ΔV ₁ in the second stage is
V ₂ is G × G = G ² times, and ΔV _{3 in the} third stage is G × G × G =
It can be seen that it becomes G ³ times and is amplified by G times as the number of stages increases.

[0008]

By the way, in such a conventional chopper type comparator, it is intended to reduce power supply noise and realize pipeline operation by operating a plurality of stages of chopper circuits in the reverse mode. A thing
There is room for improvement in terms of simplifying the overall configuration of the -D converter and supporting multiple bits.

That is, the n-bit parallel comparison type AD converter (a) divides the full-scale voltage (V _H -V _L = V _FS ) by 2 ⁻ⁿ V _FS and divides it by 2 ⁿ −1. Of the reference potential (V _Ri : i is 1, 2, ..., 2 ⁿ −1), and (b) the input analog voltage V _in is compared with each comparison reference potential V _Ri to _obtain V _{If in} > V _Ri , “1”, V
_{When in} <V _Ri, a binary signal that becomes “0” is output 2 ⁿ
-1 basic comparison circuit, (c) a gate circuit for determining the boundary between the "1" output group and the "0" output group, (d) an encoder circuit for converting the output of the gate circuit into n-bit binary data Since the requirement (b) corresponds to the above-mentioned chopper type comparator, 2 ⁿ -1 chopper type comparators are required. For example, in an 8-bit A / D converter, 2 ⁸ -1 = 25.
What is required with 5 is 2 ¹⁰ with a 10-bit AD converter.
It is a huge number of -1 = 1023. [Object] Therefore, an object of the present invention is to provide a technique useful for increasing the number of bits by sharing the constituent elements of the comparison circuit with each comparison circuit and simplifying the configuration.

[0010]

In order to achieve the above object, the present invention provides m kinds of reference voltages (V _R1 , V _R2 , ...).
, V _Rm ) and m sets of comparator circuits for comparing the input analog voltage V _in with one reference voltage to generate a binary signal. Selection means for selectively selecting the input analog voltage V _in and one reference voltage given to the set, an inverter amplifier for inputting the output of the selection means through a capacitor, and an input / output of the inverter amplifier And a plurality of stages of chopper circuits each including a switch that can be connected to each other, the chopper circuits on the subsequent stage side of some comparison circuits are shared by the some comparison circuits, and the some comparison circuits are It is characterized in that a deciding means for deciding a sharing destination of the chopper circuit is provided on the basis of the output logics of the other comparison circuits.

[0011]

In the present invention, the chopper circuit on the rear stage side is shared by some of the 2 ⁿ -1 comparison circuits, and the overall configuration of the AD converter can be simplified.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. First Embodiment FIGS. 1 and 2 are views showing a first embodiment of an AD converter according to the present invention. First, the configuration will be described. In FIG.
20 is 2 ⁿ −1 (here, for convenience, n = 8 and 2
55 resistors R _{1 to} R ₂₅₅ are connected to full scale voltage (V _H
-V _L = V _FS ) is connected in series, and V _FS is resistance-divided at intervals of 2 ⁻ⁿ V _FS to form 255 reference voltages (V _Ri : i is 1,
2, ..., 255; the same applies hereinafter), 21 _i compares the input analog voltage V _in with each comparison reference potential V _Ri, and if V _in > V _Ri , “0”. , V _in <
In the case of V _Ri , there are 255 comparison circuits that output binary signals of “1”.

All the comparison circuits 21 _i are composed of chopper type comparators (see FIG. 5) similar to the conventional example at the beginning,
This is different from the conventional example in that the chopper circuit is shared by some comparison circuits. That is, the comparison circuit 21 ₁ (hereinafter “# 1 comparison circuit”) corresponding to the reference voltage V _R1 is selected by the selection means 22 _1.
And a one-stage chopper circuit 23 _{1 (1)} , and the comparison circuit 21 ₂ (hereinafter “# 2 comparison circuit”) corresponding to the reference voltage V _R2 is
Selector 22 ₂ and two-stage chopper circuit 23 _{2 (1)} , 23
Comparing circuit 21 including _{2 (2)} and corresponding to reference voltage V _R3
3 (hereinafter “# 3 comparison circuit”) includes a selection means 22 ₃ and a one-stage chopper circuit 23 _{1 (1)} , ...
_The comparison circuit 21 ₂₅₅ (hereinafter “# 255 comparison circuit”) corresponding to _R255 is configured to include selection means 22 ₂₅₅ and two-stage chopper circuits 23 _{255 (1)} and 23 _{255 (2)} .

The two-stage chopper circuit 23 _{i (1)} , 2
The outputs of several comparison circuits including 3 _{i (2)} (for convenience, two of # 2 comparison circuit 21 ₂ and # 255 comparison circuit 21 ₂₅₅ ) are shared chopper circuit 25 via switches 24 ₂ and 24 _255.
2 input chopper circuit 2
Comparison circuits other than some comparison circuits including 3 _{i (1)} and 23 _{i (2)} (for convenience, # 1 comparison circuit 21 ₁ and # 3 comparison circuit 21 ₃
(2) of the latches 26 and 27 and the outputs of the latches 26 and 27 to the control circuit 28.

The control circuit (determining means) 28 includes the latch 2
Outputs of 6 and 27 (# 1 comparison circuit 21 ₁ and # 3 comparison circuit 2
Switch 24 ₂ or 24 ₂₅₅ based on the output of 1 ₃ )
A control signal φA for selectively turning on / off is output. For example, when there is a boundary between "1" and "0" in the outputs of the latches 26 and 27, the switch 24 ₂ is turned on and
The shared chopper circuit 25 is connected after the 2 comparison circuit 21 ₂ . Therefore, in this case, the # 2 comparison circuit 21 ₂ substantially has a three-stage chopper circuit.

Next, the operation will be described. Now, consider a case where the input analog voltage V _in is lower than V _R1 and higher than V _R3 , for example. First, in the positive period (t ₀ ; see FIG. 2) of the clock signal φ, all the reference voltages V _Ri are selected by the selection means 21 _{1 to} 21 ₂₅₅ . At the same time, the selected voltage (V _Ri ) changes to the first stage chopper circuit 23 _{1 (1)} to 2
3 _{255 (1)} capacitor (see capacitor 2 _{13 in} Fig. 5) is charged and the first stage chopper circuit 23 _{1 (1)} to 23
All _{255 (1)} are reset.

Next, the negative period (t ₁ ) of the clock signal φ
Then, in the first stage chopper circuit 23 _{1 ( 1)} to 23 _{255 (1)} , Δ
V ₁ = G (V _in −V _Ri ) is calculated. At the same time, the calculation result (ΔV ₁ ) is the chopper circuit 23 _{2 (2)} of the second stage of the # 2 comparison circuit 21 ₂ and the second stage of the # 255 comparison circuit 21 ₂₅₅ , 2
The capacitor of 3 _{255 (2)} is charged, and the chopper circuits 23 _{2 (2)} and 23 _{255 (2)} of the second stage are reset.

At this time, the operation result (ΔV ₁ ) of the # 1 comparison circuit 21 ₁ is a high potential equivalent to “1” because V _in <V _R1 , and the operation result of the # 3 comparison circuit 21 ₃ ( Δ
V ₁ ) is a low potential equivalent to “0” because V _in > V _R3 . Therefore, in this case, since there is a boundary between "1" and "0" in the outputs of the latches 26 and 27, the control circuit 28 determines that the switch 24 ₂ is turned on and the # 2 comparison circuit 21
After ₂ , the shared chopper circuit 25 is connected.

Next, when the clock signal φ is in the positive period (t₂)
Then, all the first stage chopper circuits 23_{1 (1)}~ 23
_{255 (1)}Is reset and the second stage chopper circuit
23 _{2 (2)}, 23_{255 (2)}At ΔV₂= G²(V_in-V_Ri)But
Is calculated. At the same time, this calculation result (ΔV₂) Is new
Char to the connected shared chopper circuit 25 capacitor
The common chopper circuit 25 is reset.

Next, when the clock signal φ is in the negative period (t₃)
Then, the first stage chopper circuit 23_{i (1)}And a new ΔV
₁Is calculated, and the result of the calculation
Circuit 23_{2 (2)}, 23_{255 (2)}Is reset and the same
Sometimes, the shared chopper circuit 25 causes ΔV₃= G³(V_in-V
_R2) Is calculated. Then, this calculation result (ΔV₃)But
It is given to the output inverter amplifier and
It is compared with the threshold of the data amplifier and ΔV is higher than the threshold.
₃Is 0 when the value is large, ΔV is greater than the threshold value ₃Is small
When it is not present, a binary signal that becomes "1" is extracted.

Therefore, according to the present embodiment, the chopper circuits of the third and subsequent stages can be shared by some comparison circuits.
The number of chopper circuits can be reduced to simplify the overall configuration of the AD converter, and a technique useful for an AD converter of 10 bits or more can be provided. Second Embodiment FIG. 3 is a diagram showing a second embodiment of the AD converter according to the present invention.

First, the structure will be described. In FIG. 3, V
i is an input analog voltage, and Vr1 and Vr2 are reference voltages (provided that Vr1> Vr2). 30 is the input voltage Vr
1 is a # 1 comparison circuit, 31 is a # 2 comparison circuit corresponding to the input voltage Vr2, and these # 1 comparison circuits 30
And the # 2 comparison circuit 31, there are two reference voltages Vr1,
A # 1.5 comparison circuit 32 corresponding to an intermediate voltage of Vr2 [(Vr2 + Vr1) / 2] is provided.

The # 1 comparison circuit 30 includes a selection means 30a for selectively selecting Vi and Vr1 in synchronization with the complementary clock signals φ and φ bar, and a selection means 30 for always selecting Vr1.
b, a first-stage chopper circuit 30c that captures the outputs of these two selecting means 30a and 30b, and a second-stage chopper circuit 30d that captures the outputs of the first-stage chopper circuit 30c. Reference numeral 31 is a selection means 31a for selectively selecting Vi and Vr2 in synchronization with the complementary clock signals φ and φ bar, and a selection means 31 for always selecting Vr1.
b, a first-stage chopper circuit 31c that captures the outputs of these two selecting means 31a and 31b, and a second-stage chopper circuit 31d that captures the outputs of the first-stage chopper circuit 31c. The comparison circuit 32 has only the second stage chopper circuit 32d. In addition, each comparison circuit 3
The chopper circuits of the third to third stages 0 to 31 are omitted.

All chopper circuits 30c, 30d, 31
c, 31d and 32d are differential type amplifiers (hereinafter referred to as "amplifiers") 30e, 30f, 31e and 3 having complementary input / output.
1f and 32f, each of the complementary inputs has capacitors 30g, 30h, 30i, 30j, 31g,
The output from the selection means or the amplifier at the previous stage is given through 31h, 31i, 31j, 32i, and 32j, and the switches 30k, 30m, and 30n are provided between the input and output of the amplifier.
30p, 31k, 31m, 31n, 31p, 32n, 3
2p is connected.

For example, the chopper circuit 30c in the first stage of the # 1 comparison circuit 30 applies the output of the selecting means 30a to the non-inverting input (+ input) of the amplifier 30e via the capacitor 30g and the output of the selecting means 30b. The condenser 30
is given to the inverting input (-input) of the amplifier 30e via h,
Furthermore, a switch 30k is provided between the non-inverting input and the negative logic output.
The switch 30m connects the inverting input and the positive logic output.

The chopper circuit 32d of the # 1.5 comparison circuit 32 applies the positive logic output of the chopper circuit 30c of the first stage of the # 1 comparison circuit 30 to the non-inverting input of the amplifier 32f via the capacitor 32i. , # 2 comparison circuit 31
The negative logic output of the first stage chopper circuit 31c is given to the inverting input of the amplifier 32f via the capacitor 32j, and the non-inverting input and the negative logic output are connected by the switch 32n, and the inverting input and the positive logic are connected. Switch 3 between outputs
It is configured by connecting with 0p.

The negative logic output and the positive logic output of each amplifier are identified by the abbreviations shown in Table 1 below. The change amount of each output during one cycle of the clock signal φ is
Given as follows: That is, the change amount ΔV of A1
A1 is

[0028]

[Equation 1]

The change amount ΔVA1 bar of A1 bar is

[0030]

[Equation 2]

The change amount ΔVA2 of A2 is

[0032]

[Equation 3]

A2 bar change amount ΔVA2 bar is

[0034]

[Equation 4]

The change amount ΔVB2 of B2 is

[0036]

[Equation 5]

The amount of change in B2 bar ΔVB2 bar is

[0038]

[Equation 6]

The change amount ΔVC1 of C1 is

[0040]

[Equation 7]

The change amount ΔVC1 bar of C1 bar is

[0042]

[Equation 8]

The change amount ΔVC2 of C2 is

[0044]

[Equation 9]

The change amount of C2 bar ΔVC2 bar is

[0046]

[Equation 10]

Is given by Therefore, according to the present embodiment, as is clear from the above equations (5) and (6), the intermediate voltage [(Vr2 + Vr) of the two comparison reference values Vr1 and Vr2 is obtained.
1) / 2] can be compared with Vi, and it is possible to cope with the increase in the number of bits without actually increasing the types of reference voltages.

[0048]

According to the present invention, since the constituent elements of the comparison circuit are shared by the respective comparison circuits, the structure can be simplified and a technique useful for increasing the number of bits can be provided.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first embodiment.

FIG. 2 is an operation timing chart of the first embodiment.

FIG. 3 is a configuration diagram of a second embodiment.

FIG. 4 is a principle configuration diagram of a chopper circuit.

FIG. 5 is a configuration diagram of a conventional chopper type comparator.

FIG. 6 is an operation timing chart of a conventional chopper type comparator.

[Explanation of symbols]

V _in : Input analog voltage V _Ri : Reference voltage 1: Inverter amplifier 2: Capacitor 3: Switch 20: Reference voltage generation circuit 21 _i : Comparison circuit 22 _i : Selection means 23 _{i (1)} , 23 _{2 (2)} , 23 _{255 (2)} : Chopper circuit 25: Shared chopper circuit 28: Control circuit (determining means)

Claims (2)

[Claims] 1. M types of reference voltages (V _R1 , V _R2 , ...,
V _Rm ) for generating a reference voltage and m sets of comparison circuits for comparing the input analog voltage V _in with one reference voltage to generate a binary signal. , connected to the input analog voltage V _in and selecting means for alternatively selecting the one reference voltage applied to the set, the output of the inverter amplifier and the inverter amplifier for receiving the output of said selection means through a capacitor And a plurality of stages of chopper circuits including a possible switch, and the chopper circuits on the subsequent stage side of some comparison circuits are shared by the some comparison circuits, and other than the some comparison circuits. An A-D converter, characterized in that a determining means is provided for determining a shared destination of the chopper circuit based on the output logic of the comparison circuit. 2. The A-D converter according to claim 1, wherein the inverter amplifier is a differential amplifier.