JPH0795410A - Intermediate value circuit - Google Patents

Abstract

PURPOSE:To obtain a center value circuit for median filter with hardware having a simple constitution by comparing two input voltages out of three input voltages with each other in three combinations to output larger values and outputting the minimum value of these outputted value as the intermediate value of three input voltages. CONSTITUTION:Input voltages V1, V2, and V3 are paired to obtain three combinations of data, and they are inputted to comparing circuits CMP1, CMP2, and CMP3 each of which selects and outputs higher one of input voltage in each combination, and three output voltages are inputted to a minimum value circuit MIN. In the circuit MIN, a supply voltage Vc is applied to drains of three pMOS transistors TRs Tr3, Tr4, and Tr5 through a high resistance R2, and thereby, drains have potentials higher than those of sources and are set to the high impedance state. Output voltages of respective comparing circuits are applied to respective gates, and the common output of drains are used as the output voltage. The circuit MIN uses the switching characteristic of pM0S TRs to make the TR, where the input voltage from the gate is minimum, conductive. Thus, the minimum voltage of input voltages appears as the output voltage. Consequently, a voltage V0 having the lntermediate value out of three inputted voltages is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an intermediate value circuit mainly used as a pixel density calculation unit in a filter circuit for image processing.

[0002]

2. Description of the Related Art As a means for removing noise from image data containing noise, smoothing (moving average method) has been conventionally adopted. The smoothing is to give the average of the densities of pixels in a certain area centered on that pixel instead of the density of a certain pixel, and is usually performed in units of 3 × 3 areas.

However, since there is a drawback that the sharpness of the edge of the image is lost when smoothing is performed, as a method of removing noise while maintaining the sharpness of the edge, instead of the density of a certain pixel, the pixel is centered. It is considered to use a median filter that gives the median value of pixels in a certain area.

[0004]

However, when calculating the median value in the median filter, it is necessary to sequentially compare the densities of the respective pixels for sorting, so that it takes a long processing time to perform processing by software, and hardware processing is performed. Was also difficult. Therefore, conventionally, the median filter has rarely been practically used for the purpose of removing noise.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and an object thereof is to provide a median value circuit used for a median filter with hardware having a simple structure.

[0006]

In order to achieve the above-mentioned object, an intermediate value circuit according to the present invention compares two input voltages in two ways in three ways and determines the larger value of each. The minimum value of these three maximum values is output as the intermediate value of the three input voltages, or the three input voltages are compared in two ways in three ways and the smaller value is output. Then, the maximum value of these three minimum values is output as an intermediate value of the three input voltages.

[0007]

Embodiments of the intermediate value circuit according to the present invention will be described below. When comparing the data a, b, and c, if the function that selects the maximum value of the data is defined as MAX () and the function that selects the minimum value is defined as MIN (), the intermediate value is obtained by one of the following operations. That is mathematically proven. The median value circuit according to the present invention is characterized in that an intermediate value of three data is obtained by utilizing this principle. MAX (MIN (a, b), MIN (a, c), MIN (b, c)) (1) MIN (MAX (a, b), AX (a, c), AX (b, c)) … (2)

FIG. 1 shows a specific example of a circuit for obtaining the median value of three data input as a voltage based on the above principle (1). This circuit includes a first, second and third input voltage V
As 1 set of data, 2 sets of V2 and 2 sets of V3,
Comparing circuit CMP1, which selects and outputs the higher input voltage,
Input to CMP2 and CMP3, and input the three voltages output from each comparison circuit to the minimum value circuit MIN. The minimum value circuit MIN outputs the intermediate value of the input voltages V1, V2 and V3.

In each of the comparison circuits CMP1, CMP2 and CMP3, a common power supply voltage Vc is applied to the drains of the two nMOS transistors Tr1 and Tr2 so as to have a higher potential than the source, and the source is grounded via the high resistance R1. By doing so, a high impedance state is achieved. Then, an input voltage is applied to each gate, and the common output of the sources is used as the output voltage.

These comparison circuits utilize the switching characteristic of an nMOS type transistor to make the transistor having the higher input voltage from the gate conductive, thereby generating a voltage on the source side of the other transistor and making it non-conductive. And As a result, the higher of the input voltages appears as the output voltage.

The minimum value circuit MIN is composed of three pMOSs.
-Type transistor Tr3, Tr4, Tr5 has a high resistance R at the drain
By applying the power supply voltage Vc via 2, the drain has a higher potential and a higher impedance than the source. Then, the output voltage of each comparison circuit is applied to each gate, and the common output of the drains becomes the output voltage.

The minimum value circuit MIN utilizes the switching characteristic of the pMOS type transistor to make the transistor having the smallest input voltage from the gate conductive, thereby generating a voltage on the drain side of the other transistor and bringing it into the non-conductive state. To do. Thereby, the minimum voltage among the input voltages appears as the output voltage.

Therefore, the circuit of FIG. 1 generates the voltage V0 having the intermediate value among the input voltages V1, V2 and V3 at the output end.

FIG. 2 shows a concrete example of a circuit for obtaining the median value of three data input as voltages according to the principle of (2). This circuit is a comparison circuit CMP4, CMP5, CMP6
Is a pMOS type transistor T as in the minimum value circuit of FIG.
It is composed of r6, Tr7 and a resistor R3 to output the lower one of the input voltages, and the maximum value circuit MAX is composed of nMOS type transistors Tr8, Tr9, Tr10 and a resistor R4 as in the comparison circuit of FIG. The maximum voltage of the input voltage is output.

Next, as an application of the above embodiment, a 3 × 3 convolution median filter circuit configured by using an intermediate value circuit will be described. As shown in FIG. 3, this median filter has density data a to i of nine pixels.
Is divided into three groups each consisting of three elements, intermediate values in each group are determined, and these intermediate values are determined to determine the overall intermediate value.

Here, the intermediate values of a, b, c are α, d, e,
Let β be the intermediate value of f and γ be the intermediate value of g, h, and i, and
Assuming that the intermediate value of the above is θ, α, β, and γ are first obtained by the above equation (1), and then θ is similarly obtained by the equation (1) based on these.

Α = MAX (MIN (a, b), MIN (a, c), MIN (b, c)) β = MAX (MIN (d, e), MIN (d, f), MIN (e, f)) γ = MAX (MIN (g, h), MIN (g, i), MIN (h, i)) θ = MAX (MIN (α, β), MIN (α, γ), MIN (β, γ))

FIG. 4 is a block diagram of the median filter of the above 3 × 3 convolution. The pixel density data is serially input from the input terminal PIN as discrete values divided into predetermined stages.

The filter circuit shown in FIG. 4 has two buffers BUF for storing the density data of three pixels which are sequentially input.
1, BUF2, nine sense amplifiers S-AMP1 to S-AMP9 that hold density data for one pixel, and three sense amplifiers are connected to each other to obtain an intermediate value of density data for three pixels. The intermediate value circuits MED1, MED2, MED3, and the second-stage intermediate value circuit MED4 for obtaining the intermediate value of the three density data input from these three intermediate value circuits.

Each of the sense amplifiers S-AMP1 to S-AMP9, when the voltage corresponding to the inputted concentration data does not coincide with the discrete value, pushes up the voltage to the discrete value immediately above the voltage drop. And has a function of latching the voltage corresponding to each data serially input during the calculation.

When the density data of 9 pixels is input at a predetermined timing, the first intermediate value circuit MED1 outputs a,
The intermediate value α of b, c is output, the second intermediate value circuit MED2 outputs the intermediate value β of d, e, f, and the third intermediate value circuit MED.
3 outputs the intermediate value γ of g, h and i. The fourth intermediate value circuit MED4 outputs the intermediate value θ of these α, β and γ to the output terminal POUT.
Output from.

A correction circuit (not shown) uses the intermediate value θ in place of the density data e. By applying such processing to the entire screen or a designated area, noise included in the image can be removed.

In the above description, only the example in which the circuit of FIG. 1 according to the equation (1) is used as each intermediate value circuit of FIG. 4 is described, but the circuit of FIG. 2 according to the equation (2) is also used. The result of can be obtained.

Further, in the above-mentioned embodiment, although the filter for 9 × 3 × 3 pixels is described, a filter for n × n pixels can be formed more generally. For example, when targeting 9 × 9 pixels,
By providing intermediate value circuits of 27 in the first stage, 9 in the second stage, 3 in the third stage, and one in the fourth stage, the intermediate value of the density of 81 pixels can be obtained.

[0025]

As described above, according to the present invention, it is possible to obtain the intermediate value of three data with a simple structure, without complicating the software when forming the median filter, and , Can be realized with relatively simple hardware.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an intermediate value circuit according to the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the intermediate value circuit according to the present invention.

FIG. 3 is an explanatory diagram of a 3 × 3 pixel row.

FIG. 4 is a block diagram of a median filter circuit using an intermediate value circuit according to the present invention.

[Explanation of symbols]

V1, V2, V3 Input voltage CMP1, CMP2, CMP3 Comparison circuit (higher voltage output) CMP4, CMP5, CMP6 Comparison circuit (lower voltage output) MIN minimum value circuit MAX maximum value circuit Tr1, Tr2, Tr8 , Tr9, Tr10 nMOS type transistors Tr3, Tr4, Tr5, Tr6, Tr7 pMOS type transistors R1, R2, R3, R4 resistors

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical display location // G06T 5/20 (72) Inventor Ozawa 3-5-18 Kitazawa, Setagaya-ku, Tokyo Takayama Building Takayamauchi Co., Ltd. (72) Inventor Akira Urushiba 3-5-18 Kitazawa, Setagaya-ku, Tokyo Takayama Building Takayamauchi Co., Ltd.

Claims (4)

[Claims] 1. A first comparator circuit which selects and outputs the higher one of the first input voltage and the second input voltage, and the higher one of the first input voltage and the third input voltage. A second comparison circuit for selecting and outputting the first input voltage, a third comparison circuit for selecting and outputting the higher one of the second input voltage and the third input voltage, and the first, second, and And a minimum value circuit that outputs the minimum voltage among the output voltages of the comparison circuit of No. 3 as the intermediate value of the first, second, and third input voltages. 2. Each of the comparison circuits sets the drains of the two nMOS transistors to a higher potential than the sources, sets the sources in a high impedance state, applies an input voltage to each gate, and outputs a common output of the sources to an output voltage. And the minimum value circuit makes the drains of the three pMOS transistors higher than the sources, and
2. The intermediate value circuit according to claim 1, wherein the drain has a high impedance state, and the output voltage of each of the comparison circuits is applied to each gate so that the common output of the drains serves as the output voltage. 3. A first comparison circuit for selecting and outputting the lower one of the first input voltage and the second input voltage, and the lower one of the first input voltage and the third input voltage. A second comparison circuit for selecting and outputting the first input voltage, a third comparison circuit for selecting and outputting the lower one of the second input voltage and the third input voltage, and the first, second, and And a maximum value circuit that outputs the maximum voltage among the output voltages of the comparison circuit 3 as the intermediate value of the first, second, and third input voltages. 4. Each of the comparison circuits sets the drains of the two pMOS transistors to a higher potential than the sources, sets the drains to a high impedance state, applies an input voltage to each gate, and outputs a common output of the drains. The maximum value circuit sets the drains of the three nMOS transistors to a higher potential than the sources, sets the sources to a high impedance state, and applies the output voltage of each of the comparison circuits to each gate. 4. The intermediate value circuit according to claim 3, wherein the common output of the sources is used as the output voltage.