JPH0784550A - Display control method and display controller - Google Patents

Abstract

PURPOSE:To make correct display without inducing display abnormality even if a parity signal is erroneously recognized by influence of temporary noise, etc. CONSTITUTION:This display controller for a display device capable of switching and displaying two display modes in accordance with a display mode switching signal Pa from outside has a detecting means 51 which outputs a change detection signal C1 by detecting the change of a display mode switching signal Pa to a signal corresponding to a second display mode during display with the first display mode, a state, discriminating means 52 which outputs a discrimination signal PC by discriminating whether the display mode switching signal Pa corresponds to the second display mode or not during the prescribed time from the detection of the change in the display mode switching signal Pa in accordance with the change detection signal C1 and a display mode switching means 54 which switches the display mode to the second display mode when the display mode switching signal corresponds to the second display mode during the prescribed time in accordance with the discrimination signal PC.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control method and a display control device, and more particularly to a display control mode having an interlaced display mode and a non-interlaced display mode, which can be displayed in either display mode based on a mode selection signal. The present invention relates to a control method and a display control device.

In recent years, colorization of display devices, particularly flat displays such as plasma displays has progressed, and it is required to support video signal display such as television broadcasting and laser discs.

Accordingly, not only the non-interlace display mode which has been conventionally performed in such a flat display, but also the display mode switching signal (hereinafter,
There is a demand for a display control method and a control device capable of automatically shifting to an interlaced display mode based on a parity signal).

[0004]

2. Description of the Related Art FIG. 14 shows an operation timing chart in a conventional display control device. In this case, if the level of the parity signal (see FIG. 14B) is inverted (“H” → “L” → “H” → ...) in each vertical synchronization period, interlaced mode display is performed. This means that if the parity signal has a constant level (either "H" or "L"), it means that non-interlaced mode display is performed.

The display control device generates a parity signal detection signal timing signal (see FIG. 14C) based on the timing of the vertical synchronizing signal V _sync (see FIG. 14A), and the parity signal at the detection timing. Detect the level of.

As a result, in FIG. 14, until time t ₁ , the parity signal changes from “H” to “L” every vertical synchronization period.
→ "H" → "L" → ...
The display control device judges that the display is the interlace mode display, and performs the interlace mode display in which one frame is divided into the even field and the odd field.

[0007] The time in t _1, a parity signal is fixed to "L" level, the parity signal detection timing of time t _2, the parity signal is at the "L" level, further time t ₃ of the parity signal detection "L" again at the timing
Detected as a level.

[0008] As a result, it is determined that the display control device parity signal becomes constant at "L" level, the transition from time t ₃ to the non-interlaced display. By the way, in the conventional color plasma display, for example, when 640 × 480 (dots) display is performed in the interlace mode, interlaced scanning such as CRT (CathodeRay Tube) is not actually performed.

This is to prevent the image from becoming dark by halving the amount of light when interlaced scanning is performed. Therefore, the same display is performed on two consecutive horizontal lines, and the two consecutive horizontal lines displaying the same data are shifted by one horizontal line between the odd field and the even field, so that apparently interlaced scanning is performed. it's shown.

More specifically, when image data for 240 horizontal lines corresponding to odd fields is sent,
Image data of the same horizontal line is simultaneously displayed on two horizontal lines (double scan) and displayed on 480 horizontal lines.

Similarly, 2 corresponding to even fields
When 40 horizontal lines of image data are sent, the image data of the same horizontal line is shifted by 1 horizontal line from the case of the odd field and displayed on 2 horizontal lines at the same time.
80 horizontal lines are displayed.

[0012]

In such a method of performing line interpolation, even if the transmitting side of image data transmits 240 horizontal lines of image data in one field for interlaced mode display, it is temporarily When the receiving side of the image data mistakenly recognizes that it is in non-interlaced mode due to the inclusion of noise, double scanning is not performed and only the 1 to 240 horizontal lines of the display screen are displayed, and the display is compressed vertically. As a result, nothing is displayed in the lower half of the screen.

More specifically, as shown in FIG. 15, at time t ₄ (or time t ₁₀ ) during display of the interlaced mode, the parity signal (see FIG. 15B) on the transmission side is at "H" level. However, the parity signal (see FIG.
(See (c)) is at the “L” level, the transmitted parity signal is at the “L” level at the parity signal detection timing at time t ₅ (or time t ₁₁ ) (see FIG. 15D). Is falsely recognized, and at time t ₆ (or time t ₁₂ ), the display shifts to the non-interlaced mode display, the double scan is not performed, and the screen enters the vertically compressed display state.

After that, at time t ₇ , if the parity signal on the transmitting side becomes "H" level and the parity signal on the receiving side also correctly becomes "H" level, it is transmitted at the parity detection timing at time t ₈ . The parity signal is recognized as being at "H" level.

As a result, the receiving side recognizes that the parity signal of the transmitting side has changed from the "L" level to the "H" level, that is, the interlace mode display,
Correct display will be performed.

Therefore, the normal display in the interlace mode and the abnormal display in the non-interlace mode (vertical screen compression) appear alternately, resulting in a screen display that is very difficult to see.

Similarly, even if the image data transmitting side transmits image data for 480 horizontal lines in one field for non-interlaced mode display, it is erroneously recognized that the image data receiving side is in the interlaced mode. In this case, there is a problem that a double scan is performed and the display is enlarged in the vertical direction, the lower half of the original image is not displayed, and an abnormal display state occurs.

Therefore, an object of the present invention is to perform a display control capable of performing a correct display without causing a display abnormality even when a parity signal is erroneously recognized due to a temporary noise or the like. A method and a display controller are provided.

[0019]

In order to solve the above-mentioned problems, the first invention is a display mode switching signal (P) from the outside.
In a display control method of a display device capable of switching between two display modes of an interlaced display mode and a non-interlaced display mode based on a), the first display mode is changed to the first display mode during display in the first display mode. Detecting that the corresponding display mode switching signal (Pa) has changed to the display mode switching signal (Pa) corresponding to the second display mode, and detecting the change of the display mode switching signal (Pa). From the display mode switching signal (P
a) determines whether or not the display mode switching signal (P) corresponds to the second display mode.
When the item a) corresponds to the second display mode, the display mode is switched to the second display mode.

A second invention is a display control method for a display device capable of switching between two display modes, an interlaced display mode and a non-interlaced display mode, based on a display mode switching signal (Pa) from the outside. Detecting that the display mode switching signal (Pa) corresponding to the first display mode has changed to the display mode switching signal (Pa) corresponding to the second display mode during display in the first display mode Then, it is determined whether or not the display mode switching signal (Pa) corresponds to the second display mode for a predetermined time after detecting the change of the display mode switching signal (Pa), and The table corresponding to the first display mode based on the display mode switching signal (Pa) until the predetermined time elapses after the change in the display mode switching signal (Pa) is detected. Generates an internal display mode switching signal (Pa ') mode switching signal (Pa) is the same signal, and outputs during said predetermined time, the display mode switching signal (P
When a) corresponds to the second display mode, the display mode switching signal (Pa) corresponding to the second display mode based on the display mode switching signal (Pa) after the lapse of the predetermined time. The internal display mode switching signal (Pa ') that is the same signal as the above is generated and output.

A third invention is a display mode switching signal (P
In a display control method of a display device capable of switching between two display modes of an interlaced display mode and a non-interlaced display mode based on a), the first display mode is changed to the first display mode during display in the first display mode. When it is detected that the corresponding external display mode instruction signal has changed to the display mode instruction signal corresponding to the second display mode, the alternative display mode switching signal (Pa ") corresponding to the second display mode. Is generated.

A fourth aspect of the present invention is a display control device for a display device capable of switching between two display modes, an interlaced display mode and a non-interlaced display mode, based on a display mode switching signal (Pa) from the outside. Detecting that the display mode switching signal (Pa) corresponding to the first display mode has changed to the display mode switching signal (Pa) corresponding to the second display mode during display in the first display mode change detection signal (C ₁₎ output detecting means (51) during said change detection signal (C ₁₎ a predetermined time after detecting the change of the display mode switching signal (Pa) based on, State determining means (52, TM, FF) for determining whether the display mode switching signal (Pa) corresponds to the second display mode and outputting a determination signal (PC).
_{2 to} FF ₄ ) and the discrimination signal (PC), the display mode is changed to the second display mode when the display mode switching signal corresponds to the second display mode for the predetermined time. And a display mode switching means (54) for switching to.

A fifth aspect of the present invention is a display control device for a display device capable of switching between two display modes, an interlaced display mode and a non-interlaced display mode, based on a display mode switching signal (Pa) from the outside. Detecting that the display mode switching signal (Pa) corresponding to the first display mode has changed to the display mode switching signal (Pa) corresponding to the second display mode during display in the first display mode change detection signal (C ₁₎ output detecting means (51) during said change detection signal (C ₁₎ a predetermined time after detecting the change of the display mode switching signal (Pa) based on, Discriminating means (52, TM, FF ₂ to which discriminates whether or not the display mode switching signal (Pa) corresponds to the second display mode and outputs a discrimination signal (PC).
FF ₄ ) and the display mode switching signal (Pa) until the predetermined time elapses after the change in the display mode switching signal (Pa) is detected based on the discrimination signal (PC).
The internal display mode switching signal (Pa ′) that is the same signal as the display mode switching signal corresponding to the first display mode is generated and output based on the above, and the display mode switching signal (Pa ′) is generated for the predetermined time. Pa) corresponds to the second display mode, the display mode switching signal (Pa) corresponding to the second display mode based on the display mode switching signal (Pa) after the lapse of the predetermined time. A display mode switching signal generating means (54) for generating and outputting an internal display mode switching signal (Pa ′) which is the same signal as
And is configured.

A sixth aspect of the present invention is a display control device for a display device capable of switching between two display modes, an interlaced display mode and a non-interlaced display mode, based on a display mode switching signal. When it is detected during display that the external display mode instruction signal corresponding to the first display mode has changed to the display mode instruction signal corresponding to the second display mode, the display mode is changed to the second display mode. Corresponding alternative display mode switching signal (Pa ")
A display mode switching signal generating means (54A) for generating
Be prepared and configured.

[0025]

According to the first aspect of the invention, the display mode switching signal (Pa) corresponding to the first display mode during display in the first display mode is changed to the display mode switching signal corresponding to the second display mode. Whether the display mode switching signal (Pa) corresponds to the second display mode for a predetermined time after detecting the change in the display mode switching signal (Pa) and detecting the change in the display mode switching signal (Pa). When the display mode switching signal (Pa) corresponds to the second display mode for a predetermined time, the display mode is switched to the second display mode.
It is possible to prevent the display mode from being erroneously changed due to the influence of temporary noise and the like, and it is possible to prevent a display abnormality such as vertical compression display of the screen due to the erroneous change of the display mode.

According to the second invention, the display mode switching signal (Pa) corresponding to the first display mode during the display in the first display mode is changed to the display mode switching signal (Pa) corresponding to the second display mode. ) Is detected, and it is determined whether or not the display mode switching signal (Pa) corresponds to the second display mode for a predetermined time after the change in the display mode switching signal (Pa) is detected. The same as the display mode switching signal (Pa) corresponding to the first display mode based on the display mode switching signal (Pa) until a predetermined time elapses after the change in the display mode switching signal (Pa) is detected. When the display mode switching signal (Pa) corresponds to the second display mode for a predetermined time, the internal display mode switching signal (Pa ′) that is a signal is generated and output, and the display mode is displayed after the predetermined time has elapsed. For switching signal (Pa) Based on this, an internal display mode switching signal (Pa ') that is the same signal as the display mode switching signal (Pa) corresponding to the second display mode is generated and output, so that a change in the display mode switching signal (Pa) is detected. Until a predetermined time elapses from the start, the internal display mode switching signal (Pa ') that is the same signal as the display mode switching signal (Pa) corresponding to the first display mode is used to display the display mode (change to the display mode before change detection). 1 display mode), and when the display mode switching signal (Pa) corresponds to the second display mode for a predetermined time, based on the display mode switching signal (Pa) after the predetermined time has elapsed. Based on an internal display mode switching signal (Pa ') that is the same signal as the display mode switching signal (Pa) corresponding to the second display mode, display is performed in the display mode after the change detection (second display mode).

Therefore, the display mode switching signal (Pa) changes again, that is, the display mode switching signal (Pa) corresponds to the original display mode until a predetermined time elapses after the change in the display mode switching signal (Pa) is detected. When it becomes, it is determined that the display mode switching is erroneously detected due to a temporary noise mixture or the like, and the first display mode before the change detection is retained. In addition, the display mode switching signal (Pa)
If the display mode corresponds to the second display mode, the display mode is switched to the second display mode based on the internal display mode switching signal (Pa ′) after a predetermined time has elapsed.

This prevents the display mode from being erroneously changed due to the influence of temporary noise, etc., and prevents display abnormalities such as vertical compression display of the screen due to the erroneous change of the display mode. It becomes possible to perform stable screen display.

According to the third invention, the display mode instruction signal from the outside corresponding to the first display mode corresponds to the second display mode during the display in the first display mode. When the display mode switching signal corresponding to the second display mode is generated when it is detected that the display mode switching signal is unstable due to some reason, the display mode switching signal is not stable. The stable display can be done with.

According to the fourth invention, the detection means (51)
Is displayed in the first display mode, the
The corresponding display mode switching signal (Pa) is the second display mode.
To the display mode switching signal (Pa) corresponding to
That the change detection signal (C ₁) Is the state determination means (5
2, TM, FF₂~ FF_Four) Is output.

State discrimination means (52, TM, FF _{2 to} FF
₄ ) indicates that the display mode switching signal (Pa) is in the second display mode for a predetermined time after detecting the change in the display mode switching signal (Pa) based on the input change detection signal (C ₁ ). It is determined whether or not it is compatible and a discrimination signal (PC) is output.

As a result, the display mode switching means (54)
Switches the display mode to the second display mode based on the determination signal (PC) when the display mode switching signal corresponds to the second display mode for a predetermined time.

Therefore, it is possible to prevent the display mode from being erroneously changed due to the influence of a temporary noise or the like, and prevent the display abnormality such as the vertical compression display of the screen due to the erroneous change of the display mode. it can.

According to the fifth invention, the detection means (51)
Detects that the display mode switching signal (Pa) corresponding to the first display mode has changed to the display mode switching signal (Pa) corresponding to the second display mode during the display in the first display mode. The detection signal (C ₁ ) is output.

Discriminating means (52, TM, FF _{2 to} FF ₄ )
Indicates whether the display mode switching signal (Pa) corresponds to the second display mode for a predetermined time after detecting the change of the display mode switching signal (Pa) based on the change detection signal (C ₁ ). Then, the discrimination signal (PC) is outputted to the display mode switching signal generating means (54).

As a result, the display mode switching signal generating means (54) detects the change of the display mode switching signal (Pa) based on the discrimination signal (PC) and continues until the predetermined time elapses. Based on (Pa), an internal display mode switching signal (Pa ') which is the same signal as the display mode switching signal corresponding to the first display mode is generated and output, and the display mode switching signal (Pa Pa) corresponds to the second display mode, the display mode switching signal (P) corresponding to the second display mode is generated based on the display mode switching signal (Pa) after a predetermined time has elapsed.
Internal display mode switching signal (P) which is the same signal as a)
a ') is generated and output.

Therefore, if the display mode switching is performed based on the internal display mode switching signal (Pa ') instead of the display mode switching signal (Pa), a predetermined time is elapsed after the change of the display mode switching signal (Pa) is detected. When the display mode switching signal (Pa) changes again until the time elapses, that is, when it corresponds to the original display mode, the display mode switching may be erroneously detected due to temporary mixing of noise. It can be determined that there is, and the display mode before the change detection is retained. Further, if the display mode switching signal (Pa) corresponds to the second display mode for a predetermined time, the display mode is switched based on the internal display mode switching signal (Pa ') after the predetermined time has elapsed. Becomes

This prevents the display mode from being erroneously changed due to the influence of temporary noise or the like, and prevents the display abnormality such as the screen vertical compression display due to the erroneous change of the display mode. It becomes possible to perform stable screen display.

According to the sixth invention, the display mode switching signal generating means (54A) receives the second display mode instruction signal corresponding to the first display mode during the display in the first display mode. When it is detected that the display mode instruction signal corresponding to the display mode is changed, the alternative display mode switching signal (Pa ″) corresponding to the second display mode is generated.

Therefore, the alternative display mode switching signal (Pa)
If the display mode switching signal is not stable due to some reason, stable display can be performed in any of the display modes by performing the display based on the above.

[0041]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described with reference to the drawings. First Embodiment FIG. 1 shows a schematic block diagram of a display system having a display control circuit according to a first embodiment of the present invention.

The display system 100 is roughly classified into NT.
A signal source 10 that outputs a display signal such as an SC video signal or an analog RGB signal, an interface control unit 20 that performs an interface operation for transmitting the display signal to a display control unit 30 in a subsequent stage, and an interface control A display control unit 30 that performs display control based on various display data output from the unit 20 and a display unit 40 that performs various displays under the control of the display control unit 30 are configured.

As the signal source 10, for example, a video device 11 such as a video tape recorder which outputs a video signal S _V such as an NTSC composite video signal in the interlaced display mode, and a vertical sync signal V in the non-interlaced display mode. _sync , horizontal sync signal H _sync and analog RGB
There is a personal computer 12 that outputs the signal S _RGB .

The interface controller 20 includes a sync signal separation circuit for separating the sync signal from the video signal S _V and Y.
A vertical sync signal V
_S , a horizontal synchronizing signal H _S, and a separation circuit 21 for outputting a luminance signal Y and a chrominance signal C separated by a parity signal Pa and a Y / C separation circuit representing either an interlaced display mode or a non-interlaced display mode, decodes the luminance signal Y and chrominance signal C, 'a decoder 22 for outputting an analog RGB signal S _RGB or analog RGB signal S _RGB' analog RGB signal S _RGB performs analog / digital conversion of the a / D converter circuit and γ A that has a γ correction circuit that performs correction and outputs RGB data D _{RG B}
Based on the / D conversion / γ correction circuit 23 and the parity signal Pa, the vertical synchronizing signal V _S and the horizontal synchronizing signal H _S from the separating circuit 21 or the vertical synchronizing signal V _sync and the horizontal synchronizing signal H _sync from the personal computer 12 are _detected . An output selection circuit 24 which selectively outputs one of them as a vertical synchronization signal V _sync ′ and a horizontal synchronization signal H _sync ′ and outputs the parity signal Pa as it is.

Further, the interface control unit 20 is
Display blank signal BLNK to prohibit output of the surface
It is output to the control unit 30. The display control unit 30 is a parite.
Signal Pa to detect and set the display mode.
With a parity signal detection determination circuit unit 31A for
Vertical sync signal V _sync', Parity signal Pa, horizontal same
Term signal H_sync', Blank signal BLNK and RGB data
TA D_RGBIs input, and a control circuit 31 that performs display control,
Plasma display panel, etc. under the control of the control circuit 31.
And a drive circuit 32 for driving the display section of
Has been.

FIG. 2 shows a parity signal detection determination circuit section 31A.
The detailed configuration of is shown. Parity signal detection determination circuit unit 31A
Is a clock generation circuit 50 that generates and outputs the first clock signal CLK ₁ and the second clock signal CLK ₂ based on the vertical synchronization signal V _sync ′, and the first clock signal CLK ₁
The first pre-stage register RE that takes in and holds the parity signal Pa and outputs it as the first parity data A ₁ based on
And G _1-0, based on the first clock signal CLK _1, the first
A _first rear-stage register REG _1-1 that takes in and holds the parity data A ₁ and outputs it as second parity data A ₂ ;
Based on the first clock signal CLK _1, the second parity data A ₂ uptake and retention, and second pre-register REG _2-0 for outputting a third parity data B _1, first on the basis of the first clock signal CLK ₁ The second rear-stage register REG _2-1 that captures and holds the 3rd parity data B ₁ and outputs it as the 4th parity data B ₂ and the 1st to 4th parity data are input, and the 1st parity data A ₁ and the 2nd parity A first parity data group A composed of data A ₂ ;
The second parity data group B composed of the third parity data B ₁ and the fourth parity data B ₂ is compared, and when the first parity data group A and the second parity data group are equal, the “H” level is set. a first comparison result the first comparator 51 which outputs a signal C _1, the first comparison result takes in signals C ₁ based on the second clock signal CLK _2, its is an inverted signal inverted first comparison result output signal XC ₁ A first flip-flop circuit FF ₁ and a buffer circuit BUF that outputs a third clock signal CLK ₃ based on an inverted first comparison result signal XC ₁ and a timer signal T from a timer TM described later.
_{Based on 1} and the third clock signal CLK ₃ , the third parity register REG _3-0 that captures and holds the first parity data A ₁ and outputs it as the fifth parity data D ₁ and the third clock signal CLK ₃ based second parity data a ₂ capture and hold, a third rear stage register REG _3-1 for outputting a sixth parity data D _2, first parity consisting of first parity data a ₁ and the second parity data a ₂ Data group A, fifth parity data D ₁ and sixth parity data
Third parity data group D consisting of parity data D ₂
And a second comparator 52 that outputs a second comparison result signal C ₂ that becomes “H” level when the first parity data group A and the third parity data group D are equal, and the second comparison result. An inverter 53 that inverts the signal C ₂ and outputs the inverted second comparison result signal XC ₂ , and a third clock signal CLK
A timer TM that outputs a timer signal T based on ₃ , and 2
A delay circuit DL including a stage inverter and delaying the timer signal T for a predetermined time and outputting the delayed timer signal DT;
A second flip-flop circuit FF ₂ for taking in the inverted second comparison result signal XC ₂ based on the second clock signal CLK ₂ and the timer signal T, and further outputting the inverted second comparison result signal C ₂ ; The second comparison result signal C ₂ from the 2 flip-flop circuit is used as a reset input, and the delay timer signal DT from the delay circuit DL is used as a set input.
The second comparison result signal C ₂ is “H” and the timer signal T is “L”
"L" is output from the output terminal when the second comparison result signal C ₂ is "L", the third flip-flop circuit FF output is "H" from the output terminal when the timer signal T is "H"
₃ and the output of the third flip-flop circuit FF ₃ , the parity signal Pa input to the parity signal detection determination circuit based on the timer signal T and the delay timer signal DT, is output to the parity generation circuit 54 described later as the parity signal Pa ′. Or a parity switching signal PC for selecting whether to output the generated parity signal generated by the parity generation circuit 54 as the parity signal Pa ′.
The flip-flop circuit FF ₄ and the display system 10
When the operating power is supplied to 0, the power supply signal POR which becomes the “H” level is input, and when the power supply signal DPOR is the “H” level, the input parity signal based on the parity switching signal PC. Pa is the parity signal P
or a parity generation circuit 54 that outputs the generated parity signal generated by itself as a parity signal Pa ′.

FIG. 3 shows a detailed configuration of the parity generation circuit 54.
Show. The parity generation circuit 54 uses the display system 10
When the operating power is supplied to 0, the "H" level is always
A power signal POR that becomes a bell is input and a two-stage invertor
Output the delayed power supply signal POR after delaying for a predetermined time.
Delay circuit DL₂And power signal POR and delayed power signal
Based on the signal DPOR, a pulse with a predetermined pulse width is generated when the power is turned on.
Flip-flop circuit FF that outputs a digital signal_FiveWhen,
The fifth flip-flop circuit FF is connected to the first input terminal._FiveOut of
Force signal is input and the parity signal Pa is input to the second input terminal.
Is input, the logical product of the₁
1st AND circuit AND which outputs₁And the first input terminal
The fifth flip-flop circuit FF _FiveOutput signal of
The power signal POR is input to the second input terminal,
The logical product is taken and the second AND signal AD is obtained.₂Output 2A
ND circuit AND₂And the high-potential power supply V to the data terminal D_CC
(= “H” level) is connected to the clock terminal
ND signal AD₁Is input and the second AND signal is input to the clear terminal.
No. AD₂Flip-flop circuit FF to which is input₆
, And the parity switching signal PC is input, and its inversion signal
An inverter that outputs a certain inverted parity switching signal XPC
55 and a sixth flip-flop circuit FF₆Output signal of
And the inverted parity switching signal XP is input to the second input terminal.
C is input, and the logical product of them is calculated to obtain the third AND signal A
D₃Output as a third AND circuit AND₃And the J terminal
And high-potential-side power supply V to the K terminal_CCConnected to the clock end
3rd AND signal AD to child₃Is input and power is supplied to the clear terminal.
The seventh flip-flop circuit F to which the source signal POR is input
F₇And a seventh flip-flop circuit F is connected to the first input terminal.
F₇Output signal is input and the power supply signal is input to the second input terminal.
POR is input, and the logical product is taken and the fourth AND signal is received.
No. AD_Four4th AND circuit AND output as_FourAnd the
High-potential-side power supply V_CCConnected to the clock end
The parity signal Pa is input to the child, and the fourth terminal A is input to the clear terminal.
ND signal AD_FourEighth flip-flop circuit to which is input
FF₈And the 8th flip-flop circuit FF to the J terminal₈of
The output signal is input and the high potential side power supply V is connected to the K terminal._CCConnected
And the vertical synchronizing signal V is applied to the clock terminal._sync'Is entered
The power signal POR is input to the clear terminal,
9th flip-flop circuit FF for outputting the signal Pa '
₉And are provided.

Here, the operation of the parity generation circuit 54 when the display system 100 is powered on will be described separately in the interlace mode (FIG. 4) and the non-interlace mode (FIG. 5).

FIG. 4 shows an operation timing chart of the parity generation circuit 54 in the interlace mode. When the power is turned on, as shown in FIG. 4B, the fifth flip-flop circuit FF ₅ outputs a pulse signal which is at the “H” level for a certain period.

While the pulse signal of the fifth flip-flop circuit FF ₅ is at "H" level, the interface controller 20 (see FIG. 1) toggles the interlace mode as shown in FIG. 4 (c). Parity signal Pa
Is input, the output of the sixth flip-flop circuit FF ₆ is latched at the “L” level as shown in FIG.

After that, the fifth flip-flop circuit FF ₅
It becomes the output signal is "L" level, the sixth flip-flop circuit FF ₆ becomes cleared again "H" level. The output signal of the sixth flip-flop circuit FF ₆ is input as the clock signal of the seventh flip-flop circuit FF ₇ via the _third AND circuit AND ₃ .

As a result, the seventh flip-flop circuit FF
The output signal of ₇ is inverted from the "L" level to the "H" level as shown in FIG. 4 (h), until the parity switching signal PC shown in FIG. 4 (f) becomes the "H" level. The state (“H” level) is maintained.

Seventh flip-flop FF₇Output of
When it goes to "H" level, the fourth AND circuit AND_FourOutput
4th AND signal AD which is a signal_FourIs also "H" level
And the eighth flip-flop circuit FF₈Is cleared,
8 flip-flop circuit FF₈The output signal of
As shown in (i), the power input to the clock terminal is
From the “L” level to “H” at the rising edge of the priority signal Pa
Switch to the level. And the eighth flip-flop circuit
FF₈Output signal of the seventh flip-flop circuit F
F ₇Until the clear signal input from is at "L" level.
Then, the state (“H” level) is maintained.
As a result, the ninth flip-flop FF₉Input of J terminal
Next, the seventh flip-flop circuit FF₇Entered from
"H" level until the clear signal becomes "L" level
Therefore, the output signal of the ninth flip-flop is maintained.
The parity signal Pa ', which is a signal, is the eighth flip-flop.
FF₈To the clock terminal while the output signal of is "H" level.
Vertical sync signal V input_sync’Synchronize and toggle
Will be kicked.

Therefore, the control circuit 31 operates based on the parity signal Pa ', so that the display section 40 displays images in the interlaced mode via the drive circuit 32.

After that, at time t ₁ in FIG. 4, when the parity switching signal PC becomes “H” level, the _third AND signal AD ₃ output from the _third AND circuit AND ₃ becomes “L” level, and the parity switching signal. the 3AND signal AD3 the PC becomes "L" level is "L" → "H" level and the output signal of the seventh flip-flop circuit FF ₇ at the rising (time t ₂₎ is inverted to "H" level and Become.

As a result, the eighth flip-flop circuit F
In F ₈ , since the output of the seventh flip-flop circuit FF ₇ is at “L” level, the _fourth AND circuit AND ₄
It becomes the 4AND signal AD ₄ is "L" level which is the output signal of the clear terminal changes to "L" level until the output of the seventh flip-flop circuit FF ₇ becomes "H" level "L" level Will be maintained (see FIG. 5 (h)).

As a result, the input to the J terminal of the ninth flip-flop FF ₉ also goes to the seventh flip-flop circuit FF ₇ next.
Until the clear signal input from becomes "H" level.
Since the parity signal Pa ′, which is the output signal of the ninth flip-flop, is maintained at the “L” level, the output signal of the eighth flip-flop FF ₈ is at the “L” level.
It is fixed at "L" level.

Therefore, the control circuit 31 operates on the basis of the parity signal Pa ', so that the display section 40 performs the display in the non-interlaced mode after the time t ₂ via the drive circuit 32. .

FIG. 5 shows an operation timing chart of the parity generation circuit 54 in the non-interlaced mode. When the power is turned on, as shown in FIG. 5B, the fifth flip-flop circuit FF ₅ outputs a pulse signal which is at the “H” level for a certain period.

In the non-interlaced mode,
The pulse signal of the fifth flip-flop circuit FF5 is "H"
During the level period, the interface control unit 20 (see FIG.
4), the toggled parity signal Pa corresponding to the interlaced mode as shown in FIG. 4C is not input, so the output of the sixth flip-flop circuit FF ₆ remains at the “H” level ( See FIG. 5 (e). As a result, the _third AND circuit which is the output of the _third AND circuit AND ₃
The signal AD ₃ remains at the “H” level (see FIG. 5G) and is not input to the clock terminal of the seventh flip-flop circuit FF ₇ as a clock signal. Therefore, the output of the seventh flip-flop circuit FF ₇ is As shown in FIG. 5F, the "L" level is maintained as in the initial state until the parity switching signal PC becomes "H" level.

[0061] On the other hand, in the eighth flip-flop circuit FF _8, since the seventh output of the flip-flop circuit FF ₇ is at "L" level, the 4AND signal AD ₄ is the output signal of the 4AND circuit the AND ₄ is " The L level is maintained, the clear terminal becomes the “L” level, and the “L” level is maintained until the output of the seventh flip-flop circuit FF ₇ becomes the “H” level (FIG. 5 (h)). reference).

As a result, the ninth flip-flop circuit FF
The input to the J terminal of ₉ is also the 7th flip-flop circuit F
The "L" level is maintained until the clear signal input from F ₇ becomes "H" level, and the parity signal P which is the output signal of the ninth flip-flop circuit FF ₉ is output.
a 'is between the output signal is "L" level of the eighth flip flop FF _8, a fixed at "L" level.

Therefore, the control circuit 31 operates on the basis of the parity signal Pa ', so that the display section 40 displays images in the non-interlaced mode via the drive circuit 32.

Thereafter, at time t ₁ 'in FIG. 5, when the parity switching signal PC becomes "H" level, the third AND
The _third AND signal AD ₃ output from the circuit AND ₃ becomes “L” level, and at the time t ₂ ′, the switching signal PC
There "H" → "L", and the the first 3AND signal AD ₃ becomes "L" → "H", the seventh flip-flop circuit F
The output signal of F ₇ is inverted and becomes "H" level.

As a result, the fourth AND signal AD ₄ which is the output signal of the _fourth AND circuit AND ₄ also becomes the “H” level, the clear of the eighth flip-flop circuit FF ₈ is deleted, and the output of the eighth flip-flop circuit FF ₈ is deleted. The signal switches from the "L" level to the "H" level at the rise of the parity signal Pa input to the clock terminal, as shown in FIG. 4 (i). The output signal of the eighth flip-flop circuit FF ₈ is then up to the seventh clear signal is input from the flip-flop circuit FF ₇ becomes "L" level, and to maintain its state ( "H" level) Become.

As a result, the ninth flip-flop circuit FF
The input to the J terminal of ₉ is also the 7th flip-flop circuit F
Until the clear signal input from F ₇ becomes “L” level, the “H” level is maintained, and the parity signal P which is the output signal of the ninth flip-flop circuit FF ₉
a 'is 8 between the output signal is "H" level of the flip-flop FF _8, a vertical synchronization signal V _sync that is input to the clock terminal' and thus continue to toggle in synchronism with.

Therefore, the control circuit 31 operates on the basis of the parity signal Pa ', so that the display section 40 performs the display in the interlace mode after the time t ₁ ' in FIG. 5 via the drive circuit 32. It will be.

As described above, the parity signal Pa 'which is the output of the ninth flip-flop circuit FF ₉ is the toggle signal corresponding to the interlace mode every time the parity switching signal PC becomes "H" level. And the signal fixed to the "L" level corresponding to the non-interlaced mode.

The ninth flip-flop circuit FF
₉ is outputs a 'parity signal Pa is a parity signal generated based on the' parity signal Pa and the vertical synchronizing signal V _sync input from the interface control unit 20, compares after the state change detecting parity signal Pa Even if the parity signal Pa changes during the period until the next parity switching signal PC becomes “H” level including the period,
Since the stable parity signal Pa ′ can be output without being affected by the influence, no display abnormality occurs.

Next, the general operation of the control circuit 31 will be described with reference to FIGS. 6 and 7. In this case, even if the control circuit 31 on the receiving side changes the parity signal Pa, if the change does not continue for three frame periods or more, the case is assumed to be treated as unchanged. To do.

FIG. 6 shows a timing chart when the control circuit 31 on the receiving side erroneously detects the parity signal Pa due to the inclusion of noise or the like. In this case, the initial display mode is the interlaced mode.

At time t ₁₀ , even though the parity signal Pa from the interface control section 20 on the transmission side is at the “H” level (see FIG. 6B), the control circuit 31 side due to noise and the like. At the parity detection timing (see FIG. 6 (d)), if the receiving side detects the "L" level as the parity signal, the control circuit 31
Since the same “L” level as the parity signal level at the previous parity detection timing is continuous, it is detected that there is a possibility of changing to the non-interlaced mode.

However, the control circuit 31 sets the above-mentioned parity switching signal PC to "L" level, that is, the parity signal Pa in the parity detection determination circuit section 31A.
Is the same as that in which the parity signal Pa has not changed, and the same parity signal Pa ′ as before the change in the parity signal Pa is detected is continuously output to the parity generation circuit 54.

At the same time, the control circuit 31 controls the timer TM.
3 is started and the parity signal Pa changes, and then 3
When the frame elapses, it is determined whether or not the changed state is retained.

In FIG. 6, two cycles from the timing (= time t ₁₀ ) at which the change of the parity signal Pa is detected, that is, before the change after two frame display time has elapsed in the interlace mode (time t ₁₁ ). Since the state has returned to the above state, the control circuit 31 determines that it is an erroneous detection due to a temporary cause, and continues the interlaced display as it is.

FIG. 7 shows a timing chart when the control circuit 31 on the receiving side correctly detects a change in the parity signal Pa. In this case, the initial display mode is the interlaced mode.

At time t ₁₂ , the parity signal Pa from the interface control unit 20 on the transmission side is switched to the “L” level (see FIG. 7B), and the control circuit 31 also has the parity detection timing (FIG. 7D). It is assumed that it has been detected that the parity signal has changed to the “L” level.

As a result, the control circuit 31 detects that the parity signal level ("H" level) at the previous parity detection timing is different and therefore the mode may be changed to the non-interlaced mode.

However, also in this case, the control circuit 31 controls the parity detection determination circuit section 31A by
The parity switching signal PC described above is set to the “L” level, that is, the same as when the parity signal Pa does not change, and the same parity signal Pa ′ as before the change in the parity signal is detected (corresponding to the interlace mode). Is continuously output to the parity generation circuit 54.

At the same time, the control circuit 31 causes the timer TM
3 is started and the parity signal Pa changes, and then 3
When the frame elapses, it is determined whether or not the changed state is retained.

In FIG. 7, three cycles from the timing (= time t ₁₂ ) at which the change in the parity signal Pa is detected, that is, even after a lapse of 3 frame display time in the interlaced mode (time t ₁₃ ), Since it remains changed, the control circuit 31 determines that the display mode has been changed, and switches the display mode to the non-interlaced mode at time t ₁₄ .

In this case, the display mode changes 4 cycles after the switching is actually instructed, that is, after 4 frames have passed in the interlaced mode, but since it is a short time, the display is not changed. Even if it goes, it does not matter in practice.

Next, the detailed operation of the control circuit 31 will be described with reference to FIGS.
And FIG. 9 will be described. In this case, even if the control circuit 31 on the receiving side changes the parity signal Pa, if the change does not continue for three frame periods or more, the case is assumed to be treated as unchanged. To do.

FIG. 8 shows a detailed timing chart when the control circuit 31 on the receiving side erroneously detects the parity signal Pa due to the inclusion of noise or the like. In this case, the initial display mode is the interlaced mode.

First, the parity signal detection determination circuit section 31A
The clock generation circuit 50 of FIG.
vertical sync signal V based on _sync '(see FIG. 8A).
The first clock signal CLK ₁ (FIG. 8) having the same cycle as _sync '
(See (c)) and the second clock signal C having a double cycle (frame cycle in interlace mode) of the vertical sync signal V _sync '.
LK ₂ (see FIG. 8H) is generated.

The first clock signal CLK ₁ is supplied to the first front stage register REG _1-0 , the first rear stage register REG _1-1 ,
Second front stage register REG _2-0 and second rear stage register RE
Is output to G _2-1, the second clock signal CLK ₂ is output to the first clock terminal of the flip-flop circuit FF ₁ and the second flip-flop circuit FF _2. In this case, the first front-stage register REG _1-0 and the first rear-stage register R
The EG _1-1 , the second front-stage register REG _2-0 and the second rear-stage register REG _2-1 function as a shift register as a whole, and based on the first clock signal CLK ₁ ,
Parity signal Pa captured by the previous-stage register REG _1-0
(See FIG. 8B) is the first front-stage register REG _1-0 →
First rear stage register REG _1-1 → Second front stage register REG
_2-0 → Transfers in the order of second post-stage register REG _2-1 .

Time t₀At the first clock signal CL
K₁At the timing corresponding to
_1-0= “L” (see FIG. 8D), first post-stage register R
EG _1-1= “H” (see FIG. 8 (e)), second front-stage resist
REG_2-0= “L” (see FIG. 8F), the second rear stage
Dista REG_2-1= “H” (see FIG. 8 (g))
Then, the second clock signal CLK₂Based on time t₁
In the first comparator 51, the first comparator 51
_1-0And the first post-stage register REG_1-1Is the retained data of
First parity data group A (= “L” + “H”) and
2 Previous register REG_2-0And the second rear register REG
_2-1Second parity data group B (=
"L" + "H") are compared, and since A = B, the first comparison signal C₁= "H" level
(See FIG. 8 (i)).

Similarly, at time t ₂ , the first comparator 51 also causes the first parity data group A (= the data held in the first front-stage register REG _1-0 and the first rear-stage register REG _1-1 to be stored). "L" + "H") and second pre-stage register R
EG _2-0 and the second parity data group B (= “L” + “H”) held by the second rear-stage register REG _2-1 are compared. Since A = B, the first comparison signal remains unchanged. C ₁ = “H” level.

By the way, at time t ₃ , although the interface section 20 on the transmission side is transmitting the “H” level parity signal, the parity signal Pa is set to “L” in the control circuit 31 due to noise mixing. If the level is detected, the first pre-stage register REG _1-0 =
"L", first post-stage register REG _1-1 = "L", second pre-stage register REG _2-0 = "H" (see FIG. 8 (f)), second post-stage register REG _2-1 = "L" And the comparator 51
The output (= C ₁ ) of " ₁ " becomes "L".

Further, at time t ₄ , the first front stage register REG _1-0 = “L”, the first rear stage register REG
_1-1 = "L", second pre-stage register REG _2-0 = "L"
(See FIG. 8 (f)), second post-stage register REG _2-1 =
It becomes "H".

Therefore, the first comparator 51 determines that the first parity data group A = “L” + “L”, the second parity data group B.
The result of comparing “=“ L ”+“ H ”is A ≠ B, so the first comparison signal C ₁ =“ L ”level,
As a result, the output signal of the first flip-flop circuit FF ₁ becomes the “H” level (see FIG. 8 (j)), and the third clock signal CLK which is the output signal of the buffer circuit BUF ₁ is generated.
₃ becomes "H" level (see FIG. 8 (k)), and the control circuit 31 detects that the parity signal Pa has changed.

Since the third clock signal CLK ₃ is set to the “H” level, the third pre-stage register REG _3-0
The output signal A ₁ of the first pre-register REG _1-0 (=
"L") and the third rear register REG _3-1 is the first
The output signal A ₂ (= “L”) of the rear-stage register REG _1-1 is taken in, that is, the third front-stage register REG _3-0 and the third rear-stage register REG _3-1 are respectively the parity signal P.
The value of the parity signal Pa at the time of a change and immediately before the change is acquired and held. At this time, the third pre-stage register RE
G _3-0 = “L” (see FIG. 8 (l)) and the third rear-stage register REG _3-1 = “L” (see FIG. 8 (m)).

Furthermore, at time t ₄ , the output signals A ₁ and A of the first front stage register REG _1-0 , the first rear stage register REG _1-1 , the third front stage register REG _3-0 and the third rear stage register REG _{3-1. 2} , D ₁ and D ₂ are input to the second comparator 52.

As a result, the second comparator 52 compares the first parity data group A = "L" + "L" and the third parity data group D = "L" + "L", and A = D Therefore, the second comparison signal C ₂ becomes “H” level (see FIG. 8 (n)).

In parallel with this, the third clock signal CLK
_{When 3} goes to "H" level, timer TM
Counting is started, and the timer signal T is set to the “H” level during the counting, that is, until three cycles have elapsed after the change in the parity signal Pa was detected (see FIG. 8O).

As a result, the delay circuit DL outputs the delayed timer signal DT obtained by delaying the output timer signal T by a predetermined time, and at the time t ₅ , the set input terminal S of the third flip-flop circuit FF ₃ is outputted. Is input with the delay timer signal DT of "H" level (see FIG. 8 (q)).
The output of the second flip-flop circuit FF ₂ is held at the “H” level because the timer signal T is cleared during the “L” period, but is cleared during the timer signal T is at the “H” level. There is.

At time t ₆ , the second comparator 52 compares the first parity data group A = “L” + “L” and the third parity data group D = “L” + “L” with the result: Since A = D ₂ , the output of the second flip-flop circuit FF ₂ remains at “H” level.

Similarly, at time t ₇ , the second comparator 52 compares the first parity data group A = “L” + “L” and the third parity data group D = “L” + “L”. As a result, since A = D, the second flip-flop circuit FF remains the same.
The output of ₂ remains "H" level.

After that, at time t ₈ , the interface unit 20 on the transmission side sends a parity signal of "H" level, and the control circuit 31 correctly detects the parity signal Pa at "H" level. Register R
EG _1-0 = "H", first post-stage register REG _1-1 =
It becomes "L".

As a result, at time t ₉ which is the comparison timing of the second comparator 52, the first front-stage register REG
_1-0 = "L", first post-stage register REG _1-1 = "H",
The third front-stage register REG _3-0 = “L” and the third rear-stage register REG _3-1 = “L”.

Therefore, the second comparator 52 determines that the first parity data group A = “L” + “H”, the third parity data group D.
Since the result of comparing “= L” + “L” is A ≠ D, the output of the second flip-flop circuit FF ₂ becomes “L” and the output of the third flip-flop circuit FF ₃ also becomes “L”. . Therefore, at the rise of the timer output T, the parity switching signal PC, which is the output from the fourth flip-flop circuit FF ₄ , remains at “L” level, and the interlaced display continues.

As described above, even if the parity signal is erroneously detected due to temporary noise mixing or the like, the display mode is not immediately switched, so that stable display can be performed.

Next, FIG. 9 shows a detailed timing chart when the control circuit 31 on the receiving side correctly detects a change in the parity signal Pa. In this case, the initial display mode is the interlaced mode.

First, the parity signal detection determination circuit section 31A
The clock generation circuit 50 of FIG.
vertical sync signal V based on _sync '(see FIG. 9A).
The first clock signal CLK ₁ (FIG. 9) having the same cycle as _sync '
(See (c)) and the second clock signal C having a double cycle (frame cycle in interlace mode) of the vertical sync signal V _sync '.
LK ₂ (see FIG. 9H) is generated.

The first clock signal CLK ₁ is supplied to the first front stage register REG _1-0 , the first rear stage register REG _1-1 ,
Second front stage register REG _2-0 and second rear stage register RE
Is output to G _2-1, the second clock signal CLK ₂ is output to the first clock terminal of the flip-flop circuit FF ₁ and the second flip-flop circuit FF _2.

Time t_TenAt the first clock signal CL
K₁At the timing corresponding to
_1-0= “L” (see FIG. 9D), first post-stage register R
EG _1-1= “H” (see FIG. 9 (e)), second front-stage resist
REG_2-0= “L” (see FIG. 9 (f)), second rear stage
Dista REG_2-1= “H” (see FIG. 9 (g))
Then, the second clock signal CLK₂Based on time t₁₁
In the first comparator 51, the first comparator 51
_1-0And the first post-stage register REG_1-1Is the retained data of
First parity data group A (= “L” + “H”) and
2 Previous register REG_2-0And the second rear register REG
_2-1Second parity data group B (=
"L" + "H") are compared, and since A = B, the first comparison signal C₁= "H" level
(See FIG. 9 (i)).

Similarly, also at time t ₁₂ , the first comparator 51 has the first parity data group A (= the data held in the first front stage register REG _1-0 and the first rear stage register REG _1-1 ). "L" + "H") and second pre-stage register R
EG _2-0 and the second parity data group B (= “L” + “H”) held by the second rear-stage register REG _2-1 are compared. Since A = B, the first comparison signal remains unchanged. C ₁ = “H” level.

By the way, time t₁₃At the sending side
In the interface unit 20 that uses
Send "L" level parity signal to enter race mode
If so, the parity signal Pa in the control circuit 31
Also becomes "L" level, and the first front-stage register REG_1-0=
"L", first post-stage register REG_1-1= "L", before the second
Stage register REG_2-0= “H” (see FIG. 9 (f)),
2 Second stage register REG _2-1= “L”, and the comparator 51
Output (= C₁) Becomes “L”.

Further, at time t ₁₄ , the first front stage register REG _1-0 = “L”, the first rear stage register REG
_1-1 = "L", second pre-stage register REG _2-0 = "L"
(See FIG. 9 (f)), second rear-stage register REG _2-1 =
It becomes "H".

Therefore, the first comparator 51 determines that the first parity data group A = “L” + “L”, the second parity data group B.
The result of comparing “=“ L ”+“ H ”is A ≠ B, so the first comparison signal C ₁ =“ L ”level,
As a result, the output signal of the first flip-flop circuit FF ₁ becomes the “H” level (see FIG. 8 (j)), and the third clock signal CLK which is the output signal of the buffer circuit BUF ₁ is generated.
₃ becomes "H" level (see FIG. 9 (k)), and the control circuit 31 detects that the parity signal Pa has changed.

Since the third clock signal CLK ₃ becomes the “H” level, the third pre-stage register REG _3-0
The output signal A ₁ of the first pre-register REG _1-0 (=
"L") and the third rear register REG _3-1 is the first
The output signal A ₂ (= “L”) of the rear-stage register REG _1-1 is taken in, that is, the third front-stage register REG _3-0 and the third rear-stage register REG _3-1 are respectively the parity signal P.
The value of the parity signal Pa at the time of a change and immediately before the change is acquired and held. At this time, the third pre-stage register RE
G _3-0 = “L” (see FIG. 9 (l)) and the third rear-stage register REG _3-1 = “L” (see FIG. 9 (m)).

Further, at time t ₁₄ , the output signals A ₁ and A of the first front stage register REG _1-0 , the first rear stage register REG _1-1 , the third front stage register REG _3-0 and the third rear stage register REG _{3-1. 2} , D ₁ and D ₂ are input to the second comparator 52.

As a result, the second comparator 52 compares the first parity data group A = “L” + “L” and the third parity data group D = “L” + “L”, and A = D Therefore, the second comparison signal C ₁ becomes “H” level (see FIG. 9 (n)).

In parallel with this, the third clock signal CLK
_{When 3} goes to "H" level, timer TM
Counting is started and the timer signal T is set to the “H” level during the counting, that is, until three cycles have elapsed after the change in the parity signal Pa was detected (see FIG. 9 (o)).

As a result, the delay circuit DL outputs the delayed timer signal DT obtained by delaying the output timer signal T by a predetermined time, and outputs the delayed timer signal DT to the set input terminal S of the third flip-flop circuit FF ₃ at time t ₁₅ . Is input with the delay timer signal DT of "H" level (see FIG. 9 (q)).
The output of the second flip-flop circuit FF ₂ is held at “H” level because the timer signal T is cleared during the “L” period, but is cleared during the timer signal T is “H” period.

At time t ₁₆ , the second comparator 52 is again activated.
However, the result of comparing the first parity data group A = “L” + “L” and the third parity data group D = “L” + “L” is A = D, so the second flip-flop circuit FF The output of ₂ remains "H" level.

Similarly, also at time t ₁₇ , the second comparator 52 compares the first parity data group A = “L” + “L” and the third parity data group D = “L” + “L”. As a result, since A = D, the second flip-flop circuit FF remains unchanged.
The output of ₂ remains "H" level.

Similarly, at time t ₁₈ , the second comparator 52 compares the first parity data group A = “L” + “L” and the third parity data group D = “L” + “L”. However, since A = D, the second flip-flop circuit FF remains the same.
The output of ₂ remains "H" level.

At this time, the first front-stage register REG _1-0 =
"L", the first second-stage register REG _{1- 1} = "L", the third front register REG _3-0 = "L", the third subsequent register RE
G _{3- 1} = becomes "L".

Therefore, the second comparator 52 determines that the first parity data group A = “L” + “L”, the third parity data group D.
Since the result of comparing “=“ L ”+“ L ”is A = D, the output of the second flip-flop circuit FF ₂ remains“ H ”and the output of the third flip-flop circuit FF ₃ also outputs“ H ”. “It remains. Therefore, during the period from the rise of the timer signal T, which is the output of the timer, to the rise of the delayed timer signal DT, the "H" level pulse is output from the fourth flip-flop circuit FF _4, so that at time t ₁₉ , the control circuit parity switch signal PC output becomes "H" level, the display mode at time t ₂₀ is to switch to the non-interlaced display.

As described above, even if the parity signal is switched, the display mode is switched after detecting that the parity signal is switched surely, so that stable display can be performed. Second Embodiment FIG. 10 shows a detailed block diagram of the parity generation circuit 54A of the second embodiment. 10, the difference from the parity generation circuit 54 of FIG. 3 is that the parity generation circuit 54 prevents abnormal display due to temporary false detection of the parity signal, but is forced when abnormalities of the parity signal continue. That is, a parity signal is generated to prevent abnormal display.

The parity generation circuit 54A has a J terminal and a K terminal.
Higher voltage power supply V _CC is connected to the terminal, the vertical synchronization signal V _sync 'input to the clock terminal, a flip-flop circuit FF ₁₀ the power signal POR is input to the clear terminal, the first flip-flop circuit FF ₁₀ The output terminal Q is connected to the first terminal T ₁ , the second output terminal XQ of the flip-flop circuit FF ₁₀ (inverted output of the first output terminal Q) is connected to the second input terminal T ₂ , and even / odd fields are set. The first switch SW _{1 for} switching is connected to one end of the high-potential power supply V _CC and the other end thereof is connected to the low-potential power supply GND, and in the non-interlace mode by an external interlace / non-interlace mode switching control signal. a second switch SW ₂ which is a closed (oN) state, the first output signal of the switch SW ₁ is input to the first input terminal, a second input terminal is high potential side power supply V _CC and the second Sui An AND circuit AND ₅ which is connected to an intermediate connection point between the switch SW _2, and is configured with a.

FIG. 11 shows the operation of the parity generation circuit 54A.
An imming chart is shown. Time t in FIG.₁At
Flip-flop circuit FF_TenIs the vertical synchronization signal V _sync’
Based on the output signal corresponding to the vertical synchronization period (Fig.
11 (d)) is output from the first output terminal Q and
The transfer output signal is output from the second output terminal XQ.

At time t ₁ , the operator turns off (opens) the second switch SW ₂ , that is, selects the interlace mode as the display mode (FIG. 11 (f)).
, The voltage of the high-potential-side power supply V _CC is applied to the second input terminal of the AND circuit AND ₅ , and the second input terminal becomes the “H” level.

As a result, the AND circuit AND ₅ has the first
The parity signal Pa ″ for which the level for the interlace mode, which is input from the first output terminal Q or the second output terminal XQ output through the switch SW ₁ and continues to invert, is output as it is.

At this time, if the first switch SW ₁ is switched by the even / odd field control signal, the parity signal Pa ″ whose polarity is inverted can be obtained (FIG. 11 (d)).
And (e)).

As a result, the interlace mode display is displayed on the display section 40. On the other hand, if the operator turns on (closes) the second switch SW ₁ at time t ₂ , that is, selects the non-interlaced mode as the display mode (see FIG. 11 (f)), the AND circuit AND ₅ of the second circuit is selected. The voltage of the low-potential-side power supply CND is applied to the second input terminal, and the second input terminal becomes "L" level.

As a result, the second input terminal of the AND circuit AND ₅ is connected to the low potential side power supply GND, and the second input terminal becomes "L" level. As a result, the AND circuit A
The output of ND ₅ is always fixed to the “L” level, and the parity signal P for the non-interlaced mode has a constant level.
Since a is output, non-interlaced mode display is performed on the display unit 40.

As described above, according to the second embodiment, since the parity signal corresponding to the display mode selected by the operator can be output, it is possible to continue the abnormality of the parity signal. Also, it is possible to reliably generate the parity signal and prevent the abnormal display.

[0130] In the above description, the non-interlace mode display time, had been fixed "to" parity signal Pa to L "level, the AND circuit AND ₅ and NAND circuit, by inverting the even / odd field control signal For example, it is possible to fix the non-interlace mode display parity signal to the “H” level while keeping the polarity of the interlace mode display parity signal.

Further, the flip-flop circuit FF ₁₀ can generate the parity signal Pa ″ regardless of which of the first switches SW ₁ is switched, but when the line interpolation is performed, the transmitted display is performed. since displaying the even / odd field data is reversed may become unnatural, it is necessary to switch the first switch SW ₁ when necessary. third embodiment FIG 12 in the third embodiment 12 is a block diagram showing a detailed configuration of the parity generation circuit 54 B. The difference from the parity generation circuit 54 A in FIG.
The point A is that the parity signal is generated without distinguishing the even field and the odd field, whereas the parity signal is automatically generated by distinguishing the even field and the odd field.

The parity generation circuit 54B has a data terminal D.
A flip-flop circuit FF ₁₁ to which a high-potential-side power supply V _CC is connected, a clock terminal receives an external parity signal Pa, and a clear terminal receives a power signal POR;
The J terminal is connected to the output terminal 1Q of the flip-flop circuit FF ₁₁ , the high potential side power supply V _CC is connected to the K terminal, the vertical synchronizing signal V _sync 'is input to the clock terminal, and the power supply signal POR is input to the clear terminal. And a flip-flop circuit FF ₁₂ which outputs the parity signal Pa ″ ′ from the output terminal 2Q thereof.

FIG. 13 shows an initial operation timing chart of the parity generation circuit 54B. At time t ₁ in FIG. 13, when the external parity signal Pa becomes “H” level (this corresponds to either the even field or the odd field), the output of the flip-flop circuit FF ₁₁ is output at the time t _2. Similarly, the output signal from the terminal 1Q becomes "H" level.

As a result, at the time t ₃ , the flip-flop circuit FF ₁₂ determines, based on the vertical synchronizing signal V _sync ', the "H" level parity signal Pa "' corresponding to the vertical synchronizing period (FIG. 11 (d). ) Reference) is output from the output terminal 2Q, and thereafter, the parity signal Pa ″ ′ having a phase corresponding to the parity signal Pa from the outside is output, which corresponds to the even field and the odd field of the input video signal. A parity signal can be output.

As described above, according to the third embodiment, the parity signal Pa ″ ″ having the phase corresponding to the parity signal Pa to be transmitted is used even when line interpolation is performed.
Can be output, so that the even / odd fields do not reverse and the display does not become unnatural.

[0136]

According to the first aspect of the invention, when the display mode switching signal (Pa) corresponds to the second display mode for a predetermined time after the change of the display mode switching signal (Pa) is detected. Since only the display mode is switched to the second display mode,
It is possible to prevent the display mode from being erroneously changed due to the influence of temporary noise and the like, and it is possible to prevent a display abnormality such as vertical compression display of the screen due to the erroneous change of the display mode.

According to the second invention, the internal display mode switching signal (Pa ') corresponding to the first display mode is generated and output for a predetermined time after the change of the display mode switching signal (Pa) is detected. However, the display mode switching signal (P
second only if a) corresponds to the second display mode
Internal display mode switching signal (P
a ') is generated and output, the display mode switching signal (P
From the detection of the change in a) until the predetermined time elapses,
The display is performed in the first display mode and then in the second display mode, and the display mode is prevented from being accidentally changed due to the influence of temporary noise, etc. It is possible to prevent the display abnormality such as the screen vertical compression display due to the change of the, and perform stable screen display. According to the third invention, even if the display mode switching signal is not stable for some reason, the alternative display mode switching signal corresponding to any display mode is forcibly generated and A stable display can be performed in the display mode.

According to the fourth invention, the display mode switching means (54) makes the display mode switching signal correspond to the second display mode for a predetermined time based on the discrimination signal (PC). In this case, the display mode is switched to the second display mode, so that the display mode is prevented from being accidentally changed due to the influence of temporary noise, etc., and the screen vertical compression is caused by the display mode being accidentally changed. It is possible to prevent display abnormality such as display.

According to the fifth aspect of the invention, the display mode switching signal generating means (54) detects a change in the display mode switching signal (Pa) based on the discrimination signal (PC) until a predetermined time elapses. Generates and outputs an internal display mode switching signal (Pa ') that is the same signal as the display mode switching signal corresponding to the first display mode based on the display mode switching signal (Pa), and at the same time, When the display mode switching signal (Pa) corresponds to the second display mode, the display mode switching signal (Pa) corresponding to the second display mode based on the display mode switching signal (Pa) after a predetermined time has elapsed. Internal display mode switching signal (P
Since a ') is generated and output, the display mode will not be accidentally changed due to the influence of temporary noise, etc.
It is possible to prevent a display abnormality such as a screen vertical compression display due to the display mode being erroneously changed and perform stable screen display.

According to the sixth invention, the display mode switching signal generating means (54A) receives the second display mode instruction signal corresponding to the first display mode during the display in the first display mode. When it is detected that the display mode instruction signal corresponding to the display mode is changed, the alternative display mode switching signal (Pa ″) corresponding to the second display mode is generated. When the display is performed based on the display, even if the display mode switching signal is not stable for some reason, stable display can be performed in any display mode.

[Brief description of drawings]

FIG. 1 is a schematic configuration block diagram of a display system.

FIG. 2 is a detailed configuration diagram of a parity signal detection determination circuit unit.

FIG. 3 is a detailed configuration diagram of a parity generation circuit according to the first embodiment.

FIG. 4 is an operation timing chart (in interlaced mode) of the parity generation circuit of the first embodiment.

FIG. 5 is an operation timing chart (in non-interlaced mode) of the parity generation circuit of the first embodiment.

FIG. 6 is a schematic operation timing chart of the control circuit (at the time of erroneous detection).

FIG. 7 is a schematic operation timing chart (at the time of normality detection) of the control circuit.

FIG. 8 is a detailed operation timing chart (at the time of erroneous detection) of the parity signal detection determination circuit section.

FIG. 9 is a detailed operation timing chart (at the time of normality detection) of the parity signal detection determination circuit section.

FIG. 10 is a detailed configuration diagram of a parity generation circuit according to a second embodiment.

FIG. 11 is an operation timing chart of the parity generation circuit of the second embodiment.

FIG. 12 is a detailed configuration diagram of a parity generation circuit according to a third embodiment.

FIG. 13 is an operation timing chart of the parity generation circuit of the third embodiment.

FIG. 14 is an operation timing chart in the conventional display control device.

FIG. 15 is a diagram illustrating a conventional problem.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Signal source 11 ... Video equipment 11 12 ... Personal computer 20 ... Interface control part 21 ... Separation circuit 22 ... Decoder 23 ... A / D conversion and gamma correction circuit 24 ... Output selection circuit 30 ... Display control part 31 ... Control circuit 31A ... parity signal detection determination circuit section 32 ... driving circuit 40 ... display section 50 ... clock generation circuit 51 ... first comparator 52 ... second comparator 53 ... inverter 54 ... parity generation circuit 54A ... parity generation circuit 54B ... parity generation circuit 55 ... inverter 100 ... display system A ... first parity data group A ₁ ... first parity data A ₂ ... second parity data AD ₁ ... first 1AND signal AD ₂ ... first 2AND signal AD ₃ ... first 3AND signal AD ₄ ... first 4AND signal the AND ₁ ... first 1AND circuit the AND ₂ ... first 2AND circuit the AND ₃ ... 3AND circuit the AND ₄ ... first 4AND circuit the AND ₅ ... the AND circuit B ... second parity data group BLNK ... blanking signal B ₁ ... third parity data B ₂ ... 4 parity data BUF ₁ ... buffer circuit C ₁ ... first comparison result signal C ₂ ... second comparison result signal CLK ₁ ... first clock signal CLK ₂ ... second clock signal CLK ₃ ... third clock signal D ... third parity data groups D ₁ ... 5 parity data D ₂ ... 6 parity data DL ... delay circuit DL ₂ ... delay circuit DPOR ... delayed power signal D _RGB ... RGB data DT ... delay timer signal FF ₁ ... first flip-flop circuit FF ₂ ... second flip-flop circuit FF ₃ ... third flip-flop circuit FF ₄ ... the fourth flip-flop circuit FF ₅ ... fifth flip-flop circuit FF ₆ ... sixth flip-flop times FF ₇ ... 7 flip-flop circuit FF ₈ ... eighth flip-flop circuit FF ₉ ... ninth flipflop circuit FF ₁₀ ~FF ₁₂ ... flip-flop circuit GND ... low potential side power supply H _S ... horizontal sync signal H _sync ... horizontal sync Signal H _sync '... Horizontal sync signal Pa ... Parity signal Pa "' ... Parity signal PC ... Parity switching signal POR ... Power supply signal REG _1-0 ... First pre-stage register REG _1-1 ... First post-stage register REG _2-0 . Second pre-stage register REG _2-1 Second post-stage register REG _3-0 ... Third pre-stage register REG _3-1 ... Third post-stage register S _RGB ... Analog RGB signal S _RGB '... Analog RGB signal S _V ... Video signal SW ₁ ... first switch SW ₂ ... second switch T ... timer signal TM ... timer V _S ... vertical synchronization signal V _sync ... vertical synchronization signal V _sync '... vertical synchronization signal _CC ... high-potential power supply XC ₁ ... inverted first comparison result signal XC ₂ ... inverted second comparison result signal

Claims (6)

[Claims] 1. A display mode switching signal (Pa) from the outside.
A display control method for a display device capable of switching between two display modes, an interlaced display mode and a non-interlaced display mode, based on the above, and corresponding to the first display mode during display in the first display mode. Detecting that the display mode switching signal (Pa) has changed to the display mode switching signal (Pa) corresponding to the second display mode, and detecting the change of the display mode switching signal (Pa) During the time, it is determined whether the display mode switching signal (Pa) corresponds to the second display mode, and during the predetermined time, the display mode switching signal (Pa) indicates the second display. A display control method, wherein the display mode is switched to a second display mode when the mode is supported. 2. A display mode switching signal (Pa) from the outside.
A display control method for a display device capable of switching between two display modes, an interlaced display mode and a non-interlaced display mode, based on the above, and corresponding to the first display mode during display in the first display mode. Detecting that the display mode switching signal (Pa) has changed to the display mode switching signal (Pa) corresponding to the second display mode, and detecting the change of the display mode switching signal (Pa) During the time, it is determined whether or not the display mode switching signal (Pa) corresponds to the second display mode, and the predetermined time elapses after the change in the display mode switching signal (Pa) is detected. Until then, the internal display mode switching signal is the same signal as the display mode switching signal (Pa) corresponding to the first display mode based on the display mode switching signal (Pa). (Pa ′) is generated and output, and when the display mode switching signal (Pa) corresponds to the second display mode during the predetermined time, the display mode switching signal ( Based on Pa), an internal display mode switching signal (Pa ') that is the same signal as the display mode switching signal (Pa) corresponding to the second display mode is generated and output. . 3. A display control method for a display device capable of switching between two display modes, an interlaced display mode and a non-interlaced display mode, based on a display mode switching signal (Pa), wherein the first display mode is used. Corresponding to the second display mode when it is detected that the external display mode instructing signal corresponding to the first display mode changes to the display mode instructing signal corresponding to the second display mode during display. Generating a substitute display mode switching signal (Pa ″) for performing the display control method. 4. A display mode switching signal (Pa) from the outside.
A display control device for a display device capable of switching between two display modes, an interlaced display mode and a non-interlaced display mode, based on the above, and corresponding to the first display mode during display in the first display mode. Detection means (51) for detecting that the display mode switching signal (Pa) has changed to the display mode switching signal (Pa) corresponding to the second display mode and outputting a change detection signal (C ₁ ); The display mode switching signal (Pa) corresponds to the second display mode for a predetermined time after detecting the change of the display mode switching signal (Pa) based on the change detection signal (C ₁ ). Discrimination signal (PC)
Status determining means (52, TM, FF _{2 to} F
F ₄ ), and based on the discrimination signal (PC), during the predetermined time,
A display control device comprising: a display mode switching unit (54) for switching the display mode to the second display mode when the display mode switching signal corresponds to the second display mode. 5. A display mode switching signal (Pa) from the outside
A display control device for a display device capable of switching between two display modes, an interlaced display mode and a non-interlaced display mode, based on the above, and corresponding to the first display mode during display in the first display mode. Detection means (51) for detecting that the display mode switching signal (Pa) has changed to the display mode switching signal (Pa) corresponding to the second display mode and outputting a change detection signal (C ₁ ); The display mode switching signal (Pa) corresponds to the second display mode for a predetermined time after detecting the change of the display mode switching signal (Pa) based on the change detection signal (C ₁ ). Discrimination signal (PC)
Discriminating means for outputting (52, TM, FF _{2 to} FF ₄ )
And the first display based on the display mode switching signal (Pa) until the predetermined time elapses after the change in the display mode switching signal (Pa) is detected based on the determination signal (PC). An internal display mode switching signal (Pa ′) that is the same as the display mode switching signal corresponding to the mode is generated and output, and the display mode switching signal (Pa) is changed to the second display during the predetermined time. When the display mode switching signal corresponds to the mode, the internal display mode is the same signal as the display mode switching signal (Pa) corresponding to the second display mode based on the display mode switching signal (Pa) after the predetermined time has elapsed. A display control device comprising: a display mode switching signal generating means (54) for generating and outputting a switching signal (Pa '). 6. A display control device for a display device capable of switching between two display modes of an interlaced display mode and a non-interlaced display mode on the basis of a display mode switching signal, and displaying during the first display mode. When it is detected that the external display mode instruction signal corresponding to the first display mode has changed to the display mode instruction signal corresponding to the second display mode, the alternative display corresponding to the second display mode. A display control device comprising a display mode switching signal generating means (54A) for generating a mode switching signal (Pa ").