JPH0760458B2 - Image memory writing controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial field of application> The present invention relates to an image memory writing control device, and more specifically, a linear interpolation calculator (hereinafter abbreviated as DDA).
It is an object of the present invention to provide a novel image memory writing control device capable of writing data to a memory without stopping the calculation operation of.

<Prior Art and Problems to be Solved by the Invention> In the conventional graphic display device,
Since it is necessary to increase the image memory capacity and to reduce the cost as a whole, static random access memory (hereinafter referred to as SRAM) is rarely used, and dynamic random access memory (hereinafter referred to as DRAM). (Abbreviated) is commonly used.

However, when DRAM is used as an image memory, the processing time required for DDA to generate pixel data is 50n per pixel.
Even though it is about sec, the time required to access the DRAM is 2
Since it is about 30 to 400 nsec, it is necessary to stop the DDA operation frequently while writing all the necessary pixel data to the image memory, which increases the time required to write the pixel data to the image memory. As a result, there is a problem that the time required for displaying an image becomes significantly long.

In order to solve such a problem, in a raster scan type graphic display device, as shown in FIG. 8, pixel data output from a DDA (71) is temporarily moved along a scan line by a predetermined number. A buffer memory (72a) (72b) for holding is provided, and an image memory (hereinafter referred to as a frame memory) in which a predetermined number of pixel data output from each buffer memory is written (7)
3) is provided, and further, the above buffer memories (72a) (72
b) It controls the switching of the frame memory (7
3) is provided with a timing control circuit (74) for supplying a memory timing signal (hereinafter abbreviated as double buffer system). 1x8 double buffer method that can hold only 8 pixel data in the direction, and 4x4 double buffer that can hold 4 pixels in the scan line direction and 4 pixels in the direction perpendicular to the scan line. There is a buffer method, and in either method, the frame memory (73)
To reduce the frequency of DDA operation stop due to long access time, improve the image data writing speed to the frame memory when viewing the entire image to be displayed, and eventually improve the image display speed to some extent Can be made.

More specifically, the double buffer method is
The pixel data is supplied from one buffer memory to the frame memory (73) while the pixel data is supplied from one buffer memory to the frame memory (73) by the DDA (71). Even while the pixel data is being written to the frame memory (73), the pixel data can be supplied to the other buffer memory, and DDA (7
As the frequency of stopping the operation of 1) is reduced, it is possible to improve the pixel data writing speed in the frame memory (73) when the entire image is viewed.

In particular, the 1 × 8 double buffer method is based on the DDA (7
The 8 pixel data in the scan line direction, which is sequentially output from 1), is temporarily held alternately in one of the buffer memories, and the frame memory is supplied from the buffer memory on the side not receiving the pixel data from the DDA (71). (73)
8 pixel data is written to the frame memory, it is possible to remarkably shorten the time required for writing to the frame memory in the case of performing an operation with a high probability that the pixel data is continuous along the scan line, such as a polygon filling operation. it can. That is, even if the time required to write data to the frame memory (73) is eight times as long as the time required to generate the pixel data of the DDA (71), the time required to write the data for each pixel will be equal to each other. It is not necessary to stop the DDA (71) except the period of refreshing the memory (73) and reading data from the frame memory (73) for display, and the time required to write data to the frame memory (73). Can be shortened as a whole.

However, when drawing a line segment that is inclined with respect to the scan line, the number of pixel data written in the buffer memory at one time decreases, so the frame memory (7
There is a problem that the DDA (71) is forced to stop the arithmetic operation for a considerable time during the data writing period for 3), and the data writing time becomes long as a whole. Explaining in more detail, for example, when drawing a line segment having an inclination angle of 45 ° or more with respect to a scan line, one of data writing from the buffer memory to the frame memory (73) is performed.
Since only one pixel data is written in the cycle (see FIG. 9A), the operation by DDA (71) need only be the operation for the one pixel data, and the data write to the frame memory (73). Even if the calculation speed is eight times the speed, the calculation operation is forced to stop during the period in which the remaining seven pixel data can be calculated (see FIG. 9B).

Further, since the 4 × 4 double buffer system has a buffer memory having a memory area of 4 pixels in the scan line direction and a direction perpendicular to the scan line, not only in the scan line direction, By using the DDA (71), which can hold up to 4 pixel data even in the direction inclined with respect to the scan line and has a calculation speed four times as fast as the data write speed to the frame memory (73), The writing speed per pixel can be made almost equal to the calculation speed of the DDA (71).

However, when the relative positional relationship between the line segment to be drawn and the buffer memory is changed, as shown in FIG.
In some cases, only one pixel or one pixel is written. In the former case, as shown in FIG.
During the period in which one pixel data can be calculated, the calculation operation must be stopped.

In summary, even if the calculation speed of the DDA (71) is increased or the capacity of the buffer memories (72a) (72b) is increased, it is inevitable that the DD
The calculation operation of A (71) may be forced to stop, and the time required to write pixel data corresponding to a line segment having an arbitrary inclination angle to the scan line in the frame memory (73). There is a problem that it fluctuates greatly.

<Objects of the Invention> The present invention has been made in view of the above problems,
DD regardless of the inclination angle of the drawing line segment with respect to the scan line
An object of the present invention is to provide an image memory writing control device capable of writing pixel data into an image memory at high speed without stopping the arithmetic operation of A.

<Means for Solving the Problems> In order to achieve the above object, the image memory writing control device of the present invention is configured such that the image memory is composed of a plurality of block memories to which different scan lines are allocated. A double buffer memory is provided corresponding to each block memory, and among the coordinate data output from the linear interpolation calculator, the coordinate data in the direction orthogonal to the scan direction is input and the lower digit is decoded and doubled based on the decode signal. In addition to selecting the buffer memory, select the block memory corresponding to this duffle buffer memory, decode the lower digit with coordinate data in the scan direction as input, and switch the selected double buffer memory based on the decode signal. A timing control means for generating a control signal to cause the control is provided.

However, as the timing control means, for the coordinate data in the scan direction, a control signal is generated at the timing when the lower predetermined digit corresponding to the capacity of the double buffer memory changes, and for the coordinate data in the direction perpendicular to the scan direction. It is preferable that the control signal is generated at the timing when the least significant digit changes.

Furthermore, it is preferable that the timing control means generates a control signal for switching the double buffer memory by also receiving the drawing end signal output from the DDA.

Further, it is preferable that the image memory is composed of a plurality of block memories of a predetermined size, and each block memory is divided into two in order to store mutually different image data, and it is a dual port DRAM. Is more preferable.

<Operation> If the image memory writing control device having the above configuration is used,
When writing the pixel data generated by the image memory to the image memory, the image memory is composed of a plurality of block memories to which different scan lines are assigned, and a double buffer memory is provided corresponding to each block memory. Of the coordinate data output from the interpolation calculator, the lower digit is decoded by inputting the coordinate data in the direction orthogonal to the scan direction, the double buffer memory is selected based on the decoded signal, and this double buffer memory is also supported. Select the block memory, input the coordinate data in the scan direction, decode the lower digit,
Since the timing control means for generating a control signal for switching the selected double buffer memory based on the decode signal is provided, the operation result data output from the DDA is immediately held in any buffer memory, Since the data held in the buffer memory is sequentially supplied to the image memory, it is possible to always generate pixel data without interrupting the operation of the DDA, and to temporarily generate the generated pixel data. The data can be written in the image memory sequentially while being held in the buffer memory, and the data writing speed to the image memory can be improved as a whole.

Then, the timing control means, for the coordinate data in the scanning direction, generates a control signal at the timing when the lower predetermined digit corresponding to the capacity of the double buffer memory changes, and for the coordinate data in the direction perpendicular to the scanning direction,
When the control signal is generated at the timing when the least significant digit changes, the double buffer memory can be switched or the double buffer memory can be selected based on the generated control data. The same effect as can be achieved.

Furthermore, when the timing control means generates a control signal for switching the double buffer memory by also inputting the drawing end signal output from the DDA, the double buffer is automatically set at the end of drawing. The memory can be switched.

When the image memory is composed of a plurality of block memories of a predetermined size, and each block memory is divided into two to store different image data, the data of the entire image memory is The number of write input bits can be increased.

When the image memory is a dual port DRAM, the prohibition time of data writing accompanying the data reading from the image memory can be greatly reduced,
The same operation as described above can be achieved.

More specifically, the calculation time required by DDA is t1
And the time required to write data to the image memory is t2
If (however, t2 = nt1), the image memory is composed of n block memories, and a double buffer memory and a timing control means are provided corresponding to each block memory, so that the calculation operation by the DDA can be performed. By supplying data from the double buffer memory to the corresponding block memory without stopping, it is possible to write data to the image memory at high speed. That is, when continuous pixel data is sequentially generated from the DDA in the scan line direction, a predetermined number of pixel data are sequentially supplied to the double buffer memory corresponding to the scan line, and a predetermined number of pixel data are supplied. In such a case, the double buffer memory can be switched and the predetermined number of pixel data can be supplied again. Then, while the pixel data is being supplied to one buffer memory, a predetermined number of pixel data can be collectively supplied from the other buffer memory to the block memory. As a result, DDA
It is possible to continuously write data to the image memory while continuously operating the.

Also, when continuous pixel data is sequentially generated from the DDA in the direction inclined to the scan line, the pixel data belonging to the same scan line is stored in the double buffer memory corresponding to the scan line in the same manner as above. It can be supplied to different double buffer memories when the scan line changes. Then, when the scan line changes, different double buffer memories are sequentially selected. Therefore, the scan line changes n times before the original double buffer memory is selected again. Since the data writing to the image memory can be completed by the time, the series of operations described above can be reflected without stopping the operation of the DDA.

<Example> Hereinafter, detailed description will be given with reference to the accompanying drawings illustrating an example.

FIG. 1 is a block diagram showing an embodiment of an image memory writing control device, in which pixel data output from a DDA (1) is stored in a plurality of double buffer memories (21) (22) ... (2n).
Is supplied to each of the double buffer memories (21), (22), ... (2n), and a plurality of block memories (31) (32) constituting the image memory (3) as a whole.
... (3n) is supplied with the held data, and further, the address data output from the DDA (1) is used as an input to perform a predetermined decoding process to the corresponding double buffer memory and block memory. Timing control circuits (41) (42) for supplying write control signals ...
(4n) is provided. Each of the timing control circuits receives the address data output from the DDA (1) as an input and scans the address data in the scan line direction (hereinafter, x
Coordinate data) and address data in the direction perpendicular to the scan line (hereinafter abbreviated as y coordinate data) are decoded respectively, and a predetermined digit data of the x coordinate (with the lowest digit as a reference) is doubled. (Data of the upper digit by a predetermined digit determined based on the capacity of the buffer memory)
The double buffer memory switching control signal is generated based on the decode signal corresponding to, the data write control signal for the block memory is generated, and the double buffer selection control signal is generated based on the decode signal corresponding to the least significant digit data of the y coordinate. , And a double buffer memory switching control signal, a data writing control signal for the block memory, and a line segment drawing end signal (a signal indicating that the control counter of DDA (1) has become 0). The double buffer memory switching control signal is generated based on the corresponding decode signal. Further, each of the block memories (31) (32) ... (3n) has a dual plane structure so that other image data can be written while one image is displayed. There is.

The operation of the image data writing control device having the above configuration is as follows.

Pixel data continuous in the scan line direction is DDA (1)
In this state, only one timing control circuit generates a write control signal, and the double buffer memory is switched every time a predetermined number of pixel data is generated, and one of the buffer memories has a DDA (1 While supplying the generated pixel data from (1), a plurality of pixel data can be collectively written from the other buffer memory to the block memory. Therefore, a predetermined number of pixel data can be collectively written in the image memory (3) without any interruption of the calculation operation by the DDA (1).

In a state in which pixel data consecutive in a direction inclined by a predetermined angle with respect to a scan line is sequentially generated from DDA (1), while pixel data belonging to the same scan line is continuously generated, this is applicable. The timing control circuit can generate a write control signal to supply pixel data to the double buffer memory and write pixel data from the double buffer memory to the block memory. Then, when the pixel data belonging to the adjacent scan line is generated, the corresponding timing control circuit generates the write control signal to supply the pixel data to the double buffer memory, and the double buffer memory to the block memory. Pixel data can be written.

Hereinafter, the timing control circuit that generates the write control signal changes every time the scan line to which the generated pixel data belongs changes, and pixel data that is continuous in the direction inclined by a predetermined angle with respect to the scan line is written in the image memory. be able to.

That is, the number of pixel data supplied to each double buffer memory is generally smaller than the limit number determined based on the capacity of the double buffer memory, but until the pixel data is supplied to the same double buffer memory. The time,
If it is set to a time that is not shorter than the time required to write data from the double buffer memory to the block memory, the pixel data held in the double buffer memory will be collected at once without interrupting the calculation operation by DDA (1). It can be written to the image memory (3).

Then, when one image data is written as described above, the image data can be read from the corresponding image memory plane to cause the image display, and while the image display is being performed, the other image data can be displayed. The next image data can be written to the image memory plane.

FIG. 2B is a diagram for explaining the data writing operation corresponding to the case where the image memory (3) is divided into four block memories (31) (32) (33) (34), and FIG. This corresponds to the case where the pixel data shown in A is sequentially generated from DDA (1).

If the pixel data P1 is generated from the DDA (1), it is supplied to one of the double buffer memories (21) (hereinafter, abbreviated as A surface). Next, if the pixel data P2 is generated, the scan line has changed, so that it is supplied to the A side of the double buffer memory (22) and the A side of the double buffer memory (21) is directed to the data reading side. Switched
Written to block memory (31). Next, the pixel data P3
If is generated, the scan line has not changed, but
Since it exceeds the bit boundary in the x coordinate direction, it is supplied to the B side of the double buffer memory (22) and
Side A is switched to the read side and written in the block memory (32). If the pixel data P4 is further generated, the scan line has changed, and therefore the pixel data P4 is supplied to the A side of the double buffer memory (23). If pixel data P5 and P6 are generated next, the scan line has not changed between both pixel data and the bit boundary in the x-coordinate direction has not been exceeded, so the double buffer memory (24) is generated in the order of generation. It is supplied to the A side of. After that, if the pixel data P7 is generated, it is supplied to the B side of the double buffer memory (21). In this case, since writing from the side A of the double buffer memory (22) to the block memory (32) has been completed, the double buffer memory (2
The B side of 2) is switched to the read side and the block memory (3
At the same time as writing to 2), side A of the double buffer memory (24) is switched to the data reading side and written to the block memory (34).

Thereafter, similarly, the pixel data can be supplied to the double buffer memory and the pixel data held in the double buffer memory can be written to the block memory.

More specifically, the change in the content of a specific digit of the address data output from the DDA (1) is indicated by the sequential register (51) of the output data from the DDA adder (11) as shown in FIG. 3A. (52) (52) can be easily carried out by adopting a pipeline configuration.

That is, as shown in FIG. 3B, the registers (51) (5
2) As a D-type flip-flop (hereinafter, D-FF
Is supplied to the D input terminal of the first-stage D-FF (51), and the l-th digit data output from the DDA adder (11) is supplied to the first-stage D-FF (51). The Q output signal of FF (51) is supplied to the D input terminal of the second stage D-FF (52).
If the DDA clock signal is supplied to the timing input terminals of both D-FFs (51) (52), both D-FFs (51)
(52) Q output signal al, bl and output signal l, l
Is obtained. Then, the obtained signals bl and l are
The signals al and l are supplied to the AND gate (54) while being supplied to the D gate (53), and both AND gates (53) (5
By supplying the output signal from 4) to the NOR gate (55), a detection flag for detecting a specific digit change can be generated.

FIG. 4 shows the change of the least significant digit of the y coordinate, the change of the high significant digit from the least significant digit of the x coordinate, and the end of the line segment drawing.
The circuit configuration for detecting only when the lower digit of the coordinate has a predetermined value is shown. Output data from the DDA adder (56) for x coordinate and the DDA adder (57) for y coordinate are respectively output. While supplying the circuit having the same configuration as that of FIG. 3, a flag output from the DDA down counter (58) (an overflow flag which becomes a high level when the content of the down counter (58) is 0), and The AND gate (60) outputs the output signal from the decoder (59) which becomes high level when the y-coordinate data output from the DDA is input and the content of the lower digit becomes a value corresponding to a predetermined block memory.
Is being supplied to. The output signals from the decoder (59) are supplied to all AND gates, and the output signals from all AND gates are supplied to the NOR gate (61).

Therefore, when the above configuration is adopted, when the output signal from the decoder (59) is at high level, y
A negative logic double buffer memory switching timing detection flag can be output from the NOR gate (61) in response to a change in the least significant digit of the coordinate, a change in a predetermined digit of the x coordinate, and the end of line segment drawing.

The decoder shown in FIG. 4 and the AND-OR-INVERTER
Can be easily converted into PAL (Programable Alley Logic).

FIG. 5 shows the timing control of the DRAM and the double buffer memory switching without stopping the DDA based on the double buffer memory switching timing detection flag generated by the circuit configuration exemplified in the above embodiment. It is a figure showing a circuit configuration, and eight D-FF
It has (71), (72), ... (78). The circuit configuration shown in FIG. 4 and the circuit configuration shown in FIG. 5 constitute a timing control circuit corresponding to one double buffer memory and block memory.

The D-FF (71) uses a horizontal synchronization signal () (see FIG. 6C) output from a CRT controller (not shown) as a timing input, and a handshake signal indicating whether read transfer or refresh has been accepted. ▲
Using ▼ (see FIG. 6Q) as a clear input, a Q output signal Q1 (see FIG. 6H) indicating whether a read transfer or refresh request to the DRAM is generated is generated. This Q output signal Q1 is supplied as it is to the D input terminal of the D-FF (72) whose timing input is the sampling strobe signal SRCK (see FIG. 6L), and DR
A Q output signal Q2 (see FIG. 6M) indicating whether it is a write cycle for AM, a read transfer, or a refresh cycle is generated.

The D-FFs (73) and (74) hold the double buffer memory switching timing detection flag ▲ ▼ (see FIG. 6F), and are the same as each other except that they selectively operate. It is designed to operate. That is, a NAND gate (7 that uses the output signal of the D-FF as a control signal)
The double buffer memory switching timing detection flag ▲ ▼ is supplied to the D input terminal through 9) and the DDA pixel strobe signal DDARCK (see FIG. 6G) whose level changes for each pixel is supplied through the OR gate (80). A negative logic handshake signal ▲ ▼ (see R in FIG. 6) supplied to the timing input terminal and indicating that the memory write cycle has been accepted is cleared through the OR gate (81) and the AND gate (82). It is supplied to the input terminal. Then, the Q output signal SELA (see FIG. 6D) output from the D-FF (78) and the output signal SELB (see FIG. 6E) corresponding to one of the D-FFs.
Are respectively supplied to the OR gates (80) and (81), and the Q output signal SELA and the output signal SELB output from the D-FF (78) are respectively associated with the OR gate (80) and (81). 81) (80).

Therefore, of the Q output signal SELA or the output signal SELB supplied to the OR gate (80), the low-level side D-FF is selected for data retention, and the rising edge of the DDA pixel strobe signal DDARCK is selected. The double buffer memory switching timing detection flag ▲ ▼ is fetched at the timing. However, since the double buffer memory switching timing detection flag ▲ ▼ is supplied through the NAND gate (79) controlled by the output signal {signals BF1 and BF2 (see I and J in FIG. 6)}, the buffer memory is full. It is supplied to the D input terminal at the timing when a state is likely to occur, and at the same time, supplied to the OR gate (83) described later and held as it is.

The D-FF (75) generates a Q output signal Q3 corresponding to the next double buffer memory switching state,
The output signal is supplied to the D input terminal, and the negative logic handshake signal ▲ ▼ is supplied to the timing input terminal.

The D-FF (76) (77) is a sampling strobe signal synchronized with a clock without generating a glitch.
SRCK is generated, and a negative logic pulse signal ▲ ▼ (see FIG. 6O) indicating two clocks before the end of the memory cycle is supplied to the timing input terminal of D-FF (76) and the memory cycle is completed. A negative logic pulse signal {circle around (1)} that is always generated therein (for example, a DRAM column address strobe signal (see FIG. 6P)) is supplied to the preset input terminal. Then, the D-FF (7
The OR gate (8) outputs the Q output signal Q1 of 1) and the output signal from the NAND gate (79) corresponding to both D-FFs (73) (74).
NAND that supplies the D input terminal of D-FF (77) through 3) and also receives the output signal of D-FF (76) (77) and sampling clock signal SCK (see FIG. 6A). The output signal from the gate (84) is output as the sampling strobe signal SRCK and is also supplied to the timing input terminal of the D-FF (77). The negative logic pulse signal ▲ ▼ is supplied to the clear input terminal of the D-FF (77). In addition, the Q output signal of D-FF (77)
It is output as a start signal (see FIG. 6N) indicating that the memory cycle starts at the rising timing.

The D-FF (78) outputs the signals SELA and SELB for double buffer memory switching as a Q output signal and an output signal, respectively. The Q output signal of the D-FF (75) is supplied to the D input terminal. In addition, the sampling strobe signal SRCK is supplied to the timing input terminal, and the output signal AC from the OR gate (83) is also supplied.
DM (see K in FIG. 6) is supplied to the G input terminal through the inverter (85).

Therefore, the Q output signal from the D-FF (75) is held at the timing when the signal supplied to the G input terminal is at the high level and the sampling strobe signal SRCK rises, and is made to correspond to the level of this Q output signal. Then, the Q output signal SELA and the output signal SELB which have mutually opposite levels are continuously output.

Furthermore, a negative logic initialization signal ▲ ▼ (Fig. 6B
Are supplied to the clear input terminals of the D-FFs (71) (73) (74) ... (78).

The operation of the circuit shown in FIG. 5 is as follows.

First, when the power is turned on, or when processing is interrupted, an initialization signal ▲
Perform necessary initialization with ▼.

After that, each time a negative logic handshake signal ▲ ▼ is supplied to the timing input terminal, the level of the Q output signal of D-FF (75) changes alternately, so a low level signal is supplied to the G input terminal. At the timing when the sampling strobe signal SRCK rises, the D-FF (78) holds the Q output signal and can output the Q output signal SELA and the output signal SELB corresponding to the level of the Q output signal. Therefore, the Q output signal SELA and the output signal SE
Either D-FF (73) or (74) is selected based on the level of LB. That is, the D-FF on the side to which the low level signal is supplied to the OR gate (80) is selected.

The D-FF on the selected side is supplied with the double buffer memory switching timing detection flag ▲ ▼ as the D input signal through the NAND gate (79) controlled by the output signal, and the OR gate ( 8
0), the DDA pixel strobe signal DDARCK is supplied as a timing input signal.
Double buffer memory switching timing detection flag at the rising edge of pixel strobe signal DDARCK ▲
▼ Take in and hold it as it is. In addition, the above double buffer memory switching timing detection flag ▲
▼ is not taken out from the Q output terminal of D-FF,
Since it is taken out from the output terminal of the NAND gate (79) as it is, it is supplied to the OR gate (83) at the timing when the buffer memory becomes full without delaying by one pixel, and the D-FF ( By being supplied to the D input terminal of 77), a start signal indicating the start of the memory cycle can be output from the Q output terminal.

Then, each time a negative logic handshake signal ▲ ▼ is supplied to the timing input terminal, D-FF (73) (74)
The above-mentioned series of operations can be performed by switching the selection state of.

Specifically, when the horizontal synchronizing signal () is supplied as a timing input, the D-FF (71) outputs a Q output signal Q1 indicating that a read transfer or refresh request is generated. Then, the handshake signal ▲ ▼ indicating that the read transfer or the refresh has been received is received as an input, and D-
Clear the Q output signal Q1 of FF (71). Further, the Q output signal Q1 is supplied to the D input terminal (72), and the D-FF (72)
Sampling strobe signal SRCK to the clock input pin of
Is supplied, the D-FF (72) outputs a Q output signal Q2 indicating a read transfer or refresh request.
The signal Q1 is output as the signal ACDM through the OR gate (83) and is supplied to the G input terminal of the D-FF (78).
-FF (75) in this case handshake signal ▲ ▼
Is not input and the level of the Q output signal Q3 does not change, so the signals SELA and SELB for double buffer switching output from the D-FF (78) do not change. That is, the switching of the double buffer is not instructed. The signal ACDM is D-FF (7
The sampling clock signal SCK is supplied to the NAND gate (84) which is supplied to the D input terminal of 7) and is opened by the output signal (inverted signal) of the D-FF (76) and the output signal (inverted signal) of the D-FF (77). Is supplied to the clock input terminal of D-FF (77) to output a start signal indicating the start of the memory cycle from the Q output terminal of D-FF (77).

Therefore, in the case of read transfer or refresh request, read transfer or refresh can be performed in response to the start signal indicating the start of the memory cycle.

On the contrary, if it is a write cycle, the following operation is performed.

Handshake signal indicating acceptance of write cycle ▲
When ▼ is supplied, the level of the Q output signal Q3 is inverted by being supplied to the clock input terminal of the D-FF (75). However, the level of the Q output signal Q3 is inverted in the D-FF (78), and the level of the output signal is changed only when the signal ACDM supplied to the G input terminal is low level and the sampling strobe signal SRCK rises. Flipped. If the write cycle is acceptable, DDA
Is operating, the DDA pixel strobe signal D
DARCK corresponds to the corresponding D through the OR gate (80) to which the signal at the low level is provided among the signals SELA and SELB.
It is supplied to the clock input pin of -FF and is selected for holding data. Therefore, the detection flag (double buffer memory switching timing detection flag ▲ ▼) output from the circuit shown in FIG. 3 or 4 is supplied as the signal BF1 or BF2 through the NAND gate (79), so that this signal is input to the D input terminal. Capture through and hold. In addition, this signal BF1 or BF2 is simultaneously OR gate (8
3), the low level signal ACDM is output and the levels of the signals SELA and SELB are immediately inverted. After that, the other D-FF is selected for holding data and the same operation is performed. As is clear from the above, when the write cycle is accepted, the double buffer memory can be switched by immediately inverting the levels of the signals SELA and SELB based on the double buffer memory switching timing detection flag ▲ ▼. In addition to being able to output the start signal immediately, the DRAM timing control and double buffer memory switching can be performed without stopping the DDA.

FIG. 6 is a timing chart for explaining the operation of each part of the circuit of FIG. 5, in which the read transfer operation for reading the image data is performed in the period of T1, and the write operation of the image data is performed in the period of T2, T3. Has been.

Therefore, by providing the timing control circuits having the configurations shown in FIGS. 4 and 5 corresponding to each block memory, the image memory of the generated pixel data can be obtained without stopping the operation of the DDA (1). The writing operation for (3) can be sequentially performed. That is, the influence of the inclination of the drawing line segment is eliminated, and any line segment is converted into one pixel, and the image memory (3) is converted into the image memory (3) in a time equal to the calculation required time of the DDA (1). Writing can be performed.

In order to obtain an image memory of 2048 × 1024 pixels in a graphic display device, it is necessary to use a DRAM of 256 Kbit
One image memory is configured by using each one to store pixel data for one screen, and two double buffer memories each having 1 × 8 bits are used as a set. Then, as the image memory, a dual plane configuration including a plane for storing the pixel data being displayed and a plane for writing the pixel data for the next display is adopted. It consists of eight 256K-bit DRAMs.

Therefore, even if the screen memory is divided into eight block memories for each plane and the double buffer memory and the timing control circuit are provided corresponding to each block memory with the dual plane configuration as described above, This is not applicable because the input bit width of the entire image memory is small. That is, since the input bit width of the 256K-bit DRAM is set to 4 bits, the input bit width of each image memory as a whole is 32 bits.
There will only be a bit.

However, when eight 1 × 8-bit double buffer memories are provided, the bit width of the entire double buffer memory becomes 64 bits, so that it is impossible to secure a one-to-one correspondence. Since 16 DRAMs must be used for each plane, there is a problem that more memory is needed than necessary.

That is, although eight DRAMs are sufficient from the viewpoint of memory capacity, 16 DRAMs are required from the viewpoint of ensuring a one-to-one correspondence in bit width. If this structure is applied to an image memory having a dual plane structure, the required number of DRAMs will be 32.

In order to solve such a problem and to secure a dual plane configuration as an image memory and to secure a sufficient input bit width, each plane of each DRAM is not divided in each DRAM. Internally, a configuration is adopted in which each plane is partitioned and which plane is to be accessed based on the most significant bit data of the row address supplied to the DRAM (see FIG. 7A). .

FIG. 7B is a diagram for explaining in more detail, in which the timing control circuits CNT0, CNT1 ... CNT7 are provided and the double buffer memory DB corresponding to each timing control circuit is provided.
0, DB1 ... DB7 are provided, and 16 DRAM0, DRAM1 ... DRAM15 are further provided corresponding to each double buffer memory, respectively ... DRAMj-2, DRAMj-1, DRAMj, DRAMj + 1, DRAMj +
It is divided into 2 ... The even-numbered and odd-numbered DRAMs are paired to correspond to the double buffer memories, respectively, and further correspond to the timing control circuits. Of course, division of each plane (sections of A plane and B plane shown in FIG. 7A) is performed inside each DRAM. Further, each of the timing control circuits described above writes the pixel data supplied to the double buffer memory on the basis of the x-coordinate and y-coordinate high-order address data output from the DDA (1), the address data in the DRAM ... It holds j-2, j-1, j, j + 1, j + 2 ... And also holds data for selecting a plane based on the most significant digit data of the row address supplied to the DRAM. It is something to keep.

Therefore, as in the case of the above-described embodiment, the DDA is changed on condition that the least significant digit of the y coordinate has changed, the fourth digit of the x coordinate has changed, or line segment drawing has ended.
It is possible to supply the pixel data output from (1) to one of the double buffer memories, and simultaneously write the pixel data held in the other buffer memory to the corresponding DRAM. Therefore, as a whole, the time required to write data to one pixel in the DRAM can be made equal to the time required to calculate one pixel by the DDA (1).

In addition, a sufficient number (16) of DRAMs are used to adopt the dual plane configuration of the image memory, and there is a one-to-one correspondence between the input bit width of each plane and the bit width of the double buffer memory as a whole. It is possible to secure the correspondence relationship of.

As a result, the calculation operation by the DDA (1) must be stopped during the refresh operation period for the DRAM and the period during which the pixel data is read from the DRAM for display, but during the periods other than the above, the DDA (1) operation is stopped. It is possible to generate pixel data and write the generated pixel data to the DRAM without stopping the calculation operation by. Moreover, since the refresh operation period of the DRAM is predetermined, it is possible to predict it, and it is possible to deal with it by only thinning out the control clock of the DDA in advance. It is possible to further reduce the time required to write data in the image memory, because a handshake for performing the operation is unnecessary.

Further, in the above embodiment, if a dual port DRAM is used as the DRAM, the time required for reading for display can be greatly shortened, and about 98% of the time can be allocated for writing data. So as a whole,
The time required to write data to the image memory can be shortened.

It should be noted that the present invention is not limited to the above embodiment, and for example, a double buffer memory can be configured by a buffer memory of 2 × 8 bits, and a resolution required for a graphic display device can be obtained. Correspondingly, it is possible to change the storage capacity of DRAM itself, the number of DRAMs, the storage capacity of double buffer memory itself, the number of double buffer memories, and the number of timing control circuits. In the case of a large size, it is possible to partition the interior of the DRAM to form a plurality of block memories, and various design changes can be made within a range that does not change the gist of the present invention.

<Effects of the Invention> As described above, according to the present invention, the image memory is configured by a plurality of block memories, and the double buffer memory corresponding to each block memory and the double data based on the coordinate data output from the DDA are used. Since the buffer memory and the timing control means for generating the switching control signal and the selection signal for the block memory are provided, the sequential pixel data can be sequentially displayed without stopping the operation operation by the DDA except for the period in which the property of the block memory is unavoidable. Moreover, the generated pixel data can be collectively written in the image memory via the double buffer memory, and the total pixel length is 1 pixel despite the fact that the actual writing time is long. The unique effect that the writing time per hit can be made equal to the DDA calculation time To do.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an image memory writing control device, FIG. 2A is a diagram explaining an example of pixel data sequentially generated from DDA, and FIG. 2B is a block having four image memories. FIG. 3A is a diagram illustrating a data write operation corresponding to the case where the data is divided into memories, FIG. 3A is a schematic diagram showing a pipelined state of DDA, and FIG. 3B is a change in the content of a specific digit of address data. FIG. 4 is a diagram showing an example of a circuit configuration for detecting a change, FIG. 4 is a diagram showing another example of a circuit configuration for detecting a change in the content of a specific digit of address data, and FIG. 5 is a double buffer memory switching timing. FIG. 7 is a diagram showing a circuit configuration for performing DRAM timing control and double buffer memory switching based on a detection flag. FIG. 6 is a timing chart for explaining the operation of the circuit diagram of FIG. 5, FIG. 7A FIG. 7 is a diagram for explaining the plane configuration of the image memory, FIG. 7B is a diagram showing the relationship between the image memory having the configuration of FIG. 7A, a double buffer memory, and a timing control circuit. FIG. 8 is a conventional double buffer. FIG. 9 is a diagram schematically showing the system, FIG. 9 is a diagram for explaining the operation of the 1 × 8 double buffer system, and FIG. 10 is a diagram for explaining the operation of the 4 × 4 double buffer system. (1) …… DDA, (21) (22)… (2n) …… double buffer memory, (3) …… image memory, (31) (32)… (3n) …… block memory, (41) ( 42)… (4n) …… Timing control circuit

Claims (4)

[Claims] 1. A control device for writing pixel data generated by a linear interpolation calculator into an image memory, wherein the image memory comprises a plurality of block memories to which different scan lines are assigned, and each block A double buffer memory is provided corresponding to the memory, and among the coordinate data output from the linear interpolation calculator, the lower digit is decoded using the coordinate data in the direction perpendicular to the scan direction as input, and the double buffer memory is based on the decoded signal. Control that selects the block memory corresponding to this dull buffer memory, decodes the lower digit by inputting the coordinate data in the scan direction, and switches the selected double buffer memory based on the decode signal. A timing control means for generating a signal is provided. Image memory write controller. 2. The method according to claim 1, wherein the timing control means receives the drawing end signal output from the linear interpolation calculator and generates a control signal for switching the double buffer memory. Image memory writing control device. 3. The image memory according to claim 1, wherein the image memory is composed of a plurality of block memories of a predetermined size, and each block memory is divided into two to store different image data. The image memory writing control device described. 4. The image memory according to claim 1, wherein the image memory is a dual port dynamic random access memory.
Or the image memory writing control device according to item 3.