JPH0758244A - Semiconductor package and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a semiconductor package which is composed of a first printed wiring board mounted with semiconductors and a second printed wiring board where outer leads are provided corresponding to the gate terminals of the semiconductors, wherein the first and the second wiring board can be aligned with each other and connected high in reliability. CONSTITUTION:A first printed wiring board 2 and a second printed wiring board 3 are connected together to form a semiconductor package 1, wherein solder bumps 10 provided to the underside of the first printed wiring board 2 are fitted into bump holes 11 provided to the second printed wiring board 3 so as to align the printed wiring boards 2 and 3 with each other. After the printed wiring boards 2 and 3 are positioned to each other, a thermal treatment is carried out at a temperature higher than a fusing point of the bumps 10 and 14, and the bumps 10 and 14 are bonded together by fusion inside the bumps holes 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called semiconductor package for mounting a semiconductor, and more particularly to a first printed wiring board on which the semiconductor is mounted and outer leads corresponding to the respective gate terminals of the semiconductor. A semiconductor package including two wiring boards of a second printed wiring board, each first printed wiring board and the second wiring board can be aligned with each other with high accuracy, and the connection reliability between them is excellent. And a method for manufacturing the semiconductor package.

[0002]

2. Description of the Related Art Conventionally, semiconductor packages having various forms for efficiently mounting various semiconductor elements (chips) on a mother board (made of a printed wiring board) and electrically connecting them have been proposed. There is. As is conventionally known, such a semiconductor package is roughly classified into a connection system, and a pin grid in which a plurality of conductor pins serving as external connection terminals are formed from one surface of a printed wiring board forming the semiconductor package. Array (PGA) type, land (pad) grid array that uses a conductor pattern formed on one surface or side surface of a printed wiring board of a semiconductor package as an external connection terminal, leadless chip carrier (LCC) type, printed wiring of a semiconductor package Four types of types: a dual in-line package (DIP) in which external connection terminals such as lead frames are formed from two sides of the board, and a quad flat package (QFP) type in which external connection terminals are formed from four sides of the printed wiring board Exists.

By the way, in recent years, in each of the above-mentioned semiconductor packages, the number of external connection terminals per unit area has been steadily increasing along with the enhancement of the functionality and the multifunctionality of the semiconductor itself. Under such circumstances, the pin grid array type has been widely used because it is possible to provide a relatively large number of external connection terminals per unit area among the various semiconductor packages described above. When using, a large number of through holes for inserting and mounting the pins are required on the motherboard side. The presence of such through holes remarkably hinders high density wiring in a printed wiring board that constitutes a mother board, and has the drawback that the pin grid array type package itself is expensive. Therefore, recently, as a low-cost semiconductor package having external connection terminals for surface mounting, a printed wiring board formed of resin as a base and a lead frame made of copper or 42 alloy are combined. Dual in-line packages and quad flat packages are being used.

[0004]

However, even in the above-mentioned dual in-line package and quad flat package, it is necessary to provide a large number of external connection terminals as the semiconductor itself becomes highly functional and multifunctional. There is no. Therefore, in order to solve this point,
The relay pads (arranged in one row or in two rows in a staggered pattern) are formed with a very narrow pitch at the peripheral edge of the printed wiring board that constitutes each package, and match the pitch between the relay pads in the lead frame. Therefore, the pitch between the leads must also be narrowed, which makes it difficult to accurately align the relay pads with the lead frame.

When connecting each relay pad and each frame with solder, after the required amount of solder is supplied to each relay pad by a screen printing method or the like, the lead frame is aligned with the printed wiring board. Then, heat treatment is performed at a temperature equal to or higher than the melting temperature of the solder to connect each relay pad to each lead. In this way, when soldering the relay pads to the lead frame,
As described above, the pitch between the relay pads and the pitch between the leads are extremely narrow, which makes it extremely difficult to supply an appropriate amount of solder to each relay pad, and in some cases insufficient solder may occur. There is a problem that there is a possibility that a connection failure may occur due to, or a solder supply amount may become excessive and a short circuit (bridge) may occur between relay pads that are close to each other.

The present invention has been made to solve the above-mentioned conventional problems, and a second printed circuit board having a semiconductor mounted thereon and a second printed circuit provided with outer leads corresponding to respective gate terminals of the semiconductor. A semiconductor package including two wiring boards, a first printed wiring board and a second wiring board, which can be aligned with each other with high accuracy, and which has excellent connection reliability between the two. It is an object to provide a method for manufacturing a semiconductor package.

[0007]

In order to achieve the above object, a semiconductor package according to the present invention is mounted with a semiconductor chip having a plurality of gate terminals and a plurality of lands to which the respective gate terminals are connected. And having a first solder bump provided at a place electrically connected to each land
A printed wiring board, an insulating film in which a plurality of holes are formed corresponding to each of the first solder bumps, a plurality of outer leads continuously formed in the insulating film from the lower surface of each hole, and each outer lead A semiconductor package comprising a second printed wiring board which is provided above and has a second solder bump filled in a part of each hole, wherein each of the first printed wiring board and the second printed wiring board comprises: The first
The solder bumps are fitted into the holes, and the first solder bumps and the second solder bumps are melt-bonded to each other to be connected to each other.

Also, in the method of manufacturing a semiconductor package according to the present invention, a plurality of through holes are formed in the first printed wiring board, and conductors are filled and formed in each through hole,
A first step of forming a plurality of lands on one surface of a first printed wiring board corresponding to one end of each conductor, and a second step of bonding a plurality of gate terminals provided on a semiconductor chip to the respective lands A step of forming a plurality of first solder bumps on the other surface of the first printed wiring board corresponding to the other end of each conductor, and an insulating film corresponding to each of the first solder bumps A fourth step of forming a plurality of holes in the second printed wiring board made of, and a fifth step of forming a predetermined circuit pattern including a plurality of outer leads continuous from the lower surface of each hole; A sixth step of filling a part of the solder with the second solder bumps on the outer leads, and inserting the first solder bumps into the holes, the first solder bumps, and the second solder bumps. 7th process for fusion bonding with Consisting of.

[0009]

In the semiconductor package according to the present invention having the above-described structure, when the first printed wiring board having the semiconductor chip mounted thereon and the second printed wiring board having the outer leads formed thereon are connected, first the first printed wiring board is connected. By inserting the first solder bumps, which are provided in the plate, at locations where they are electrically connected to the lands to which the gate terminals of the semiconductor chip are connected, into the holes formed in the insulating film of the second printed wiring board, The first and second printed wiring boards are aligned with each other. At this time, the first and second printed wiring boards can be reliably and accurately aligned with each other by the first solder bumps and the holes.

Thereafter, the first solder bumps of the first printed wiring board and the second solder bumps filled in some of the holes of the second printed wiring board are fusion-bonded. At this time, the first solder bumps and the lands to which the gate terminals of the semiconductor chips are connected are electrically connected to each other on the first printed wiring board, and the second solder bumps and the outer leads formed on the insulating film. Since these are fused and connected, each gate terminal of the semiconductor chip in the first printed wiring board and each outer lead in the second printed wiring board are reliably connected to each other.

Further, in the method of manufacturing a semiconductor package according to the present invention, each gate terminal of the semiconductor chip is bonded to each land on the first printed wiring board through the first step and the second step, and further, the third step. By the process, the first solder bump is formed on the conductor-side surface in the through hole that is electrically connected to each land. After the fourth step to the sixth step, the second printed wiring board made of an insulating film has a plurality of holes, outer leads continuous to the lower surface of each hole, and
A second solder bump is formed on each outer lead.

Thus, the first printed wiring board and the second printed wiring board
After forming the printed wiring board, in the seventh step, the first
A semiconductor package is manufactured by fitting each first solder bump of the printed wiring board into each hole of the second printed wiring board, and melt-bonding the first solder bump and the second solder bump. Is.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the drawings. FIG. 1 is an explanatory view schematically showing in cross section two printed wiring boards that constitute a semiconductor package. In FIG. 1, a semiconductor package 1 includes a first printed wiring board 2 and a second printed wiring board 3.
And are connected to each other.

First, the first printed wiring board 2 will be described. The first printed wiring board 2 is made of a ceramic substrate and has lands 5 (two lands 5 are shown in FIG. 1) on its upper surface corresponding to a plurality of gate terminals provided on a semiconductor chip 4 described later. Have been formed). In addition, lands 6 pattern-connected to each land 5,
7 is provided. Further, through holes 8 are formed in the first printed wiring board 2 so as to correspond to the lands 5, 6, and 7, and the through holes 8 are made of molybdenum and tungsten as will be described later. The conductor 9 obtained by firing the conductive paste is filled.
In addition, the solder bumps 10 are formed on the lower end surfaces of the conductors 9, respectively.
Is provided. As a method of forming the solder bumps 10, a method of masking a portion of the first printed wiring board 2 excluding the lower end surface of each conductor 9 with a solder resist and then dipping into a solder bath, A method of selectively solder-plating, and a solder cream prepared by kneading solder particles and a binder made of flux with each conductor 9
There is a method of screen-printing on the lower end surface of, and any method can be applied in this embodiment.

A semiconductor chip 4 is bonded to a central position on the upper surface of the first printed wiring board 2, and a plurality of gate terminals provided on the upper surface of the semiconductor chip 4 and the lands 5 described above. And are connected to each other by wire bonding.

Next, a method for producing the first printed wiring board 2 having the above-described structure will be described. First, a ceramic material that will be the main body of the ceramic substrate is formed into a substrate shape, and then each through hole 8 is formed. Thereafter, each through hole 8 is filled with a conductive paste of molybdenum and tungsten and fired. As a result, a ceramic substrate is formed by filling the conductor 9 in each through hole 8. Further, a predetermined circuit pattern including the lands 5, 6, and 7 is formed on the ceramic substrate, the semiconductor chip 4 is bonded to a predetermined position on the ceramic substrate, and then the semiconductor chip 4 is provided on the semiconductor chip 4 by wire bonding. Each gate terminal and each land 5
And connect. Then, a portion of the lower surface of the ceramic substrate thus configured except the lower end surface of each conductor 9 is masked with a solder resist, and then the ceramic substrate is dipped in a solder bath. The solder bumps 10 are formed on the lower end surfaces of the conductors 9 by such dipping. In this way, the first printed wiring board 2 is produced.

Next, the second printed wiring board 3 will be described with reference to FIGS. 2 is a plan view of the second printed wiring board 3, and FIG. 3 is a rear view of the second printed wiring board 3. In each of these figures, the base material of the second printed wiring board 3 is made of a heat-resistant polyimide film (thickness: 75 μm). Bump 10
A plurality of bump holes 11 are formed corresponding to the above, and further four long holes 12 are formed around each bump hole 11.
Are formed. Further, on the lower surface of the polyimide film, the outer leads 13 are continuously extended from each bump hole 11 to the elongated hole 12 while closing the lower surface of each bump hole 11.
Is provided. Each outer lead 13 is formed by etching a copper foil bonded to the lower surface of the polyimide film, as described later.
Further, in each of the bump holes 11, solder bumps 14 are provided in order to partially fill each of the bump holes 11 from below by the same method as described above. Here, each solder bump 1
As shown in FIG. 1, 4 is in contact with each outer lead 13 continuously provided in each bump hole 11.

2 and 3, only a part of each outer lead 13 is shown, but it goes without saying that each outer lead 13 is formed so as to extend in four directions. The land 15 (see FIG. 3) formed at the end of each outer lead 13 is a land for a checker and is used when confirming whether the semiconductor chip 4 performs a predetermined operation. Is.

Next, a method for producing the second printed wiring board 3 having the above-mentioned structure will be described with reference to FIG. FIG. 4 is an explanatory diagram continuously showing a series of steps for producing the second printed wiring board 3. First, a polyimide film F having a thickness of 75 μm is prepared, and the adhesive layer 16 is applied to one surface of the film F. (FIG. 4 (A)). Then, after the adhesive layer 16 is dried so that the adhesive layer 16 is in a semi-cured state (a state in which the dried state can be confirmed by touching with a finger),
The bump holes 11 and the long holes 12 are punched by punching (FIG. 4 (B)). After this, the polyimide film F
The copper foil 17 is adhered to one surface (lower surface) through the adhesive 16 (FIG. 4C). On the surface of the copper foil 17 of the polyimide film F to which the copper foil 17 is adhered in this manner, the etching resist 18 is applied except for the portion where the predetermined circuit pattern including the outer leads 13 is formed, and the exposure of the etching resist 18 is performed. Development is performed (FIG. 4 (D)). After that, the unnecessary copper foil 17 is removed by further etching (FIG. 4 (E)), and finally the etching resist 18 is removed, followed by the same method as described above.
The second printed wiring board 3 is created by providing the solder bumps 14 in the respective bump holes 11 (FIG. 4 (F)).

Next, a method of connecting the first printed wiring board 2 and the second printed wiring board 3 which are created as described above to each other will be described. First, the solder bumps 10 provided on the lower surface of the first printed wiring board 2 and the bump holes 11 formed on the second printed wiring board 3 are arranged so as to face each other (see FIG. 1). . Then, the solder bumps 10 of the first printed wiring board 2 are fitted into the bump holes 11 of the second printed wiring board 3 to align the first and second printed wiring boards 2 and 3 with each other. . At this time, since the respective solder bumps 10 and the respective bump holes 11 perform the positioning between the first and second printed wiring boards 2 and 3, no special jig is required for the positioning, and The printed wiring boards 2 and 3 can be positioned relative to each other with high accuracy.

After the printed wiring boards 2 and 3 are positioned with respect to each other as described above, heat treatment is performed at a temperature higher than the melting temperature of the solder bumps 10 and 14 to melt both solder bumps 10 and 14 in the bump holes 11. Join. This allows the first printed wiring board 2 to pass through the solder bumps 10 and 14 respectively.
The respective lands 5, 6, 7 in and the outer leads 13 in the second printed wiring board 3 are electrically connected.

At this time, in the first printed wiring board 2, since the solder bumps 10 are provided by utilizing the entire lower surface of the wiring board 2, it is possible to increase the pitch between the solder bumps 10. And each solder bump 1
It is also possible to form a large value of 0 itself, and accordingly, it is possible to increase the pitch of the bump holes 11 in the second printed wiring board 3 to increase the pitch between the outer leads 13. is there. This allows
It is possible to reliably prevent a bridge from occurring between the outer leads 13 and a connection failure between the solder bumps 10 and 14 to improve the connection reliability.

Further, since the second printed wiring board 3 is composed of the polyimide film F having high flexibility, the stress applied to the joint portion by the solder bumps 10 and 14 can be relaxed based on the flexibility.
As a result, the connection reliability can be improved when various heat cycles are performed.

As described above in detail, in the semiconductor package 1 according to this embodiment, when the first printed wiring board 2 and the second printed wiring board 3 are connected to each other, first, the lower surface of the first printed wiring board 2 is first connected. Each solder bump 1 formed on
0 indicates each bump hole 1 provided on the second printed wiring board 3.
Since the printed wiring boards 2 and 3 are aligned with each other by fitting the printed wiring boards 1 and 2 into each other, a special jig for positioning is not required, and the printed wiring boards 2 and 3 can be accurately positioned. Mutual positioning is possible.

In addition, as described above, each printed wiring board 2,
3 After positioning each other, heat treatment is performed at a temperature equal to or higher than the melting temperature of the solder bumps 10 and 14 so that both solder bumps 10 and 14 are melt-bonded in the bump holes 11.
In addition, in the first printed wiring board 2, each solder bump 1
Since 0 is provided by utilizing the entire lower surface of the wiring board 2, the pitch between the solder bumps 10 can be increased, and the solder bumps 10 themselves can also be formed large. The second printed wiring board 3
The pitch between the outer leads 13 can be increased by increasing the pitch between the bump holes 11 in FIG. As a result, it is possible to reliably prevent a bridge from occurring between the outer leads 13 and a poor connection between the solder bumps 10 and 14, thereby improving the connection reliability.

Furthermore, since the second printed wiring board 3 is composed of the polyimide film F having high flexibility, the stress applied to the joint portion by the solder bumps 10 and 14 can be relaxed based on the flexibility.
As a result, the connection reliability can be improved when various heat cycles are performed.

The present invention is not limited to the above-mentioned embodiments, and it goes without saying that various improvements and modifications can be made without departing from the gist of the present invention. For example, although the first printed wiring board 2 is made of a ceramic substrate in the above-mentioned embodiment, it is obvious that other substrates such as a glass epoxy substrate and a paper-phenol substrate may be used. In the above embodiment, the second printed wiring board 3
However, it is obvious that various films can be applied as long as they are insulating films having heat resistance.

[0028]

As described above, the present invention comprises two wiring boards, a first printed wiring board on which a semiconductor is mounted and a second printed wiring board provided with outer leads corresponding to the respective gate terminals of the semiconductor. To provide a semiconductor package in which the first printed wiring board and the second wiring board can be aligned with each other with high accuracy and which is excellent in connection reliability between them, and a method for manufacturing the semiconductor package. Can be produced, and its effect is great.

[Brief description of drawings]

FIG. 1 is an explanatory diagram schematically showing in cross section two printed wiring boards that constitute a semiconductor package.

FIG. 2 is a plan view of a second printed wiring board 3.

FIG. 3 is a rear view of the second printed wiring board 3.

FIG. 4 is an explanatory diagram continuously showing a series of steps for producing the second printed wiring board 3.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor package, 2 ... 1st printed wiring board, 3 ... 2nd printed wiring board, 4 ... Semiconductor chip, 5, 6, 7 ... Land, 8 ... Through hole ,
9 ... Conductor, 10 ... Solder bump, 11 ... Bump hole, 13 ... Outer lead, Solder bump, F ...
・ Polyimide film

Claims (2)

[Claims] 1. A semiconductor chip having a plurality of gate terminals is mounted, a plurality of lands to which each gate terminal is connected are formed, and a first solder bump is provided at a place electrically connected to each land. A first printed wiring board; an insulating film having a plurality of holes formed corresponding to the first solder bumps; a plurality of outer leads continuously formed on the insulating film from the lower surface of each hole; A semiconductor package comprising a second printed wiring board provided on an outer lead and having a second solder bump filled in a part of each hole, wherein each of the first printed wiring board and the second printed wiring board is provided. Are connected to each other by fitting the first solder bumps into the holes and melt-bonding the first solder bumps and the second solder bumps to each other. Conductor package. 2. A plurality of through holes are formed in the first printed wiring board, conductors are filled in the respective through holes, and then a plurality of conductors are formed on one surface of the first printed wiring board corresponding to one end of each conductor. A first step of forming individual lands; a second step of bonding a plurality of gate terminals provided on a semiconductor chip to the lands; and a first printed wiring corresponding to the other end of each conductor. A third step of forming a plurality of first solder bumps on the other surface of the board, and a fourth step of forming a plurality of holes in a second printed wiring board made of an insulating film corresponding to each of the first solder bumps. A fifth step of forming a predetermined circuit pattern including a plurality of outer leads continuous from the lower surface of each hole, and filling a part of each hole with solder to form a second solder on each outer lead. A sixth step of forming bumps Wherein with the first solder bump fitted to the each well, the method of manufacturing a semiconductor package comprising a seventh step of fusion bonding the respective first solder bump and the second solder bump.