JPH0750476A - Multilayer printed wiring board - Google Patents
Multilayer printed wiring boardInfo
- Publication number
- JPH0750476A JPH0750476A JP5193800A JP19380093A JPH0750476A JP H0750476 A JPH0750476 A JP H0750476A JP 5193800 A JP5193800 A JP 5193800A JP 19380093 A JP19380093 A JP 19380093A JP H0750476 A JPH0750476 A JP H0750476A
- Authority
- JP
- Japan
- Prior art keywords
- rows
- pad
- hole
- pads
- holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は多層印刷配線板に関し、
特に実装部品の複数のリード端子を接続するため複数の
パッドとこれらパッドと接続するスルーホールとを含み
表面実装に適した多層印刷配線板に関する。FIELD OF THE INVENTION The present invention relates to a multilayer printed wiring board,
In particular, the present invention relates to a multilayer printed wiring board including a plurality of pads for connecting a plurality of lead terminals of a mounted component and through holes connected to these pads and suitable for surface mounting.
【0002】[0002]
【従来の技術】表面実装用として使用される極めて一般
的な従来の多層印刷配線板の一例(第1の例)を図3に
示す。2. Description of the Related Art FIG. 3 shows an example (first example) of a very general conventional multilayer printed wiring board used for surface mounting.
【0003】この多層印刷配線板は、絶縁材料により形
成された基板1と、この基板1の表面の部品の実装位置
にこの部品の複数のリード端子から成る複数(この例で
は2列)のリード端子列とそれぞれ対応し上記複数のリ
ード端子とそれぞれ対応して形成された複数のパッド2
から成る複数(2列)のパッド列と、これらパッド列の
所定のパッド2に対応し基板1の裏面及び内層面に形成
された所定の配線と接続する複数のスルーホール3及び
スルーホールランド3aと、これらスルーホール3及び
スルーホールランド3aと対応するパッド2とをそれぞ
れ接続する複数の配線4と、スルーホール3及びスルー
ホールランド3aとパッド2との間の配線4以外の配線
4aとを有する構造となっている。This multilayer printed wiring board has a plurality of (two rows in this example) leads consisting of a substrate 1 formed of an insulating material and a plurality of lead terminals of the component at the mounting position of the component on the surface of the substrate 1. A plurality of pads 2 respectively formed corresponding to the terminal rows and corresponding to the plurality of lead terminals.
A plurality of (two rows) pad rows and a plurality of through holes 3 and through hole lands 3a connected to predetermined wirings formed on the back surface and inner layer surface of the substrate 1 corresponding to the predetermined pads 2 of these pad rows. And a plurality of wirings 4 respectively connecting the through holes 3 and the through hole lands 3a to the corresponding pads 2, and a wiring 4a other than the wiring 4 between the through holes 3 and the through hole lands 3a and the pads 2. It has a structure.
【0004】この多層印刷配線板においては、スルーホ
ール3及びスルーホールランド3aが、部品の実装位置
や裏面及び内層面の配線位置等に合わせて、任意の位置
に形成されている。また、裏面や内層面の配線と接続し
ないパッド2に対しては、スルーホール3及びスルーホ
ールランド3aは設けられていない。In this multilayer printed wiring board, the through holes 3 and the through hole lands 3a are formed at arbitrary positions in accordance with the mounting positions of components and the wiring positions of the back surface and inner layer surface. Further, the through hole 3 and the through hole land 3a are not provided for the pad 2 which is not connected to the wiring on the back surface or the inner layer surface.
【0005】また、複数のバッド2の全てとそれぞれ対
応するスルーホールー3及びスルーホールランド3a
(以下、単にスルーホール3という)をそれぞれのパッ
ド2の近傍に設け、裏面や内層面の所定の配線と接続し
たり、それら配線と対応するパッド2との間等の接続の
良否の判定に使用する従来の多層印刷配線板の第2の列
が図4に示されている。この例では、スルーホール3は
全てパッド列の外側に配置されている。Further, the through holes 3 and the through hole lands 3a corresponding to all of the plurality of buds 2, respectively.
(Hereinafter, simply referred to as through holes 3) are provided in the vicinity of each pad 2 to connect with a predetermined wiring on the back surface or the inner layer surface, and to judge whether the connection between the wiring and the corresponding pad 2 is good or bad. A second row of conventional multilayer printed wiring boards used is shown in FIG. In this example, all the through holes 3 are arranged outside the pad row.
【0006】この第2の例では、部品の小型化等によっ
てパッド2の配列が狭ピッチ化すると、スルーホールラ
ンド3aの直径がパッド2の幅より大きい場合、はんだ
リフロー等により部品を実装する際に隣接するスルーホ
ールランド3a間ではんだブリッジが発生しやすいの
で、図5に示すように、スルーホール3をジクザク状に
配列したり(第3の例)、図6に示すように、パッド2
の幅より小さい直径のスルーホール3(この場合はスル
ーホールランド3aは含まない)を直接パッド2の形成
領域内に形成した例(第4の例、例えば特開平3−13
2092号公報参照)がある。In this second example, when the pitch of the pads 2 is narrowed due to the miniaturization of the components and the like, when the diameter of the through-hole lands 3a is larger than the width of the pads 2, when the components are mounted by solder reflow or the like. Since solder bridges are likely to occur between the through hole lands 3a adjacent to each other, as shown in FIG. 5, the through holes 3 are arranged in a zigzag pattern (third example), or as shown in FIG.
Of a through hole 3 having a diameter smaller than the width of the pad (in this case, the through hole land 3a is not included) is directly formed in the formation region of the pad 2 (fourth example, for example, JP-A-3-13).
2092).
【0007】また、図5に示された第3の例では、実装
部品の占有面積が広くなり、かつパッド2及び配線4等
の接続の良否を判定する検査の操作が煩雑になる等の理
由により、図7に示すように、スルーホール3をパッド
列の内側及び外側に交互に配置した例(第5の例)もあ
る(例えば特開平3−44994号公報参照)。Further, in the third example shown in FIG. 5, the area occupied by the mounted components is widened, and the inspection operation for judging the quality of the connection of the pad 2 and the wiring 4 is complicated and the like. Accordingly, as shown in FIG. 7, there is also an example (fifth example) in which the through holes 3 are alternately arranged inside and outside the pad row (for example, see Japanese Patent Laid-Open No. 3-44994).
【0008】[0008]
【発明が解決しようとする課題】これら従来の多層印刷
配線板は、第1の例では、スルーホール3が任意の位置
にばらばに配置されているため、CADシステムにより
配線設計を行う場合、部品実装位置を限定することが困
難であり、CAD設計に不向きであるという欠点があ
り、第2の例〜第5の例では、共にスルーホール3がパ
ッド列の外側か実装部品のリード端子の外側となる位置
に配置されており、これらスルーホール3は検査用とし
て使用されるため、スルーホール列を含めた実装部品の
占有面積が広く、部品の実装密度を高めることが困難で
あるという欠点があり、また、両面実装の場合には、一
方の面の部品実装位置のスルーホール3が他方の面の実
装部品の下に隠れないように実装部品を配置する必要が
あるため、同様に部品の実装密度を高めることが困難で
あるという欠点があった。In these first conventional multilayer printed wiring boards, the through holes 3 are arranged at arbitrary positions in the first example, so that when the wiring is designed by the CAD system, It is difficult to limit the component mounting position and is unsuitable for CAD design. In the second to fifth examples, the through holes 3 are both on the outside of the pad row or on the lead terminal of the mounted component. Since the through holes 3 are arranged on the outer side and are used for inspection, the area occupied by the mounted components including the through hole array is large, and it is difficult to increase the mounting density of the components. In the case of double-sided mounting, it is necessary to arrange the mounting components so that the through holes 3 at the component mounting positions on one surface are not hidden under the mounting components on the other surface. It has a drawback that it is difficult to increase the packing density of the.
【0009】本発明の目的は、部品の実装密度を高める
ことができ、かつ部品実装位置の限定が容易となりCA
D設計に適し配線設計の効率化ができる多層印刷配線板
を提供することにある。An object of the present invention is to increase the mounting density of components and to easily limit the mounting position of components, which makes CA
An object of the present invention is to provide a multilayer printed wiring board suitable for D design and capable of improving the efficiency of wiring design.
【0010】[0010]
【課題を解決するための手段】本発明の多層印刷配線板
は、絶縁材料により形成された基板と、この基板の表面
の部品の実装位置にこの部品の複数のリード端子から成
る複数のリード端子列とそれぞれ対応し前記複数のリー
ド端子とそれぞれ対応して形成された複数のパッドから
成る複数のパッド列と、これら複数のパッド列のそれぞ
れに対しこれら複数のパッド列の内側及び外側のうちの
一方の側でかつ少なくとも一つのパッド列に対しては内
側にそれぞれ前記複数のパッドそれぞれと対応しかつ近
接して形成された複数のスルーホールから成る複数のス
ルーホール列と、前記複数のパッドと前記複数のスルー
ホールとをそれぞれ対応して接続する複数の配線とを有
している。A multi-layer printed wiring board according to the present invention comprises a substrate formed of an insulating material, and a plurality of lead terminals formed at a mounting position of the component on the surface of the substrate. A plurality of pad rows formed of a plurality of pads respectively corresponding to the plurality of lead terminals and corresponding to the plurality of lead terminals, and for each of the plurality of pad rows, of the inner side and the outer side of the plurality of pad rows A plurality of through-hole rows formed of a plurality of through-holes formed on one side and on the inner side with respect to at least one pad row, respectively corresponding to the plurality of pads and in close proximity; It has a plurality of wirings corresponding to and connecting with the plurality of through holes.
【0011】[0011]
【実施例】次に本発明の実施例について図面を参照して
説明する。Embodiments of the present invention will now be described with reference to the drawings.
【0012】図1(a)〜(c)はそれぞれ本発明の第
1の実施例を示す表面側、内層面及び裏面側の平面図で
ある。FIGS. 1A to 1C are plan views of a front surface side, an inner layer surface and a back surface side, respectively, showing a first embodiment of the present invention.
【0013】この実施例は、絶縁材料で形成された基板
1と、この基板の表面の部品の実装位置にこの部品の複
数のリード端子から成る複数のリード端子列(この実施
例では、右側にQFP型部品の4列、左側にSOP型の
2列)とそれぞれ対応し上記複数のリード端子とそれぞ
れ対応して形成された複数のパッド2からなる複数(4
列及び2列)のパッド列と、これら複数のパッド列のそ
れぞれに対しこれら複数のパッド列の内側にそれぞれ複
数パッドそれぞれと対応しかつ近接して形成された複数
のスルーホール3及びスルーホールランド3aから成る
複数(4列及び2列)のスルーホール列と、複数のパッ
ド2と複数のスルーホール3及びスルーホールランド3
a(以下単にスルーホール3という)とを対応接続する
複数の配線4とを有する構成となっている。なお図1に
は、上記のパッド2周辺のスルーホール3及び配線4の
ほかに、その他の配線4aの中継用のスルーホール3も
示されている。In this embodiment, a board 1 formed of an insulating material and a plurality of lead terminal rows each including a plurality of lead terminals of the part at the mounting position of the part on the surface of the board (in this embodiment, to the right side) A plurality (4) of QFP type components and a plurality of pads 2 (4) formed on the left side and corresponding to the plurality of lead terminals.
Rows and two rows of pad rows, and a plurality of through holes 3 and through hole lands corresponding to and adjacent to each of the plurality of pads inside the plurality of pad rows. A plurality of rows (4 rows and 2 rows) of through holes 3a, a plurality of pads 2, a plurality of through holes 3 and a through hole land 3
and a plurality of wirings 4 correspondingly connected to a (hereinafter simply referred to as through hole 3). In addition to the through hole 3 and the wiring 4 around the pad 2, the through hole 3 for relaying the other wiring 4a is also shown in FIG.
【0014】この実施例では、スルーホール3の各列
が、パッド列の内側に配置されているので、スルーホー
ル列を含めた実装部品の占有面積はパッド列の外側の線
で囲まれた面積となり、図4〜図7に示された従来例よ
り小さくすることができ、実装密度を高めることができ
る。なお、図6に示された従来例もパット列の外側で囲
まれた面積となっているが、スルーホールの位置は実装
部品のリード端子の外側となるので、スルーホール3ま
での配線をパットを延長して形成したにすぎないので、
実質的には図4,図5,図7と同様である。In this embodiment, since each row of through holes 3 is arranged inside the pad row, the area occupied by the mounting components including the through hole row is the area surrounded by the line outside the pad row. Therefore, it can be made smaller than the conventional example shown in FIGS. 4 to 7, and the mounting density can be increased. Although the conventional example shown in FIG. 6 also has an area surrounded by the outside of the pad row, since the position of the through hole is outside the lead terminal of the mounted component, the wiring up to the through hole 3 is put. Since it was only formed by extending
Substantially the same as FIG. 4, FIG. 5, and FIG. 7.
【0015】パッド2及び配線4等の接続の良否の判定
検査は、表面側のスルーホール3は実装部品で隠れるの
で裏面側で行う。裏面側にも部品を実装する両面実装の
場合は裏面側のスルーホール列が実装部品の下に隠れな
いようにする必要がある。この場合でも、スルーホール
列はパッド列の内側に配置されているので、部品が実装
できない範囲は小さく、従って実装密度を高めることが
できる。The inspection of the quality of the connection of the pad 2 and the wiring 4 etc. is conducted on the back side because the through hole 3 on the front side is hidden by the mounted components. In the case of double-sided mounting in which components are also mounted on the back surface side, it is necessary to prevent the through-hole row on the back surface side from being hidden under the mounted components. Even in this case, since the through hole array is arranged inside the pad array, the range in which the components cannot be mounted is small, and therefore the mounting density can be increased.
【0016】図2は本発明の第2の実施例を示す平面図
である。FIG. 2 is a plan view showing a second embodiment of the present invention.
【0017】この実施例は、4列のパッド例のうちの2
列と対応するスルーホール列をパッド列の内側に、他の
2列と対応するスルーホール列は外側に配置したもので
ある。This embodiment uses two of the four row pad examples.
The through hole rows corresponding to the rows are arranged inside the pad row, and the through hole rows corresponding to the other two rows are arranged outside.
【0018】スルーホール列を全てパッド列の内側に配
置した場合、スルーホール列を含めた実装部品の占有面
積は最小となるが、周囲の実装部品の配置状態によって
は必ずしも得策といえない場合も生じる。この場合に
は、周囲の実装部品の配置状態に合わせて、スルーホー
ル列を内側,外側の何れかに配置する。ただし、複数の
スルーホール列のうちの少なくとも1列はパッド列の内
側に配置しないと実装密度の向上は期待できない。When all the through-hole rows are arranged inside the pad row, the area occupied by the mounted components including the through-hole row is minimized, but it may not always be a good idea depending on the arrangement state of the surrounding mounted components. Occurs. In this case, the through hole row is arranged on either the inside or the outside according to the arrangement state of the surrounding mounted components. However, improvement of the mounting density cannot be expected unless at least one of the plurality of through hole rows is arranged inside the pad row.
【0019】これら実施例においては、各スルーホール
3を対応するパッド2の近傍に、すなわち、パッド列の
近傍にスルーホール列が形成されているので、CADシ
ステムで配線設計を行う場合、このスルーホール列によ
り部品実装位置を限定することができ、従ってCADシ
ステムにおける配線設計が容易となる。In these embodiments, each through hole 3 is formed in the vicinity of the corresponding pad 2, that is, in the vicinity of the pad row. Therefore, when the wiring design is performed in the CAD system, the through hole row is formed. The hole mounting can limit the component mounting position, which facilitates the wiring design in the CAD system.
【0020】[0020]
【発明の効果】以上説明したように本発明は、実装部品
の複数のリード端子列とそれぞれ対応する複数のパッド
列の各パッドと接続するスルーホールからなる複数のス
ルーホール列をパッド列の近傍にかつその少なくとも1
列を、上記複数のパッド列の内側に形成した構成とする
ことにより、スルーホールを接続検査用として使用する
場合のスルーホール列を含めた実装部品の占有面積を小
さくすることができるので実装密度を高めることがで
き、また、このスルーホール列により、CADシステム
における部品実装位置の限定が容易となるので、配線設
計が容易となり、配線設計の効率化をはかることができ
る効果がある。As described above, according to the present invention, a plurality of through-hole rows, each of which has a plurality of through-holes connected to the pads of the plurality of pad rows corresponding to the plurality of lead terminal rows of the mounted component, are provided in the vicinity of the pad row. And at least one
By arranging the rows inside the plurality of pad rows, it is possible to reduce the occupied area of the mounting components including the through-hole rows when using the through-holes for connection inspection. In addition, since the through hole array facilitates limiting the component mounting position in the CAD system, the wiring design is facilitated and the efficiency of the wiring design can be improved.
【図1】本発明の第1の実施例を示す表面側、内層面及
び裏面側の平面図である。FIG. 1 is a plan view of a front surface side, an inner layer surface and a back surface side showing a first embodiment of the present invention.
【図2】本発明の第2の実施例を示す平面図である。FIG. 2 is a plan view showing a second embodiment of the present invention.
【図3】従来の多層印刷配線板の第1の例の平面図であ
る。FIG. 3 is a plan view of a first example of a conventional multilayer printed wiring board.
【図4】従来の多層印刷配線板の第2の例の平面図であ
る。FIG. 4 is a plan view of a second example of a conventional multilayer printed wiring board.
【図5】従来の多層印刷配線板の第3の例の平面図であ
る。FIG. 5 is a plan view of a third example of a conventional multilayer printed wiring board.
【図6】従来の多層印刷配線板の第4の例の平面図であ
る。FIG. 6 is a plan view of a fourth example of a conventional multilayer printed wiring board.
【図7】従来の多層印刷配線板の第5の例の平面図であ
る。FIG. 7 is a plan view of a fifth example of a conventional multilayer printed wiring board.
1 基板 2 パッド 3 スルーホール 3a スルーホールランド 4,4a 配線 1 substrate 2 pad 3 through hole 3a through hole land 4 and 4a wiring
Claims (2)
基板の表面の部品の実装位置にこの部品の複数のリード
端子から成る複数のリード端子列とそれぞれ対応し前記
複数のリード端子とそれぞれ対応して形成された複数の
パッドから成る複数のパッド列と、これら複数のパッド
列のそれぞれに対しこれら複数のパッド列の内側及び外
側のうちの一方の側でかつ少なくとも一つのパッド列に
対しては内側にそれぞれ前記複数のパッドそれぞれと対
応しかつ近接して形成された複数のスルーホールから成
る複数のスルーホール列と、前記複数のパッドと前記複
数のスルーホールとをそれぞれ対応して接続する複数の
配線とを有することを特徴とする多層印刷配線板。1. A substrate formed of an insulating material, and a plurality of lead terminal rows each composed of a plurality of lead terminals of the component at a mounting position of the component on the surface of the substrate, respectively corresponding to the plurality of lead terminals. A plurality of pad rows formed of a plurality of pads, and for each of the plurality of pad rows, one of the inner side and the outer side of the plurality of pad rows and at least one pad row Respectively connect the plurality of pads and the plurality of through holes to the plurality of through hole rows each including the plurality of through holes formed inside and corresponding to the plurality of pads, respectively. A multilayer printed wiring board having a plurality of wirings.
パッド列の内側に形成された請求項1記載の多層印刷配
線板。2. The multilayer printed wiring board according to claim 1, wherein all of the plurality of through hole rows are formed inside the plurality of pad rows.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5193800A JPH0750476A (en) | 1993-08-05 | 1993-08-05 | Multilayer printed wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5193800A JPH0750476A (en) | 1993-08-05 | 1993-08-05 | Multilayer printed wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0750476A true JPH0750476A (en) | 1995-02-21 |
Family
ID=16313989
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5193800A Pending JPH0750476A (en) | 1993-08-05 | 1993-08-05 | Multilayer printed wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0750476A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63238658A (en) * | 1987-03-26 | 1988-10-04 | Brother Ind Ltd | Character deleting method for generated document |
JPH06318204A (en) * | 1994-03-23 | 1994-11-15 | Brother Ind Ltd | Character erasing method for prepared document |
JP2021159139A (en) * | 2020-03-30 | 2021-10-11 | 株式会社藤商事 | Game machine |
JP2021159134A (en) * | 2020-03-30 | 2021-10-11 | 株式会社藤商事 | Game machine |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6290506A (en) * | 1985-10-16 | 1987-04-25 | Toyo Seikan Kaisha Ltd | Slit-width detecting apparatus for thin-sheet pipe-shaped body |
-
1993
- 1993-08-05 JP JP5193800A patent/JPH0750476A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6290506A (en) * | 1985-10-16 | 1987-04-25 | Toyo Seikan Kaisha Ltd | Slit-width detecting apparatus for thin-sheet pipe-shaped body |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63238658A (en) * | 1987-03-26 | 1988-10-04 | Brother Ind Ltd | Character deleting method for generated document |
JPH06318204A (en) * | 1994-03-23 | 1994-11-15 | Brother Ind Ltd | Character erasing method for prepared document |
JP2021159139A (en) * | 2020-03-30 | 2021-10-11 | 株式会社藤商事 | Game machine |
JP2021159134A (en) * | 2020-03-30 | 2021-10-11 | 株式会社藤商事 | Game machine |
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A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19960423 |