JPH0745839A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To control crystal grains generated from amorphous silicon by selectively implanting silicon ions in an amorphous silicon film, generating crystal seeds by heating, growing crystals by heat annealing, and then applying specific strong light to form a channel forming region of a TFT in the silicon ion implanted region. CONSTITUTION:The method for manufacturing a semiconductor device comprises the steps of forming a base film 102 of silicon oxide on a substrate 101, then forming an amorphous silicon film 103, providing a mask 104, exposing the film 103, and implanting silicon ions. Then, the method further comprises the steps of removing the mask 104, and heat annealing it to crystallize it. In this case, may crystal seeds are generated in a region 105 in which the ions are not implanted, and growth of crystals advances laterally from the region 105. The silicon film is patterned, and an insular active unit 104' of a TFT is formed. Such many active layers are formed on the substrate, visible light or infrared-rays having a peak at 0.5-4mum are applied to further aid crystallization of the active layer. Then, when the active layer region is doped with an impurity for imparting P- or N-type conductivity, a P-type and N-type channel TFT can be formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an insulating substrate such as glass,
Alternatively, a semiconductor device having a non-single-crystal silicon film provided on an insulating film formed on various substrates, such as a thin film transistor (TFT) or a thin film diode (TFD),
Further, the present invention relates to a method for manufacturing a thin film integrated circuit to which they are applied, particularly a thin film integrated circuit for an active liquid crystal display device (liquid crystal display).

[0002]

2. Description of the Related Art In recent years, semiconductor devices having TFTs on an insulating substrate such as glass, for example, active type liquid crystal display devices using TFTs for driving pixels and image sensors have been developed.

Thin film silicon semiconductors are generally used for TFTs used in these devices. The thin-film silicon semiconductor is roughly classified into two, that is, an amorphous silicon semiconductor (a-Si) and a crystalline silicon semiconductor. Amorphous silicon semiconductors are the most commonly used because they have a low manufacturing temperature, can be relatively easily manufactured by the vapor phase method, and have high mass productivity. Since it is inferior to the silicon semiconductors it has,
In order to obtain higher speed characteristics in the future, establishment of a method for manufacturing a TFT made of a crystalline silicon semiconductor has been strongly demanded. As the crystalline silicon semiconductor, polycrystalline silicon, microcrystalline silicon, amorphous silicon containing a crystalline component, semi-amorphous silicon having an intermediate state between crystalline and amorphous are known. .

As a method for obtaining these thin film silicon semiconductors having crystallinity, (1) a film having crystallinity is directly formed at the time of film formation. (2) An amorphous semiconductor film is formed and crystallized by the energy of laser light. (3) An amorphous semiconductor film is formed, and thermal energy is applied (annealed) for a long time so as to have crystallinity. That method is known.

However, whichever method is used,
Crystalline silicon having excellent characteristics comparable to single crystal silicon has not been obtained. This is because no matter which method was used, grain boundaries were generated inside the coating and there was no means for controlling them.

[0006]

SUMMARY OF THE INVENTION The present invention provides means for solving the above problems. More specifically, it is intended to control crystal grains generated from amorphous silicon and to use a specific portion of the crystal thus controlled as a channel formation region of a TFT or TFD.

[Means for Solving the Problems]

According to the present invention, silicon ions are selectively implanted into an amorphous silicon film, and then heated at 500 to 700 ° C., preferably 550 to 600 ° C. to selectively generate crystal nuclei, which is further prolonged. The crystals are grown by thermal annealing for a period of time. In this way, after crystallizing a part or all of the film, strong light irradiation (lamp annealing step),
Further, it promotes crystallinity and at the same time densifies the film quality. Then, in the thus obtained crystalline silicon film, the channel forming region of the TFT is manufactured by using the crystalline region of the region into which silicon ions are previously implanted.

[0008]

In the present invention, the selective ion implantation of silicon significantly reduces the density of crystal nucleus generation in the region where the ion implantation is performed. On the other hand, the generation density of crystal nuclei in the region where the ion implantation is not performed is the same as the conventional one. Therefore, in the thermal annealing process after the ion implantation, nuclei are generated from the region not ion-implanted, and crystals start to grow laterally from the nuclei to the ion-implanted region. The dose of ion implantation depends on the thickness of the film, but is 1 × 10 ¹⁴ to 1 × 10 ¹⁶ cm ⁻² , preferably 5 × 10 ^14.
× 10 ^{14 to} 5 × 10 ¹⁵ cm ^-2 is preferable. Moreover, it is advisable to select the acceleration energy so that the bottom surface of the film is most injected.

In the laterally crystal-grown region, there is damage due to silicon ion implantation on the film and the interface between the film and the underlying layer.
It is difficult to obtain a perfectly good crystal by annealing at 500 to 700 ° C., and many defects are contained inside. Annealing at higher temperatures is necessary to improve such defects. Moreover, it is necessary to perform annealing so as not to affect the substrate. Lamp annealing is required for this purpose.

The lamp annealing step in the present invention is specifically light from near infrared light to visible light, preferably light having a wavelength of 4 μm to 0.5 μm (for example, wavelength 1.3 μm).
Infrared light having a peak at 1) is irradiated for a relatively short time of about 10 to 1000 seconds to heat the silicon film, thereby promoting crystallinity. The wavelength of the light used is preferably absorbed by the silicon film and not substantially absorbed by the glass substrate.

Further, in such heat treatment, the silicon film is often peeled off due to a difference in coefficient of thermal expansion between the silicon film and the substrate, a difference in temperature between the surface of the silicon film and the substrate / silicon film interface, and the like. is there. In particular, this is remarkable when the area of the film is large so as to cover the entire surface of the substrate. Therefore, by dividing the membrane into a sufficiently small area, and by widening the gap between the membranes so as not to absorb excess heat,
It is possible to prevent peeling of the film. Further, since the entire surface of the substrate is not heated through the silicon film, thermal contraction of the substrate can be suppressed to the minimum.

In particular, the crystallized intrinsic or substantially intrinsic (phosphorus or boron of 10 ¹⁷ cm ⁻³ or less) silicon film absorbs visible / infrared light having a wavelength of 0.5 to 4 μm and has a thickness of 10 μm.
Far infrared light having a wavelength of m or more is absorbed by the glass substrate and heated, but when most of the wavelengths of 4 μm or less, heating of the glass is extremely small. That is, a wavelength of 0.5 to 4 μm is effective for further crystallizing the crystallized silicon film.

In the present invention, not the crystal nucleus region where silicon ions are not implanted, but the portion where the crystal grows laterally from the region is used as the channel forming region of the TFT or TFD. This is because the crystal orientation is random in the region of crystal nuclei,
Moreover, the size of the crystal grains varies. On the other hand, in the laterally grown region, the crystals are aligned in the growth direction, and the sizes of the crystals are also uniform. Therefore, the crystal orientation and the TFT
The characteristics can be improved by optimizing the direction of the drain current of.

[0014]

[Embodiment 1] In this embodiment, a P-channel TFT (PT) using a crystalline silicon film formed on a glass substrate is used.
FT) and N-channel TFT (NTFT)
This is an example of forming a circuit in which and are complementarily combined. The structure of this embodiment can be used for a switching element of a pixel electrode of an active type liquid crystal display device, a peripheral driver circuit, an image sensor and an integrated circuit.

FIG. 1 shows a sectional view of the manufacturing process of this embodiment. First, a 2000-Å-thick silicon oxide base film 102 was formed on a substrate (Corning 7059) 101 by a sputtering method. The substrate is annealed at a temperature higher than the strain temperature before or after the formation of the base film, and then gradually cooled to the strain temperature or less at 0.1 to 1.0 ° C./min. The shrinkage of the substrate in the accompanying steps (including the infrared light irradiation of the present invention) is small, and mask alignment is ready. 620-66 for Corning 7059 substrate
After annealing at 0 ° C for 1 to 4 hours, 0.1 to 1.0 ° C /
Min, preferably 0.1-0.3 ° C./min and slowly cooled to 45
It may be taken out when the temperature has dropped to 0 to 590 ° C.

After forming the base film, an intrinsic (I-type) amorphous silicon film 103 having a thickness of 300 to 1500Å, for example 800Å, is formed by plasma CVD. And
A mask 104 made of photoresist was provided. This mask 104 has a slit-shaped amorphous silicon film 1
Expose 03. That is, when the state of FIG. 1A is viewed from above, the amorphous silicon film 103 is exposed in a slit shape, and the other portions are masked. After the mask 104 is provided, an ion implantation method is performed to
Silicon ions were implanted into the amorphous silicon film 103 at a dose of × 10 ¹⁵ cm ^-2 . The acceleration voltage was 40 to 150 keV, for example, 80 keV. (Fig. 1 (A))

Next, the mask 104 was removed. Then, thermal annealing was performed at 600 ° C. for 24 hours in a nitrogen inert atmosphere (atmospheric pressure) to crystallize. At this time, many crystal nuclei were generated in the region 105 into which silicon ions were not implanted, and crystal growth proceeded from the region 105 in the lateral direction (direction parallel to the substrate) as indicated by the arrow. Area 10
A region 103 ′ sufficiently far from 5 remained amorphous. (Fig. 1 (B))

After this step, the silicon film was patterned to form a TFT island-shaped active layer 104 '. At this time, it is important that the region 105 in which crystal nuclei are generated and the amorphous region 103 ′ do not exist in the portion that will be the channel formation region. By doing so, the orientation of the silicon crystals in the active layer and the grain size can be made uniform, and T showing uniform characteristics can be obtained.
An FT can be made. The size of the active layer 104 'is determined in consideration of the channel length and the channel width of the TFT. The small size was 50 μm × 20 μm, and the large size was 100 μm × 1000 μm.

Many such active layers were formed on the substrate. And 0.5 to 4 μm, where 0.8 to 1.4 μm
Irradiation with visible / infrared light having a peak at m for 30 to 180 seconds was performed to further promote crystallization of the active layer. Temperature is 800
˜1300 ° C., typically 900 to 1200 ° C., for example 1100 ° C. Irradiation was carried out in an H ₂ atmosphere in order to improve the surface condition of the active layer. In this step, since the active layer is selectively heated, the heating of the glass substrate can be minimized. And, it is very effective in reducing defects and dangling bonds in the active layer. (Fig. 1 (C))

A halogen lamp was used as a visible / infrared light source. The intensity of visible / near infrared light was adjusted so that the temperature on the single crystal silicon wafer of the monitor was 800 to 1300 ° C, typically 900 to 1200 ° C. Specifically, the temperature of the thermocouple embedded in the silicon wafer was monitored and fed back to the infrared light source. In this embodiment, the temperature rising / falling temperature is as shown in FIG.
It carried out like (A) or (B). The temperature rise is constant, the speed is 50 to 200 ° C / sec, and the temperature fall is 20 by natural cooling.
Was ~ 100 ° C.

FIG. 4A shows a general temperature cycle, which is composed of three processes of a temperature raising time a, a holding time b, and a temperature lowering time c. However, in this case, since the sample is rapidly heated and cooled from room temperature to a temperature as high as 1000 ° C., and further from a high temperature state to room temperature, it has a great influence on the silicon film and the substrate, and the silicon film may be peeled off. high. In order to solve this problem, as shown in FIG. 4B, a preheat time d or a postheat time f is provided before reaching the holding time, and a substrate or a film at 200 to 500 ° C. is provided before reaching the holding time. It is desirable to keep the temperature so that it does not have a great influence.

During the irradiation of infrared light, it is preferable to form a silicon oxide or silicon nitride film as a protective film on the surface thereof. This is to improve the surface condition of the silicon film 104 '. Further, in order to improve the state of the surface of the silicon film 104 ', it was performed in an H ₂ atmosphere. H ₂
0.1 to 10% of HCl, other hydrogen halides, compounds of fluorine, chlorine, or bromine may be mixed in the atmosphere.

Since this visible / near-infrared light irradiation selectively heats the crystallized silicon film, the heating of the glass substrate can be minimized. And, it is very effective in reducing defects and intangible bonds in the silicon film. In addition, it is important that this visible / near-infrared light irradiation is performed after the crystallization step by heating. When the amorphous silicon film was suddenly irradiated with infrared light without being crystallized by thermal annealing in advance, good crystals were not obtained.

Next, a thickness of 10 is obtained by the plasma CVD method.
A 00Å silicon oxide film 106 was formed as a gate insulating film. TEOS (tetra-ethoxy-silane, Si (OC ₂ H ₅ ) ₄ ) and oxygen are used as source gases for CVD,
The substrate temperature during film formation is 300 to 550 ° C., for example 400 ° C.
And After forming the silicon oxide film 106 to be the gate insulating film, the optical annealing by irradiation with visible / near infrared light was performed again. By this annealing, mainly the silicon oxide film 10
The level at the interface between 6 and the silicon film 104 and its vicinity could be eliminated. This is extremely useful for an insulating gate type field effect semiconductor device in which the interface characteristics between the gate insulating film and the channel formation region are extremely important.

Subsequently, by the sputtering method,
A film of aluminum (containing 0.01 to 0.2% scandium) having a thickness of 6000 to 8000Å, for example, 6000Å was formed. Then, the aluminum film was patterned to form the gate electrodes 107 and 109. Further, the surface of the aluminum electrode was anodized to form oxide layers 108 and 110 on the surface. This anodic oxidation was performed in an ethylene glycol solution containing 1-5% tartaric acid. The resulting oxide layers 108, 110 have a thickness of 200.
It was 0Å. The oxides 108 and 110 are
The thickness of the offset gate region is formed in the subsequent ion doping process, so that the length of the offset gate region can be determined by the anodizing process.

Next, the gate electrode portion, that is, the gate electrode 107 and the oxide layer 108 around the gate electrode 107, and the gate electrode are formed in the active layer region (which constitutes the source / drain and the channel) by the ion doping method (also called plasma doping method). 109 and the oxide layer 110 around it as a mask,
Impurities that impart P or N conductivity type were added in a self-aligned manner. As doping gas, phosphine (PH
₃ ) and diborane (B ₂ H ₆ ) are used, and the acceleration voltage is 60 to 90 kV, for example 80 kV in the former case, and 40 to 80 kV, for example 65 kV in the latter case. The dose amount was 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, phosphorus was 2 × 10 ¹⁵ cm ⁻² and boron was 5 × 10 ¹⁵ . Upon doping, one region was covered with a photoresist to selectively dope each element. As a result, N-type impurity regions 114 and 116 and P-type impurity regions 111 and 113 are formed, and a P-channel type TFT (PTFT) region and an N-channel type TFT (NT) are formed.
It was possible to form a region with FT).

After that, annealing was performed by irradiation with laser light. As the laser light, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was used, but another laser may be used. The laser beam irradiation condition is such that the energy density is 200 to 400 mJ / cm.
² , for example, 250 mJ / cm ² and 2 per place
Irradiation was performed for 10 shots, for example 2 shots. The effect may be increased by heating the substrate to about 200 to 450 ° C. during the irradiation of the laser light. (Fig. 1
(D))

Further, this step may be performed by lamp annealing with visible / near infrared light. In the visible / near infrared, crystallized silicon, or phosphorus or boron is 10 ¹⁹ to 10 10.
It is easily absorbed by the amorphous silicon added with ²¹ cm ^-3.
Effective annealing comparable to thermal annealing at 000 ° C. or higher can be performed. When phosphorus or boron is added, the light is sufficiently absorbed even in the near infrared due to the impurity scattering. This can be fully inferred because it is black even when observed with the naked eye. On the other hand, since it is difficult to be absorbed by the glass substrate, it does not require heating the glass substrate to a high temperature and requires only a short treatment time, so it can be said that it is the optimal method in the process where shrinkage of the glass substrate is a problem. .

Subsequently, a silicon oxide film 11 having a thickness of 6000Å
8 was formed by the plasma CVD method as an interlayer insulator. As this interlayer insulator, polyimide or a two-layer film of silicon oxide and polyimide may be used. Further, a contact hole is formed, and a TFT electrode / wiring 1 is formed of a metal material, for example, a multilayer film of titanium nitride and aluminum.
17, 120, 119 were formed. Finally, anneal at 350 ° C. for 30 minutes in a hydrogen atmosphere of 1 atm, and
We have completed a semiconductor circuit that has a complementary structure. (Fig. 1
(E) In particular, in the present invention, the dangling bonds generated in the step of photo-annealing by visible / near infrared light are neutralized in the subsequent step by heating at 250 to 400 ° C. in a hydrogen atmosphere. This is very important.

The circuit shown above has a CMOS structure in which PTFT and NTFT are provided in a complementary type. In the above process, two independent TFTs are simultaneously formed by simultaneously forming two TFTs and cutting them at the center. It is also possible to produce.

[Embodiment 2] This embodiment is an example in which an N-channel TFT is provided in each pixel as a switching element in an active liquid crystal display device. Although one pixel will be described below, a large number of pixels (generally several hundreds of thousands) are formed in the same structure. Also, N
It goes without saying that not only the channel type TFT but also the P channel type TFT may be used. Further, instead of being provided in the pixel portion of the liquid crystal display device, it can be used in the peripheral circuit portion. It can also be used for image sensors and other devices. That is, if it is used as a thin film transistor, its use is not particularly limited.

The outline of the manufacturing process of this embodiment is shown in FIG.
In this embodiment, Corning 70 is used as the substrate 201.
59 glass substrate (thickness 1.1 mm, 300 x 400 m
m) was used. First, the base film 202 (silicon oxide) was formed to a thickness of 2000 Å by the plasma CVD method. CVD
TEOS and oxygen were used as the raw material gas. After forming the base film, a thickness of 300 to 150 is formed by a plasma CVD method.
Intrinsic (I-type) amorphous silicon film 2 of 0Å, for example, 800Å
03 was deposited. Then, a mask 204 formed of photoresist was provided. Furthermore, silicon ions were implanted into the amorphous silicon film 103 at a dose of 1 × 10 ¹⁵ cm ^-2 by the ion implantation method. Acceleration voltage is 40-150
KeV, for example, 80 keV. (Fig. 2 (A))

After that, the photoresist mask 204 was removed, the amorphous silicon film 203 was dehydrogenated at 450 ° C. for 1 hour, and then crystallized by heating annealing.
This annealing step was performed at 600 ° C. for 48 hours in a nitrogen atmosphere. In this annealing step, since the region 205 under the photoresist mask 204 was not doped with silicon ions, crystallization started from this portion.
During this crystallization, the growth expanded from the region 205 in the lateral direction, as indicated by the arrow in FIG. Area 203 '
Is an uncrystallized region. (Fig. 2 (B))

After this thermal annealing step, the crystallized silicon film was patterned to leave only the island-shaped active layer 205 'of the TFT, and the others were removed. At this time, it is important that the region 205 in which crystal nuclei are generated does not exist in the active layer, especially in the channel formation region. Of course, it is not desirable that the uncrystallized region 203 'also exists in the channel formation region. That is, the silicon film 203 of FIG.
Among them, at least the uncrystallized region 203 ′ and the region 205 in which crystal nuclei are generated are removed by etching, and the intermediate portion of the crystalline silicon film 203, which is crystal-grown in a direction parallel to the substrate, is used as an active layer. Is preferred. This is because the orientation and size of the crystal grains in the region 205 where the crystal nuclei are generated are random. After patterning in this manner, the island-shaped active layer 205 ′ was irradiated with visible / near infrared light and annealed by light. The temperature was 1100 ° C. and the time was 30 seconds. (Fig. 2 (C))

Further, tetra ethoxy silane (TEO
S) as a raw material by a plasma CVD method in an oxygen atmosphere by a silicon oxide gate insulating film (thickness 70 to 120 n
m, typically 120 nm) 206. The substrate temperature was 350 ° C. Next, a well-known film containing polycrystalline silicon as a main component was formed by a CVD method and patterned to form a gate electrode 207. Phosphorus is added to polycrystalline silicon in an amount of 0.1 to 5 as an impurity in order to improve conductivity.
% Introduced.

After that, phosphorus is implanted as an N-type impurity by an ion doping method to self-align with the source region 20.
8, the channel formation region 209, and the drain region 210 were formed. Then, by irradiating the KrF laser beam, the crystallinity of the silicon film whose crystallinity was deteriorated due to the ion implantation was improved. At this time, the energy density of the laser light was set to 250 to 300 mJ / cm ² . By this laser irradiation, the sheet resistance of the source / drain of this TFT became 300 to 800 Ω / cm ² . Also,
This step may be performed by visible / near infrared lamp annealing. (Fig. 2 (D))

After that, an interlayer insulator 211 is formed of silicon oxide or polyimide, and the pixel electrode 212 is further formed.
Was formed of ITO. Then, a contact hole is formed, and chromium /
The electrodes 213 and 214 were formed of an aluminum multilayer film, and one of the electrodes 214 was connected to the ITO 212. Finally, hydrogenation was performed by annealing in hydrogen at 200 to 400 ° C. for 2 hours. In this way
The TFT is completed. This step is simultaneously performed on many other pixel regions at the same time. In addition, in order to further improve the moisture resistance, a passivation film may be formed on the entire surface with silicon nitride or the like. (Fig. 2 (E))

The TFT manufactured in this example uses a crystalline silicon film that has been crystal-grown in the carrier flow direction as an active layer forming a source region, a channel formation region, and a drain region. Since the carriers do not traverse, that is, the carriers move along the crystal grain boundaries of needle-like crystals, a TFT with high carrier mobility can be obtained. TFT manufactured in this example
Is an N-channel type, and its mobility is 90 to 130.
(Cm ² / Vs). The movement to the N-channel TFT using the crystalline silicon film obtained by the crystallization by the conventional thermal annealing without paying attention to the size and direction of the crystal is 50
Compared ~70 (cm ² / Vs) and was the thing, which is the improvement of the big characteristics. Further, unless annealing by irradiation of visible / near infrared light is performed after the crystallization step by thermal annealing, generally only mobility and low on / off ratio can be obtained. From this, it was found that the crystallization promoting step by intense light irradiation is useful for improving the reliability of the TFT.

[Embodiment 3] This embodiment will be described with reference to FIG. First, a base film 302 is formed on a glass substrate 301, and then a thickness of 300 to 8 is formed by a plasma CVD method.
A 00Å amorphous silicon film 303 was formed. Then, using the photoresist mask as in the first embodiment, silicon ions are selectively implanted, and further, 600 ° C., 4
The silicon film 303 was crystallized by performing heat annealing for 8 hours. At this time, as indicated by the arrow, crystal growth proceeded in the lateral direction from the region 304 where silicon ions were not implanted. The region 303 'is an uncrystallized region. (Fig. 3
(A))

Next, the silicon film 303 is patterned,
Island-shaped active layer regions 305 and 306 were formed. At this time, the region indicated by 304 in FIG. 3A is a region in which silicon ions are not implanted, and the size and direction of crystal grains are random. Therefore, also in this embodiment, the active layer regions 305 and 306, which are regions for forming active elements such as TFTs, are patterned while avoiding the region 304. The etching of the active layer was performed by the RIE method having anisotropy in the vertical direction. (Fig. 3
(B))

Then, a silicon oxide or silicon nitride film 307 having a thickness of 200 to 3000 Å was formed by the plasma CVD method. Then, as in Example 1, lamp annealing of visible / near infrared light was performed. The conditions were the same as in Example 1. In this embodiment, when irradiating visible / near infrared light,
Since a protective film of silicon oxide or silicon nitride is formed on the surface of the active layer, it was possible to prevent the surface from being roughened or contaminated during infrared light irradiation. (Fig. 3 (C))

After irradiation with visible / near infrared light, the protective film 307 was removed. After that, the gate insulating film 30 is formed as in the first embodiment.
8. Form gate electrodes 309 and 310 (FIG. 3D)
Then, an interlayer insulator 311 was formed, a contact hole was formed therein, and metal wirings 312, 313, and 314 were formed. (FIG. 3E) In this way, a complementary TFT circuit was formed. In this embodiment, a protective film is formed on the surface of the active layer upon irradiation with visible / near infrared light, so that the surface is prevented from being roughened or contaminated. Therefore, the characteristics (electric field mobility and threshold voltage) and reliability of the TFT of this example were extremely good.

[0043]

The crystallinity of the crystalline silicon film, which has been crystallized in the lateral direction by the silicon ion implantation and the thermal annealing, by additionally performing the optical annealing of visible / near infrared light irradiation, the crystallinity can be improved. Further improvement was made and at the same time the film quality could be densified, and a silicon film having good crystallinity could be obtained. Further, after forming an insulating film on the silicon film, annealing can be performed by irradiation of infrared light to reduce the interface state. After these steps, hydrogenation annealing can be performed in a hydrogen atmosphere. 200-450
The unbonded hands could be removed and neutralized by the treatment at ℃. As described above, the present invention is extremely effective in forming an insulating gate type semiconductor device.

[Brief description of drawings]

1A to 1C show steps of manufacturing a TFT of Example 1. FIG.

FIG. 2 shows a process of manufacturing a TFT of Example 2.

FIG. 3 shows a manufacturing process of a TFT of Example 3.

FIG. 4 shows an example of temperature setting according to the first embodiment.

[Explanation of symbols]

 Reference Signs List 101 glass substrate 102 base film (silicon oxide film) 103 silicon film 103 'uncrystallized silicon region 104 mask 104' island silicon film (active layer) 105 region where crystal nuclei occur 106 gate insulating film (silicon oxide film) 107 , 109 Gate electrodes (aluminum) 108, 110 Anodized layers (aluminum oxide) 111, 114 Source (drain) regions 112, 115 Channel formation regions 113, 116 Drain (source) regions 117, 119 Electrodes 118 Interlayer insulators 120 electrodes

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/26 21/268 Z 8617-4M 27/12 R

Claims (4)

[Claims] 1. A first step of forming an amorphous silicon film on a substrate, and a second step of selectively implanting silicon ions into the amorphous silicon film.
And a third step of crystallizing the amorphous silicon film by heat annealing, and irradiating the amorphous silicon film with near infrared or visible light, preferably strong light having a wavelength of 4 μm to 0.5 μm. A fourth step of promoting crystallization by performing the above step, and a channel formation region is formed by using the crystal region in which silicon ions are implanted in the second step of the silicon film which is wholly or partially crystallized in the above step. A fifth step of forming, a method for manufacturing a semiconductor device, comprising: 2. The insulating property according to claim 1, which covers the island-shaped non-single-crystal semiconductor silicon film after the second step or the third step and transmits strong light used in the fourth step. Forming a film of the semiconductor device. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the insulating film is a film containing silicon nitride or silicon oxide as a main component. 4. The method according to claim 1, after the fourth step,
A method of manufacturing a semiconductor device, comprising a step of neutralizing dangling bonds of silicon by thermal annealing at 200 to 450 ° C. in a hydrogen atmosphere.