JPH0744531A - Arithmetic device - Google Patents

Abstract

PURPOSE:To conduct the processing of obtaining an autocorrelation function of array data subjected to arithmetic operation processing at a high speed with a less step number by writing array data subjected to arithmetic operation processing to 1st and 2nd storage means simultaneously by a write means. CONSTITUTION:Array data stored in a memory 1 are read and shifted left by a barrel shifter 7 and stored tentatively in a latch circuit 10 via a register 9 and a bus 3. While a write control section 11 outputs a write signal 12 of the memory 1 and a write signal 13 of a memory 2, the section 11 commands write of an output of the latch circuit 10 to the memories 1, 2 to store the array data after scaling processing to both the memories 1, 2 simultaneously. Then the array data are read simultaneously from the memories 1, 2 and product sum is calculated by using a multiplier 5, an ALU 8 and a register 9. Thus, the processing of transferring the array data after scaling processing from the memory 1 to the memory 2 is not required.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit for calculating an autocorrelation function of array data inside a digital signal processor.

[0002]

2. Description of the Related Art In recent years, digital signal processors (DSPs) have been widely used in digital mobile communication devices such as mobile phones. In such a DSP, when performing a voice encoding process or the like, a calculation for obtaining an autocorrelation function of array data represented by the following equation (Equation 1) is often performed.

[0003]

[Equation 1]

In this case, a DSP used for a mobile phone or the like
In order to reduce the cost, fixed point arithmetic is performed. In that case, before execution of the multiply-accumulate operation of (Equation 1), in order to prevent a digit loss during multiplication, all x [n] are left-shifted by the same shift number and scaling is performed again.
It may be calculated as [n].

Next, such a conventional arithmetic unit will be described. FIG. 3 is a block diagram showing the configuration of a conventional arithmetic unit. In FIG. 3, this arithmetic unit is connected to memories 1 and 2 for storing data x [n], a memory 1, a bus line 3 for supplying data and storing an arithmetic result, and a memory 2. And a multiplier 5 for multiplying the data on the bus lines 3 and 4
And a multiplexer 6 for selecting and outputting either the value of the bus line 3 or the output of the multiplier 5. Further, this arithmetic unit shifts the output of the multiplexer 6 or outputs it as it is, and an ALU (Arith (Arith) that outputs the barrel shifter 7 through the output of this barrel shifter 7 as it is (through) or the output of the register 9.
metic and logic unit) 8, a register 9 that holds the output of this ALU 8 and outputs it to the left input of the ALU 8 or the bus line 3, and a memory 9 that holds the value of the bus line 3
2 and a latch circuit 10 for outputting to 2.

Next, the operation of autocorrelation function calculation in the configuration of this conventional example will be described. Where x [n] is
It is assumed that it is stored in the memory 1, and the following processing is performed. (1) x [n] Scaling Process x [n] is left-shifted to prevent digit loss during multiplication.
First, x [n] data is read from the memory 1 and left-shifted by the predetermined number of bits by the barrel shifter 7 through the bus line 3 and the multiplexer 6. The ALU 8 passes the output of the barrel shifter 7 as it is and stores it in the register 9. Next, the output of the register 9 is temporarily stored in the latch circuit 10 through the bus line 3 and is stored again in the memory 1 as x [n] data. (2) Transfer processing of x [n] In order to perform high-speed processing of the multiply-accumulate operation of (Equation 1), it is desirable that the data of x [n] and x [n + m] can be read simultaneously from the memories 1 and 2. For that purpose, (1) the same x stored in the memory 1 is stored in the scaling process of x [n].
The array data of [n] must also exist in the memory 2. Therefore, the data of x [n] is sequentially read from the memory 1, and the memory 2 is read through the bus line 3 and the latch circuit 10.
Write in. (3) Clearing the register 9 The output of the register 9 is input to the left side of the ALU 8 and at the same time to the right side of the ALU via the bus line 3, the multiplexer 6 and the barrel shifter 7. The ALU 8 performs subtraction, outputs a value 0, and stores it in the register 9. (4) Sum of products operation processing The value of x [n] is read from the memory 1 and input to the right side of the multiplier 5 through the bus line 3. At the same time, the value of x [n + m] is read from the memory 2 and input to the left side of the multiplier 5 via the bus line 4. The multiplier 5 performs multiplication, and the result is passed through the multiplexer 6 and barrel shifter 7 to the ALU.
Enter on the right side of 8. The ALU 8 adds the output of the barrel shifter 7 and the output of the register 9 and stores the result in the register 9. By repeating such processing L times, the autocorrelation function R represented by (Equation 1) can be obtained.

[0007]

However, the above-described conventional arithmetic device requires a process of transferring the array data which has been subjected to the scaling process from the memory 1 to the memory 2. Therefore, there is a drawback that the calculation of the autocorrelation function cannot be performed at high speed.

The present invention solves such a conventional problem, and an object of the present invention is to provide an excellent arithmetic unit capable of executing autocorrelation function calculation processing at a high speed with a small number of steps.

[0009]

In order to achieve the above object, the arithmetic unit of the present invention stores first and second storage means for storing data, and the first and second storage means. It is configured to include at least an arithmetic means for performing a sum-of-products operation on the data and a writing means for simultaneously writing the outputs from the arithmetic means to the first and second storage means.

Further, first and second storage means for storing data, operation means for performing at least multiply-accumulate operation on the data stored in the first and second storage means, and data from the outside The input means for inputting and the writing means for simultaneously writing the data input from the inputting means into the first and second storage means are provided.

[0011]

With such a configuration, in the arithmetic unit according to the first aspect of the invention, the writing means writes the array data subjected to the arithmetic processing to the first and second storage means at the same time,
Also, the process of transferring the array data to the second storage means is unnecessary. Therefore, the processing for obtaining the autocorrelation function is executed at high speed with a small number of steps for the array data that has been subjected to the arithmetic processing.

In the arithmetic unit according to the second aspect of the invention, the writing means simultaneously writes the data input by the input / output device into the first and second storage means. Therefore,
The process of obtaining the autocorrelation function for the array data input from the outside is executed at high speed with a small number of steps.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the arithmetic unit of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a first embodiment of an arithmetic unit according to the present invention. In the following text and drawings, the same constituent elements in the previous FIG. 3 are designated by the same reference numerals. In FIG. 1, this arithmetic unit is connected to memories 1 and 2 for storing data x [n], a memory 1, a bus line 3 for supplying data and storing an arithmetic result, and a memory 2. It has a bus line 4 for supplying data and a multiplier 5 for multiplying the data on the bus lines 3, 4. Further, this arithmetic unit selects the value of the bus line 3 or the output of the multiplier 5 and outputs it, and the barrel shifter 7 that shifts the output of the multiplexer 6 or outputs it as it is, and the barrel shifter 7 It has an ALU 8 for passing the output of the above as it is or for performing an arithmetic logic operation with the output of the register 9 and outputting. Furthermore, this arithmetic unit
A register 9 that holds the output of the LU 8 and outputs it to the left side input of the ALU 8 or the bus line 3, and a latch circuit 10 that holds the value of the bus line 3 and outputs it to the memory 1 and the memory 2.
And a write controller 11 for outputting a write signal S12 for the memory 1 and a write signal S13 for the memory 2 to the memory 1 and the memory 2, respectively.

Next, the operation of autocorrelation function calculation in the configuration of the first embodiment will be described.

The equation for calculating the autocorrelation function here is the same as the previous equation (1). Then, it is assumed that x [n] is stored in the memory 1, and the following processing is performed. (1) Scaling process of x [n] First, x [n] is left-shifted in order to prevent digit cancellation during multiplication. Then, the data of x [n] is read from the memory 1 and left-shifted by a predetermined number of bits by the barrel shifter 7 through the bus line 3 and the multiplexer 6. AL
U8 passes the output of the barrel shifter 7 as it is and stores it in the register 9. Next, the output of the register 9 is temporarily stored in the latch circuit 10 through the bus line 3. The write control unit 11 outputs the write signal S12 of the memory 1 and the write signal S13 of the memory 2, and instructs the memory 1 and the memory 2 to write the output of the latch circuit 10. X [n]
Data is stored in both the memory 1 and the memory 2. (2) Clear processing of register 9 The output of the register 9 is input to the left side of the ALU 8 and simultaneously to the right side of the ALU 8 through the bus line 3, the multiplexer 6 and the barrel shifter 7. The ALU 8 performs subtraction, outputs a value 0, and stores it in the register 9. (3) Product-sum operation processing The value of x [n] is read from the memory 1 and input to the right side of the multiplier 5 via the bus line 3. At the same time, the value of x [n + m] is read from the memory 2 and input to the left side of the multiplier 5 via the bus line 4. The multiplier 5 performs multiplication, and the result is passed through the multiplexer 6 and barrel shifter 7 to the ALU.
Enter on the right side of 8. The ALU 8 adds the output of the barrel shifter 7 and the output of the register 9 and stores the result in the register 9. By repeating such processing L times, the autocorrelation function R represented by (Equation 1) can be obtained.

As described above, according to this embodiment, the write controller 11 outputs the write signal S12 of the memory 1 and the write signal S13 of the memory 2 at the end of the scaling process of x [n] in (1). Then, the memory 1 and the memory 2 are instructed to write the output of the latch circuit 10. Therefore, the data of x [n] after the scaling processing can be stored in both the memory 1 and the memory 2, and the array data of x [n] after the scaling processing is transferred from the memory 1 to the memory 2. No processing is required. That is, the conventional process of obtaining the autocorrelation function shown in (Equation 1) is
A small number of steps and high-speed execution are possible.

Next, a second embodiment will be described. FIG. 2 is a schematic block diagram showing the configuration of the second embodiment.
In FIG. 2, this arithmetic unit has an input / output unit 14 for outputting data input from the outside to the bus line 3 in addition to the configuration of the first embodiment shown in FIG. The arranged array data can be simultaneously written in the memories 1 and 2 through the bus line 3 and the latch circuit 10.

Next, the operation of the configuration of the second embodiment will be described. (1) Input processing of x [n] First, the input / output unit 14 externally inputs the data of x [n] from the outside.
Each word is fetched and output to the bus line 3. The latch circuit 10 temporarily stores this value and stores it in the memory 1 and the memory 2.
Output to. The write control unit 11 outputs the write signal S12 of the memory 1 and the write signal S13 of the memory 2, and instructs the memories 1 and 2 to write the output of the latch circuit 10. And x input from outside
The data of [n] is stored in both the memory 1 and the memory 2. By repeating such processing for the number of data L, the array data of L x [n] is stored in the memory 1 and the memory 2.
Stored in both. (2) Area processing of register 9 The output of the register 9 is input to the left side of the ALU 8 and also to the right side of the ALU 8 through the bus line 3, the multiplexer 6 and the barrel shifter 7. The ALU 8 performs subtraction, outputs a value 0, and stores it in the register 9. (3) Product-sum operation processing The value of x [n] is read from the memory 1 and input to the right side of the multiplier 5 via the bus line 3. At the same time, the value of x [n + m] is read from the memory 2 and input to the left side of the multiplier 5 via the bus line 4. The multiplier 5 performs multiplication, and the result is passed to the ALU 8 via the multiplexer 6 and the barrel shifter 7.
To the right of. The ALU 8 adds the output of the barrel shifter 7 and the output of the register 9 and stores the result in the register 9.

By repeating such processing L times, the autocorrelation function R represented by (Equation 1) can be obtained.

[0021]

As is apparent from the above description, in the arithmetic unit according to the first aspect of the present invention, the writing means writes the array data subjected to the arithmetic processing to the first and second storage means at the same time. Also, since the process of transferring the array data to the second storage unit is not required, there is an effect that the process of obtaining the autocorrelation function can be executed at high speed with a small number of steps for the array data that has been subjected to the arithmetic processing.

Further, in the arithmetic unit according to the second aspect of the present invention, since the writing means simultaneously writes the data inputted by the input / output device to the first and second storage means, the array data inputted from the outside is Thus, the processing for obtaining the autocorrelation function can be executed at high speed with a small number of steps.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of an arithmetic unit according to the present invention.

FIG. 2 is a schematic block diagram showing the configuration of the second embodiment.

FIG. 3 is a block diagram showing a configuration of a conventional arithmetic unit.

[Explanation of symbols]

 1, 2 memory 3, 4 bus line 5 multiplier 6 multiplexer 7 barrel shifter 9 register 8 ALU 10 latch circuit 11 write control unit 14 input / output unit

Claims (2)

[Claims] 1. A first and second storage means for storing data, an operation means for performing at least a sum of products operation on the data stored in the first and second storage means, and the operation means. And a writing means for writing the output of the above into the first and second storage means at the same time. 2. A first and second storage means for storing data, an operation means for performing at least a product-sum operation on the data stored in the first and second storage means, and data from the outside. An arithmetic unit comprising: input means for inputting; and writing means for simultaneously writing data input from the input means to the first and second storage means.