JPH0743932B2 - Semiconductor device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a highly integrated semiconductor device.

[Background of the Invention]

As semiconductor devices become highly integrated, power consumption Pd and transient power supply current I _T increase, which is a serious obstacle to high integration in the future. In particular, an increase in I _T causes an increase in noise inside the semiconductor device, a printed circuit board on which the semiconductor device is mounted, or an electronic device as a whole including a large number of semiconductor devices, which is an important problem. In particular, it is important to reduce the peak current value I _P of I _T in order to reduce noise. It is effective to reduce the power supply voltage as a solution to this problem, but from the viewpoint of compatibility with conventional systems and ease of use, there is a demand from the user to keep the power supply voltage constant regardless of the degree of integration. strong. Therefore, it is not a good idea to lower the power supply voltage than the conventional one for the above purpose.

Therefore, the power supply voltage input from the outside is kept the same as the conventional one, and the power supply voltage from the outside is dropped to a constant voltage by the voltage conversion circuit provided inside the semiconductor chip to operate the entire chip or a part thereof. A method can be considered. This method is disclosed mainly in Japanese Patent Application Nos. 56-57143, 56-168698, 57-220083 and the like for the purpose of operating a semiconductor device using a fine element having a low breakdown voltage at the same power supply voltage as the conventional one having a higher breakdown voltage. Has been done.

FIG. 1 is a diagram showing the basic concept of the method disclosed above. In FIG. 1, 1 is a semiconductor chip made of silicon or the like, 2a and 2b are internal circuits, and 2a is an external power supply voltage.
The voltage conversion circuit 11 operates V _EXT , 2b at V _INT, which is V _EXT dropped to a constant voltage. Reference numerals 4 and 5 schematically show the external and internal signal paths, respectively. The eleven specific configurations are disclosed in the above-mentioned prior application.

FIG. 1 (B) schematically shows the effect of reducing the transient power supply current by adopting the above method. In the figure, the broken _lines i _E0 , i _a0 , i _b0 are the power supply voltage V _EXT
Total power supply current when operated directly at, current flowing in 2a,
The currents flowing in 2b are shown respectively. Here, for the sake of simplicity, it is assumed that i _a0 and i _b0 flow simultaneously and their values are equal. The current waveform is also approximated by a triangle. Here, when the operating voltage of 2b is V _INT , the current flowing in 2b becomes small as i _b = (V _INT / V _EXT ) i _b0 = αi _b0 as shown by the solid line, and the total current also changes accordingly. It becomes smaller and becomes as shown by the solid line i _E = i _a0 + i _{b in} the figure.

Now, _assuming that i _a0 = i _b0 , the effect of reducing the power supply current in the system of FIG. Therefore, the current reduction effect of 2b is halved as a whole. That is, even if α = 0.8, the effect is i
_E = 0.9i _E0 , which only contributes 10%. If V _INT is made low and α is made small, the contribution will be large, but it is impossible to make unlimited connections from the viewpoint of performance such as operation speed of 2b.

[Object of the Invention]

Therefore, the object of the present invention is to significantly reduce the transient current of the power supply without reducing α, that is, V _INT more than necessary, and particularly to reduce the peak current value thereof. Another object of the present invention is to provide a means for efficiently reducing the operating voltage of a circuit composed of fine elements in addition to the above-mentioned reduction of the transient current, and operating with the same power supply voltage as the conventional one even if the fine elements are used. To provide.

[Outline of Invention]

In the present invention, in order to achieve the above object, the transient power supply current is dispersed on the time axis, and the current is reduced by averaging the whole. More specifically, the energy required for the operation of the corresponding circuit is stored in the chip in advance at another time,
The circuit is operated by this stored energy. As a result, the transient power supply current generated when the energy is supplied from the power supply is dispersed in a time zone different from the time zone in which the circuit operates. Here, as the energy storage means,
The capacitor provided inside the chip is used. Also,
Furthermore, in the present invention, it is possible to determine the operating voltage of the circuit by dividing the charge between this capacitance and another capacitance provided separately or the capacitance of the corresponding circuit itself.

Example of Invention

 Hereinafter, details of the present invention will be described with reference to examples.

FIG. 2 is an embodiment showing the basic concept of the present invention. In the figure, the elements having the same numbers as those in FIG. 1 indicate the same elements. Same figure
C ₁ is the capacity described above as a means for storing energy in advance. C ₂ is a capacitance for determining the value of V _INT by dividing the charge with C ₁ , but an example of utilizing the capacitance of 2b itself is shown. Of course, it is also possible to use an externally added capacitor as indicated by the broken line C ₂ ′ in the figure. S ₁ and S ₂ are switches for controlling the operation. The operation of this embodiment will be described with reference to the current waveform in FIG. In the same figure, the broken line is the current when the whole is operated at V _EXT as in FIG. 1 (B), and i _a0 = i _b0, and the points where each waveform is approximated by a triangle are also shown in FIG. 1 (B). ) Is the same. The solid line shows the current waveform in this embodiment. At time T ₁ , S ₁ is on,
C ₁ If S ₂ is turned off is charged to a voltage of V _EXT, the V _EXT
A transient current i _c1 determined by the value of C ₁ flows. continue,
When S ₁ is off and S ₂ is on during the time period T ₂ , the node
The voltage of 10 is due to the charge division of C ₁ and C ₂ , (The initial value of C ₂ is 0V). Then at time T ₃ , S ₁ , S
Both ₂ are turned off, and 2a and 2b operate. However, since 2b operates by using the electric charge stored in C ₂ as an energy source, current flows from V _EXT to only 2a. Therefore, the transient power supply current I _E according to the present embodiment is the sum of i _c1 flowing at T ₁ and i _a0 flowing at T ₃ , as indicated by the solid line in FIG. It becomes possible to disperse into. In other words, by storing the energy required for the operation of 2b in C ₁ in advance, the flowing current was dispersed in the time period from T ₃ to T ₁ . The value of i _c1 is the current when the charge is supplied from V _EXT to C ₁ , but the energy supplied by this is equal to the energy consumed by 2b, so it is the same as i _b0. When the triangle approximation of Becomes It was but go-between, the value of i _E is always i _a0 following values: (i _a0 =
i _b0 ), and it is possible to easily reduce the value of i _E to 1/2 or less compared to the case of operating as it is at V _EXT .

FIG. 3 is another embodiment for explaining the details of the present invention, and shows an example in which the circuit 2b of FIG. ₂ is composed of a capacitor C ₂ , a resistor R _L and a switch S ₃ . The circuit 2a is omitted here for simplification. Also, a resistor R _IN is inserted in the input terminal of the power supply. FIG. 2B shows the operation waveform and the current waveform, which are shown in correspondence with the states of the switches in the respective time zones T ₁ , T ₂ , and T ₃ .

First, when only S ₁ is turned on at T ₁ , C ₁ is charged to V _EXT . At this time, the voltage V _{12 of} C ₁ has an initial value as described later, Therefore, the current i _c1 is expressed as shown in the figure, and the peak value at that time is Is represented. Then, at T ₂ , when only S ₂ is turned on, C ₁ and
Although resulting charge division of C _2, the initial value of C _2, since a V ₁₀ = 0V, Becomes That is, this value becomes the operating voltage V _{INT of} 2b. Subsequently, 2b operates during the time period of T ₃ , or S ₃ turns on and operates in the present embodiment. As a result, the charge of C ₂ is discharged via R _L. The current at this time is i _RL shown by the broken line in the figure, but this current does not flow from V _EXT .

In the above operation, the energy is supplied from V _{EXT in} the time period of T ₁ , and its value is , And this value is equal to the case of operating the Yotsute 2b to a voltage lowered to alpha] V _EXT by some means the Yotsute V _EXT to the conventional method shown in Figure 1. That is, it can be seen that the present invention does not consume extra energy.

As described above, according to the present invention, it is possible to store the energy required for operation in the capacitor C ₁ in advance in another time zone without consuming extra energy, and operate the transient current from the power supply. Can be shifted to a time zone different from the time zone in which the circuit originally operates. Further, the value of the current i _c1 flowing at this time can be controlled by the resistor R _{IN as} shown in FIG. 7B, and the problematic peak value can be reduced. As a result, the total transient power supply current supplied from V _EXT can be greatly reduced as described in FIG. Further, since the circuit 2b is operated at the voltage of αV _EXT (α1), the power consumption of the entire integrated circuit can be reduced.

The basic concept of the present invention has been described above with reference to the embodiments shown in FIGS. The present invention can be applied to various semiconductor integrated circuits, but an example in which the present invention is applied as a data line precharge means of a dynamic memory (hereinafter abbreviated as DRAM) will be described below with reference to specific embodiments.

FIG. 4 shows an embodiment in which the present invention is applied as a data line precharge means for DRAM.

In the figure, MC is a memory cell, which is arranged in a matrix at the intersections of the word lines X _{0 to} X ₃ and the data lines Y _{0 to} Y ₃ to form a memory cell array AR. The outline of the operation is as follows.

First, the read operation is performed as follows. When the address signals A _{0 to} A ₃ are input from the outside, the X decoder (X DEC) is determined. As a result, for example, when the word line X ₀ line is selected, the driver DRV outputs a selection pulse to X ₀ , and the read signal is output from the memory cell MC connected thereto to each of the data lines Y _{0 to} Y _3. Appears. On the other hand, Y DE
If the Y ₀ line is selected by C, the signal read to Y ₀ is output to the I / O line through the switch SW ₀ and is output to the outside as the data output D ₀ . For writing, the data input D _i is sent to the I / O lines, SW ₀ and Y ₀ lines by the write control signal WE, and data is written to the memory cell connected to the intersection with the selected X _0. Is written. Where clock φ
Therefore, various internal timings are generated by the timing generation circuits TMG1 and TMG2, and various circuit operations are controlled. The power supply voltage V _EXT (for example, 5 V) and V _SS (0 V) are also supplied to each circuit.

In such a DRAM, it is necessary to reset all circuits and put them in a standby state at the time of ending (or at the time of starting) the above operation. At that time, a large transient power supply current to the power supplies V _EXT and V _SS is required. Cause This current is the current flowing through the parasitic capacitance C _D when precharging (pre-charging) the data lines Y _{0 to} Y ₃ in the AR to a predetermined voltage and other TMG.
1, it can be roughly divided into two components of the current that flows in circuits other than AR such as TMG2. In this embodiment, the present embodiment is applied as a data line precharge means in AR to reduce the transient power supply current. That is, the AR corresponds to the 2b circuit in FIGS. 2 to 3 and the other corresponds to the 2a circuit.

First, turn on SW _P (corresponding to S ₁ in Figs. 2 to 3) and press C
Charge _DP . Next, at the pre-charge of AR, SW _P is turned off, SW _S (corresponding to S ₂ in FIGS. 2 to 3) is turned on, and C ₁
Precharge the data lines of Y ₀ to Y ₃ by dividing the charge of C _D and C _D. These switches are controlled by the output signals of the circuit provided inside the chip, but they are not shown for simplicity. The precharge voltage V _{DP at} this time is calculated by the charge division of C ₁ and C _D. Becomes At this time, the current flowing by the precharge of the data line uses the electric charge of C _DP as an energy source and is not supplied from the external V _EXT . That is, the precharge current was transferred to another time zone as the charging current of C _DP .

According to this embodiment described above, the data line precharge current of the AR and the current flowing through other circuits can be shifted so as not to overlap with each other by shifting the time zone, and the transient power supply current can be greatly reduced. . In this embodiment, the charging operation of C _DP is completely independent of the operation of AR, so that it can be performed at any time, and during the time when the DRAM transient power supply current is the minimum, or This can be done during the time when the generation of noise is the least problem in DRAM and devices using it. Thereby, the effect of the present invention becomes more effective.

FIG. 5 shows another embodiment of the present invention, which is an example in which the C _DP of FIG. 4 is operated by being shared by all data lines. The operation is exactly the same as in Fig. 4, but since C ₁ is shared, the precharge voltage V _DP is Becomes Here, n is the number of data lines. It was but connexion, it is sufficient to set the C _DP n times than that of Figure 4.

According to this embodiment, in addition to the effects obtained in the embodiment of FIG. 4, the V _DP of all the data lines of Y ₀ to Y _3, to a value exactly the same without being affected by manufacturing variations Therefore, the entire operation can be stabilized.

FIG. 6 shows an embodiment in which the memory array is divided into a plurality of memory arrays in FIG. 5, and here shows an example in which the memory array is divided into two memory arrays AR and AR '. In this embodiment as well, the same effect as in FIG. 5 can be obtained, but the entire data line voltage can be set to the same value regardless of the division of the memory array, and the overall operation can be stabilized. .

FIG. 7 is a more detailed embodiment of the present invention. In the embodiment of FIG. 4, a so-called 1-transistor type dynamic memory cell composed of a capacitor C _S and a MOS transistor Q _M is used as the memory cell. The example used is shown. Here, the memory array AR has a data line n and a word line m.
N × m matrix. The data lines are always composed of two pairs such as D ₀ , _{0 to} D _n to _n , and here, a so-called folded data line (in which the paired data lines are arranged parallel to each other ( Folded Dat
a Line Arrangement) configuration. For this structure, see 1980 ISSCC Dig.of Tech.Papers, pp228-pp22.
9. etc. for details. In this embodiment, the circuits such as TMG1 and TMG2 in FIG. 4 are omitted for simplicity. The operation of this embodiment will be described below assuming that all MOS transistors used are of the n-channel type.

First, as shown in FIG. 6B, when the pulse φ _P is applied, 100, ▲ ▼ is charged from αV _EXT to V _EXT . Then, for example, when the word line X ₀ is selected, the read signal is output from the memory cells MC connected to it to the data lines D _{0 to} D _n . On the other hand, a pulse is applied to the dummy word line DX ₁ at the same time as X ₀ , so that the data line ₀
A signal of about 1/2 of MC is output as a reference signal on ~ _n . Next, when φ _A changes from a high potential to a low potential, the sense amplifier SA operates and MC
The output signal from is discriminated and differentially amplified. The amplified signal is output to the outside in the same manner as described above. Also,
Writing is performed in the same manner as described above. afterwards,
When φ _S and φ _SS are applied, Q _S and Q _SS turn on, and C _DP and C _SS
By the electrification division of _D , the data line is precharged. At this time, necessarily, either in pairs and Natsuta data line low potential (~0V), since the other is decreased to a high potential (~V _DP), the voltage V _DP after Purichiyaji is Becomes The potential relation between D ₀ and ₀ changes according to the information of MC, but since both data lines are always shorted by Q _SS , the value of V _DP described above does not change.

According to this embodiment, the precharge current of the data line is
_As the precharge current I _CDP to _DP , the operation of the memory array can be independently dispersed in any time zone,
The transient power supply current can be greatly reduced. In FIG. 2B, φ _P is set to a low potential after φ _A , but this does not have an essential meaning, so that the high potentials of φ _P and φ _S do not overlap as much as possible. It is only necessary to set it, and any waveform can be set within the range that satisfies this condition.

FIG. 8 shows an example in which _CDP is shared between the data lines which form a pair in FIG. The operation of this embodiment is exactly the same as in FIG. Data line precharge voltage is Therefore, C _DP may be controlled so that V _DP has a desired value.

Also in this embodiment, the same effect as in FIG. 7 can be obtained. In this embodiment, since C _DP is shared between the paired data lines, it is necessary in FIG.
The transistor Q _SS for preventing the voltage V _DP of the data line from changing according to the information of C can be omitted.

Figure 9 is Figure 7, an example which is shared by all the data lines C _DP in Figure 8, is also a specific example of the embodiment described in Figure 5.

The operation of this embodiment can be explained in exactly the same way as in FIGS. The value of V _DP is Therefore, V _DP can be set arbitrarily by C _DP .

In this embodiment, in addition to the effects shown in FIGS. 7 and 8,
The V _DP of the entire AR can be set to be constant, and the operation can be stabilized. Note that, as in FIG. 8, Q _SS can be removed also in this embodiment.

In the above embodiments, an example in which a capacitance is added as a means for pre-storing energy required for circuit operation has been described, but energy is pre-stored by utilizing the capacitance originally present in the circuit in the semiconductor device. It is also possible.

FIG. 10 shows an embodiment thereof, and here shows an example in which the DRAM is divided into four memory arrays AR0 to AR3 as a whole, and the precharge of the data line is performed by the mutual charge division. Here, for simplicity, only one data line is shown as D. φ _{0 to} φ ₃ are selection signals for each AR, and only the AR to which the signal is applied operates. φ _{P0 to} φ _P3 are signals for precharging the data lines of the memory array other than those selected by φ ₀ to φ ₃ . Let's explain the operation using AR0 as an example.

The data line of each AR is precharged to V _DP = αV _EXT . When φ ₀ is applied, AR0 performs a predetermined operation. On the other hand, signals are also applied to φ _{P1 to} φ _P3, and the data lines of AR1 to AR3 are charged to V _EXT by SW _P1 to SW _P3 . Then φ ₀ , φ
_P1 to [phi] _P3 is turned off (low voltage), when phi _S is applied
SW _{S0 to} SW _S3 are turned on, causing charge division between the data line capacitances of each memory array, and each data line is precharged to a predetermined value V _DP . The value of V _DP in this case is Becomes

As described above, according to this embodiment, it is possible to store energy in advance by utilizing the capacity originally existing in the semiconductor device, and it is not necessary to add an extra capacity for this purpose. . Further, according to the present embodiment, since each memory array is formed of the same material and the same pattern, the data line capacitances are always substantially the same value even if the manufacturing conditions change. Therefore, there is an advantage that the value of V _DP is always kept constant.

FIG. 11 is a more detailed embodiment of the embodiment shown in FIG. 10, and shows an example using a one-transistor type memory cell having a folded data line structure, as in FIGS. 7 to 9. ing. Note that the memory cells are not shown in the figure for simplicity. The memory array is divided into two, AR and AR '. Phi _A in the figure, _'AR by, AR' phi _A is activated, respectively, φ _{P, 'Yotsute} the AR, AR' φ _P data line is Purichiyaji respectively. Therefore, φ _A and φ _A ′ are the tenth
Φ _P and φ _P ′ in φ ₀ to φ ₃ in the figure are φ _P0 to φ _{P3 in} FIG.
Respectively correspond to. In the present embodiment, when the AR is in operation, the AR 'is in the idle state, and when the AR' is in the active state, the AR is in the idle state. It is configured not to be applied.

The operation will be described below with reference to FIG. Note that the description will be made here assuming that AR is in operation and AR 'is in a dormant state. The selection of the memory array is performed by the address signal described in FIG.

First, when φ _P ′ is applied, each data line of AR ′ becomes α V _EXT
Is precharged to V _EXT . Then, when the AR word line φ _A is applied, the signal of the memory cell is amplified in the same manner as described above. Then, when φ _S and φ _SS are applied, each data line is precharged by the charge division between the data line capacitance of AR ′ and the data line capacitance of AR.
At this time, the value of V _DP is Becomes In this embodiment, the power supply current is represented by φ _P ′.
It flows as I _CD when charging AR ′.

According to the embodiment described above, the same material, for determined the Yotsute V _DP to charge division between the same pattern formed in the data line can be realized a stable operation without affected by manufacturing variations. The point that the transient power supply current can be greatly reduced is the same as in each of the embodiments described above.

FIG. 12 shows the precharge of the data line in FIG.
This is an example in which the high potential compensation circuit ACR of the data line also serves.
That is, ACR is originally, for example, 1981 ISSCC Dig.of Tech.Pa.
As described in pers, pp.85, it is for compensating the data line voltage on the high potential side after SA amplification (increasing it to V _EXT in this case) and sufficiently increasing the rewriting voltage to the memory cell. However, here, this is also used as a precharge means for the memory array in the dormant state. In the figure, for simplicity, only a pair of data lines are shown in the memory array of AR and AR '. The operation will be described below with reference to FIG.

Similarly to the above, when a signal is applied to the word line and a minute signal from the memory cell appears on the data line, the memory array selected by the address signal, for example, φ of AR.
_{When A} becomes a low potential, SA amplifies a minute signal. After that, when φ _AC and φ _AC ′ are applied and the ACR operates, the data line in the high potential (αV _EXT ) state, here, D ₀ , A of AR.
The potential of D ₀ ′, ₀ ′ of R ′ is raised to V _EXT . Next, when φ _S and φ _SS are applied, charge division is performed between the data line capacitances D ₀ , ₀ , D ₀ ′, ₀ ′, and precharge is performed. The voltage V _{DP at} that time is Becomes In this embodiment, the transient power supply current is φ _AC , φ
_{When AC} ′ is applied, I _CD as a charging current for the data line capacitance C _D of D ₀ , D ₀ ′ ₀ ′ flows.

According to this embodiment described above, the following effects can be obtained in addition to the effects of FIG.

That is, in the present embodiment, it is not necessary to select the ACR drive signal by the address signal, and it is possible to use a common signal for AR and AR '. If I _CD becomes too large by simultaneously performing ACT operation,
As in φ _P and φ _P ′ in the figure, a memory array in a dormant state, here φ _AC ′ in AR ′ is selected by an address signal so as to be φ _AC ″ in FIG. By I
It is possible to separate _{CDs such} as I _CD ″ (AR) and I _CD ″ (AR ′). Also, as in the indicated phi _AC which by a one-dot chain line in the drawing, to slow down the rise time, I _CD (AR ')
It is also possible to reduce the current as shown in. The method for reducing the current by delaying the rising time of the precharge signal in this way is also applicable to each of the above-described embodiments. In addition, in this embodiment, V _DP that controls power consumption and transient current is set to αV _EXT , and the rewrite voltage (MC after read operation that controls the stability of operation of the memory cell MC is set).
The voltage to be rewritten to, that is, the memory voltage) can be V _EXT, and low power consumption, low transient current, and high stable operation can be realized. Further, in this embodiment, the value of V _DP can be controlled by the combination of the data lines for dividing the charge. If fine adjustment of V _DP is required, provide C _DP ′ as shown in Fig. (A) to charge V _CC with Q _P ′ or discharge to ground potential with Q _G. It is possible to make fine adjustment. This method can also be applied to Figs. 10 and 11. Further, in this embodiment, an example in which the data line on the high potential side is level-compensated to V _EXT by ACR is shown.
It is also possible to raise the power supply voltage to a level higher than V _EXT by the method disclosed in 706. In this embodiment, the value of V _DP is determined by the electric charge stored in the capacitor, and the electric charge disappears due to the leakage current of each node,
There is a risk of _DP fluctuation. In such a case, as shown in FIG. 7A, the resistors R _B1 and R _B2 , which are large enough not to cause a problem in terms of power consumption, generate a voltage approximately equal to αV _EXT , and the above leakage current is generated. Should be compensated. This can be directly applied to each of the above-described embodiments.

The details of the present invention have been described above in the embodiments. The obtained effects are also described in each embodiment, but the main purpose of the present invention is to reduce the transient current and to increase the external power supply voltage by α times (α
By lowering to 1) and operating the circuit, various effects can be obtained in addition to the low power consumption. For example, in the embodiment in which each data line is short-circuited, the entire capacitance can be used as a smoothing capacitance to reduce the noise in the semiconductor device. Further, by lowering the operating voltage internally as described above, it becomes possible to operate with the same high power supply voltage as in the conventional case even if a fine element having a low breakdown voltage is used.

In each of the above embodiments, the application of the DRAM using the one-transistor type memory cell of the folded data line arrangement has been described as an example, but the present invention can be applied to various cases other than the above. For example, in addition to the folded data line configuration, IEE PROC., Vol.130, Pt.
I, No.3, June 1983, pp127-135., Etc. can be applied as is to DRAM with an open data line configuration (Open Data Line Arrangment). In addition, Japanese Patent Application Nos. 56-81042 and 57-12
The present invention can be applied as it is to a memory array configuration for dividing a data line into a large number to increase the S / N ratio as disclosed in 5687, 58-4162 and the like. Further, in the embodiment, an example in which it is applied as a data line precharge method has been described, but it is used to set the operating voltage of the other circuits shown in FIG. 4, or charge division is performed between the capacitances of different circuits. You can also set the voltage. Further, although the embodiments have been described on the assumption that N-MOS transistors are used, they can be applied to P-MOS transistors as they are by reversing the potential relationships of all signals. Further, the present invention can be applied to a C-MOS type semiconductor device using both N and P type MOS transistors, and further to a semiconductor device using a combination of bipolar type transistors.

〔The invention's effect〕

According to the present invention described above, a semiconductor device with low transient power supply current and low power consumption can be realized.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a conventional example, and FIGS. 2 to 12 are diagrams for explaining an embodiment of the present invention.

Continuation of the front page (56) Reference JP-A-57-172761 (JP, A) JP-A-58-70482 (JP, A) Actually developed JP-A-56-159353 (JP, U)

Claims (4)

[Claims] 1. A first memory array having a first pair of lines, a second memory array having a second pair of lines, the first pair of lines of the first memory array and the second line. Switch means connected between the memory array and the second pair of wires, the first memory array being activated and the second memory array being deactivated. At the end of the operation of the first memory array, the switch means is changed from the non-conducting state to the conducting state so that the capacitance of the first pair line of the first memory array and the second memory array. Performing charge transfer between the second pair of the second memory array and the first pair of the first memory array by charge sharing with the capacitance of the second pair of lines. A semiconductor device characterized by: 2. The first memory array is operated and the second memory array is stopped, and the second pair line of the second memory array is charged to a predetermined potential. At the end of the operation of the first memory array, the switch means is changed from the non-conducting state to the conducting state so that the capacitance of the first pair line of the first memory array and the second memory array. Charging from the second pair of lines of the second memory array to the first pair of lines of the first memory array by charge sharing with the capacitance of the second pair of lines. The semiconductor device according to claim 1. 3. The first pair of lines of the first memory array and the second pair of lines of the second memory array read information of selected memory cells of the respective memory arrays. The semiconductor device according to claim 1, wherein the semiconductor device is a data line pair. 4. The semiconductor device according to claim 3, wherein the memory cell is a dynamic memory cell composed of one transistor and one capacitor.