JPH0740602B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to an arrangement of bit lines and word lines of a semiconductor memory device.

[Conventional technology]

FIG. 2 shows a chip layout of a conventional SRAM (for DRAM, see, for example, Japanese Patent Application Laid-Open No. 60-161658).

Conventionally, the bit lines of a static random access memory are arranged in the x direction, and as the storage capacity increases, the bit lines become longer and the parasitic capacitance increases. For example, in a static random access memory of 64K bits, 256 memory cells in the x direction and 256 memory cells in the y direction are conventionally arranged in a matrix. 12 times the storage capacity
How about getting to an 8K bit? Since the number of matrices cannot be increased in the y direction due to the restriction of the package,
In addition, the only way to do this is to double the number of matrices in the x direction that have a margin. Of course, if the x-direction is doubled, the bit line length is doubled and the parasitic capacitance is also doubled, so that the access time cannot be reduced.

[Problems and Objectives to be Solved by the Invention]

However, the conventional SRAM has a problem that the bit line becomes longer as the storage capacity increases, the parasitic capacitance increases, and it is difficult to increase the speed. Therefore, in order to solve such a conventional problem, the present invention has a feature that the access time is shortened without lengthening the bit line even if the storage capacity is increased.
It is intended to provide a layout configuration of SRAM.

[Means for solving problems]

The semiconductor memory device of the present invention is a semiconductor memory device in which a plurality of memory cell arrays are formed on a substantially rectangular semiconductor chip having two sides having different lengths, wherein the memory cell array has a plurality of bit lines and a plurality of words. Lines, the bit lines are arranged substantially parallel to a short side direction of the semiconductor chip, the word lines are arranged substantially parallel to a long side direction of the semiconductor chip, and the plurality of memory cell arrays are the semiconductor chips. It is characterized in that they are arranged so as to be aligned in the long side direction.

〔Example〕

FIG. 1 is a layout configuration diagram in a chip in the embodiment of the present invention. Hereinafter, the present invention will be described with reference to FIG.

Bit lines 5 are arranged in parallel with 4 input / output terminals arranged in the y direction, and word lines 6 are arranged so as to be orthogonal to the input / output terminals. Even if the storage capacity increases, it is not possible to increase the number of matrixes of memory cells in the y direction due to package restrictions. Therefore, the number of matrices is increased in the x direction. Even if the number of memory cells is increased in the x direction, the length of one bit line does not change and the parasitic capacitance does not increase. On the contrary, the resistance of the word line increases, but this can be suppressed by using a low resistance material or dividing the row decoder into two.

〔The invention's effect〕

As described above, by adopting the configuration of the present invention, both the bit line and the word line can be shortened, and the access time can be shortened.

[Brief description of drawings]

 FIG. 1 is a layout diagram in the chip of the present invention. FIG. 2 is a layout diagram of a conventional chip. DESCRIPTION OF SYMBOLS 1 ... Memory cell array 2 ... Row decoder 3 ... Peripheral circuit 4 ... Input / output terminal 5 ... Bit line 6 ... Word line 7 ... Memory cell array 8 ... Row decoder 9 ... Peripheral circuit 10 ... Input / output terminal 11 ... Bit line 12 ... Word line

Claims (1)

[Claims] 1. A semiconductor memory device comprising a plurality of memory cell arrays formed on a substantially rectangular semiconductor chip having two sides having different lengths, wherein the memory cell array comprises a plurality of bit lines and a plurality of word lines. The bit lines are arranged substantially parallel to a short side direction of the semiconductor chip, the word lines are arranged substantially parallel to a long side direction of the semiconductor chip, and the plurality of memory cell arrays are arranged at long sides of the semiconductor chip. A semiconductor memory device, wherein the semiconductor memory device is arranged so as to be aligned in a direction.