JPH07297408A - Tunnel transistor and its manufacture - Google Patents

Abstract

PURPOSE:To provide a transistor which can be improved in degree of integration and operating speed and utilizes a tunnel phenomenon. CONSTITUTION:After successively forming an n<+>-type GaAs layer 2 which becomes a source, undoped GaAs layer 3, p<+>-type GaAs layer 4 which becomes a drain, and undoped GaAs layer 5 which becomes a current barrier layer on an semi-insulating GaAs substrate 1, the layers 3, 4, and 5 on the layer 2 are etched in the form of a mesa. Then a n<+>-type GaAs layer 6 which becomes a channel layer and undoped A GaAs layer 7 which becomes a gate insulating film are successively formed on the exposed side face of the mesa and a Schottky electrode 8 is provided on the layer 7. As a result, an inter-band tunnel junction is formed at the contacts between the layer 6 and the layers 4 and 3 on the side face of the mesa. On the other hand, no leak current flows between the drain 4 constituting the upper part of the mesa and the N<+>-type GaAs 6 of the channel layer due to the undoped GaAs layer 5. Therefore, the P/V ratio of the negative resistance characteristic is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor utilizing a tunnel phenomenon which can be highly integrated and can operate at high speed.

[0002]

2. Description of the Related Art Utilizing a tunneling phenomenon at a p ⁺ -n ⁺ junction on a semiconductor surface, a normal Si MOSFET or Ga is used.
A tunnel transistor has been proposed as a transistor whose operating principle is different from that of As MESFET. Regarding this device, for example, Japanese Patent Application No. 6-020 by Uemura
No. 707. This transistor positively utilizes the avalanche and tunnel effect, which are problems at the limit of miniaturization of MOSFET, and enables high integration. The structure and operation of this conventional tunnel transistor will be briefly described with reference to the structural diagram.

FIG. 2 is a schematic diagram of the structure of a conventional tunnel transistor. This conventional tunnel transistor
A non-degenerate substrate 1, a degenerate first semiconductor 2 having one conductivity type, and a non-degenerate second semiconductor 3.
A third semiconductor 4 having a conductivity type opposite to that of the first semiconductor 2.
And a fifth semiconductor 6 provided on the second semiconductor 3,
A sixth semiconductor 7 provided on the fifth semiconductor 6, and a sixth semiconductor
A gate electrode 8 provided on the semiconductor 7, a source electrode 9 forming an ohmic contact with the first semiconductor 2, and a third electrode
Drain electrode 1 forming ohmic contact with the semiconductor 4 of
It is composed of 0 and 0.

Regarding the operation of this conventional tunnel transistor, semi-insulating GaAs is used for the substrate 1, n ⁺ -GaAs is used for the first semiconductor 2, and undoped GaA is used for the second semiconductor 3.
s, p ⁺ -GaAs on the third semiconductor 4, and the fifth semiconductor 6
To n ⁺ -GaAs and the seventh semiconductor 7 to i-Al _0.3 Ga
_0.7 As, Al for the gate electrode 8 and AuG for the source electrode 9
e, an example using AuZn for the drain electrode 10 will be described.

The fifth semiconductor 6 is in contact with the first, second and third semiconductors 2, 3 and 4, but the portion in contact with the third semiconductor 4 is fully depleted in the fifth semiconductor 6. Semiconductor 6
Appropriately select the carrier concentration and thickness of. At this time, an inter-band tunnel junction is formed between the third semiconductor 4 and the fifth semiconductor 6 on the second semiconductor 3, and the current-voltage characteristic thereof has a negative resistance characteristic. Since the third semiconductor 4 is sharpened at the tunnel junction portion by the mesa etching, electric field concentration occurs and a large tunnel current flows. The fifth semiconductor 6 on the second semiconductor 3 acts as a channel and contacts the source first semiconductor 2. 5th depending on the gate voltage
By changing the carrier concentration of the semiconductor 6, the tunnel current can be modulated and a transistor operation can be obtained.

[0006]

In the conventional tunnel transistor, as can be seen from the figure, in the upper part of the mesa,
A junction is formed between the third semiconductor and the fifth semiconductor, and an extra current other than the band-to-band tunnel current flows through this portion. As a result, the valley current in the negative resistance characteristic increases, the ratio of the peak current to the valley current (P / V ratio) decreases, and it becomes difficult to apply it as a functional element.

An object of the present invention is to provide a tunnel transistor in which the P / V ratio of the negative resistance characteristic is increased as compared with the conventional structure.

Another object of the present invention is to provide a method of manufacturing such a tunnel transistor.

[0009]

In a tunnel transistor of the present invention, a degenerate first semiconductor having one conductivity type, a non-degenerate second semiconductor, and the first semiconductor are provided on a part of a substrate. The semiconductor device has a laminated structure of a degenerate third semiconductor having a conductivity type opposite to that of the semiconductor and a non-degenerate fourth semiconductor, and at least the same surface as the first semiconductor is formed on the exposed surface of the second semiconductor. A degenerate fifth semiconductor made of a material having a conductivity type and having the same or a narrower bandgap than the second semiconductor; and a bandgap on the layer of the fifth semiconductor, the bandgap wider than the fifth semiconductor. A wide sixth semiconductor layer, a Schottky electrode on the fifth semiconductor layer, and a pair of electrodes forming ohmic junctions with the first semiconductor and the third semiconductor, respectively. There is.

According to the method of manufacturing a tunnel transistor of the present invention, a degenerate first semiconductor having one conductivity type, a non-degenerate second semiconductor, and a conductivity opposite to the first semiconductor are formed on a substrate. Stacking a degenerate third semiconductor having a mold and a non-degenerate fourth semiconductor; leaving a drain region in a mesa shape to expose a part of the first semiconductor; Forming a fifth semiconductor to be a channel layer on the surface of the structure, forming a sixth semiconductor to be a gate insulating layer on the fifth semiconductor, and forming a sixth semiconductor on the sixth semiconductor. The method is characterized by including a step of forming a gate electrode, a step of forming a source electrode on the exposed first semiconductor, and a step of forming a drain electrode on the third semiconductor.

[0011]

By inserting the fourth semiconductor serving as the current barrier layer between the third semiconductor and the fifth semiconductor in the upper portion of the mesa of the conventional tunnel transistor, the leak current flowing between them is reduced, and P / V is reduced. The ratio can be increased.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a schematic diagram showing an embodiment of the present invention. 1, the same symbols as those in FIG. 2 are equivalent to those in FIG. 3 and have the same functions.

This tunnel transistor includes a degenerate first semiconductor 2 having one conductivity type on a part of a substrate 1, a non-degenerate second semiconductor 3, and a conductivity type opposite to that of the first semiconductor 2. And a degenerate third semiconductor 4 and a non-degenerate fourth semiconductor 5 have a stacked structure.
On the exposed surfaces of the third, fourth semiconductors 2, 3, 4, 5 the first
Second semiconductor 6 having the same conductivity type as that of the second semiconductor 3 and having the same or narrower bandgap than the second semiconductor 3, and the fifth semiconductor 6 on the fifth semiconductor 6 A sixth semiconductor 7 having a bandgap wider than that of the sixth semiconductor 7
A gate electrode 8 provided thereon, a source electrode 9 forming an ohmic contact with the first semiconductor 2, and a third semiconductor 4
And a drain electrode 10 forming an ohmic contact with.

As an example, the substrate 1 is made of semi-insulating GaAs,
N ⁺ -GaAs for the first semiconductor 2, undoped GaAs for the second semiconductor 3, p ⁺ -GaAs for the third semiconductor 4,
Undoped GaAs as the fourth semiconductor 5 and the fifth semiconductor 6
Is n ⁺ -GaAs, and the sixth semiconductor 7 is undoped Al.
_0.3 Ga _0.7 As, Al for gate electrode 8 and source electrode 9
And AuZn for the drain electrode 10.

The fifth semiconductor 6 is in contact with the first, second, third and fourth semiconductors 2.3, 4, 5, but the part in contact with the third semiconductor 4 is completely depleted. The carrier concentration and the thickness of the fifth semiconductor 6 are appropriately selected so as to be made uniform. At this time, an interband tunnel junction is formed between the third semiconductor 4 and the fifth semiconductor 6 on the second semiconductor 3. Since the third semiconductor 4 is sharpened at the tunnel junction portion by the mesa etching, electric field concentration occurs and a large tunnel current flows. The fifth semiconductor 6 on the second semiconductor 3 acts as a channel and contacts the source first semiconductor 2.
The carrier concentration of the fifth semiconductor 6 can be changed by the gate voltage, and the tunnel current can be modulated. Here, the fourth semiconductor 5 is the third semiconductor 4 and the fifth semiconductor 6.
Since it is inserted between and, the current component flowing through this portion is suppressed, and only the current component flowing through the interband junction formed on the side surface of the mesa is provided between the source and the drain. As a result, the leak current, which is a factor that deteriorates the negative resistance characteristic, is reduced, and the characteristic is improved.

The tunnel transistor having such a structure is manufactured as follows.

First, as shown in FIG. 3, the substrate 1 is MBE
The first semiconductor 2 to the fourth semiconductor 5 are introduced into a device by a molecular beam epitaxial method on a substrate to obtain n ⁺ -Ga.
As (1 × 10 ¹⁹ cm ⁻³ , 300 nm), undoped G
aAs (200 nm), p ⁺ -GaAs (1 × 10 ²⁰ c
m ^-3 , 100 nm), undoped GaAs (50 nm)
Are sequentially grown at a substrate temperature of 520 ° C.

Next, as shown in FIG. 4, the drain region is left in a mesa shape by lithography and etching, and the first region is formed.
A part of n ⁺ -GaAs which is the semiconductor 2 of is exposed.
After cleaning by organic washing, the sample is again M
As shown in FIG. 5, the n ⁺ -GaAs of the fifth semiconductor 6 which will be a channel layer on the surface of the formed structure was introduced into the BE device.
(1 × 10 ¹⁹ cm ⁻³ , 1.2 nm), and undoped Al _0.3 Ga _0.7 of the sixth semiconductor 7 to be the gate insulating layer.
Re-grow As (40 nm). After that, Al for the gate electrode is deposited.

Next, as shown in FIG. 6, Al and the sixth, fifth and fourth semiconductor layers 7, 6 and 5 are etched into the shape of the gate electrode 8.

Next, as shown in FIG. 7, AuGe is formed on n ⁺ -GaAs of the first semiconductor 2 by lift-off and alloyed to form the source electrode 9. Finally, by performing lift-off, the AuZn, which is the drain electrode 10, is formed into a third layer.
It is formed on p ⁺ -GaAs which is the semiconductor 4 of, and the fabrication of the tunnel transistor is completed.

The fabricated tunnel transistor exhibited a negative resistance characteristic depending on the gate voltage under forward bias. As a result of suppressing the valley current, P /
The V ratio increased by about 3 times.

In the above embodiments of the present invention, only the n-type and the p-type as the third semiconductor and the third semiconductor are shown as the conductivity type. However, these conductivity types are reversed. However, the same operation can be obtained. As the fourth semiconductor, another material may be used as long as it is a layer capable of suppressing the leak current. Further, the structure in which the fifth semiconductor is used as the channel layer has been described, but as the fifth semiconductor, an ionized impurity having a wider band gap than the second semiconductor and having the same conductivity type as the first semiconductor is used. It is also possible to apply to a transistor having a structure in which a channel layer is formed on the second semiconductor surface by using the contained layer. Furthermore, as the material to be used,
Besides GaAs / AlGaAs system, SiGe / Si,
Ge / GaAs, InGaAs / InAlAs, GaS
It is obvious that the present invention can be applied to other semiconductors such as b / AlGaSb.

[0024]

According to the structure of the tunnel transistor of the present invention, the P / V ratio of the negative resistance characteristic is increased to about 3 times that of the conventional structure.

[Brief description of drawings]

FIG. 1 is a schematic sectional view showing a tunnel transistor of one embodiment of the present invention.

FIG. 2 is a schematic sectional view of a conventional tunnel transistor.

FIG. 3 is a schematic cross-sectional view showing the method of manufacturing the tunnel transistor of FIG.

FIG. 4 is a schematic cross-sectional view showing the method of manufacturing the tunnel transistor of FIG.

5 is a schematic cross-sectional view showing the method of manufacturing the tunnel transistor of FIG.

FIG. 6 is a schematic cross-sectional view showing the method of manufacturing the tunnel transistor of FIG.

FIG. 7 is a schematic cross-sectional view showing the method of manufacturing the tunnel transistor of FIG.

[Explanation of symbols]

 1 substrate 2 1st semiconductor 3 2nd semiconductor 4 3rd semiconductor 5 4th semiconductor 6 5th semiconductor 7 6th semiconductor 8 gate electrode 9 source electrode 10 drain electrode

Claims (5)

[Claims] 1. A degenerate first semiconductor having one conductivity type, a second semiconductor not degenerate, and a degeneracy opposite to the first semiconductor on a part of the substrate. A second semiconductor having a laminated structure of a third semiconductor and a non-degenerate fourth semiconductor, having the same conductivity type as the first semiconductor on at least the exposed surface of the second semiconductor; A degenerate fifth semiconductor made of a material having the same or a narrower bandgap than that of the fifth semiconductor, a sixth semiconductor layer having a wider bandgap than the fifth semiconductor on the layer of the fifth semiconductor, 5. A tunnel transistor having a Schottky electrode on the semiconductor layer of No. 5, and a pair of electrodes forming ohmic junctions with the first semiconductor and the third semiconductor, respectively. 2. A degenerate first semiconductor having one conductivity type, a second semiconductor not degenerate, and a degeneracy opposite to the first semiconductor on a part of the substrate. It has a laminated structure of a third semiconductor and a layer for suppressing leakage current,
A degenerate fifth semiconductor having a same conductivity type as that of the first semiconductor on at least the exposed surface of the second semiconductor and having a band gap that is the same as or narrower than that of the second semiconductor; A sixth semiconductor layer having a wider bandgap than the fifth semiconductor layer on the fifth semiconductor layer, a Schottky electrode on the fifth semiconductor layer, the first semiconductor and the third semiconductor layer.
And a pair of electrodes forming ohmic junctions on the semiconductor of the tunnel transistor. 3. The substrate is semi-insulating GaAs, the first semiconductor is n ⁺ -GaAs, the second semiconductor is undoped GaAs, the third semiconductor is p ⁺ -GaAs, and the fourth semiconductor is Undoped GaAs, the fifth semiconductor is n ⁺ -GaAs, and the sixth semiconductor is undoped Al.
The tunnel transistor according to claim 1, wherein the tunnel transistor is _0.3 Ga _0.7 As. 4. A degenerate first having one conductivity type on a substrate.
The second semiconductor, which is not degenerate, and the first semiconductor
Stacking a degenerate third semiconductor having a conductivity type opposite to that of the first semiconductor and a non-degenerate fourth semiconductor, leaving a drain region in a mesa shape and partially removing the first semiconductor. A step of exposing, a step of forming a fifth semiconductor to be a channel layer on the surface of the above structure, a step of forming a sixth semiconductor to be a gate insulating layer on the fifth semiconductor, A step of forming a gate electrode on the sixth semiconductor; a step of forming a source electrode on the exposed first semiconductor; and a step of forming a drain electrode on the third semiconductor. A method for manufacturing a tunnel transistor, comprising: 5. A degenerate first having one conductivity type on a substrate.
The second semiconductor, which is not degenerate, and the first semiconductor
Stacking a degenerate third semiconductor having a conductivity type opposite to that of the first semiconductor, and a layer for suppressing leakage current; leaving a drain region in a mesa shape to expose a part of the first semiconductor A step, a step of forming a fifth semiconductor to be a channel layer on the surface of the above structure, a step of forming a sixth semiconductor to be a gate insulating layer on the fifth semiconductor, and a step of forming the sixth semiconductor Forming a gate electrode on the semiconductor, the step of forming a source electrode on the exposed first semiconductor, and the step of forming a drain electrode on the third semiconductor. A method for manufacturing a featured tunnel transistor.