JPH07295663A - Power source on/off control circuit - Google Patents

Abstract

PURPOSE:To prevent a logic circuit from malfunctioning by securely generating a reset pulse even when the circuit is so constituted that the reset pulse is generated at a rise of a voltage. CONSTITUTION:When a switch SW is turned off, the logic circuit 14 supplies a high level to a terminal P3 to turn on a transistor(TR) Q2. Consequently, a capacitor C is charged. The logic circuit 14 turns off a logic power source 12 when specific operation ends after the switch SW is opened. Consequently, the TR Q2 is turned OFF, but the capacitor C is still charged, so TRs Q3 and Q4 stay on for a specific subsequent time. Therefore, even if the switch SW is closed, an output TR Q1 is not turned on to stop the logic circuit 12 from being actuated. Consequently, the output of an oscillation circuit 16 is lower than a specific potential without fail and the reset pulse is generated by a reset pulse generating circuit 18 without fail when the logic power source 12 is turned on, thereby preventing the logic circuit 14 from malfunctioning.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an on / off control circuit for turning on a power supply circuit to perform a predetermined operation when a switch such as a shutter of a camera is pressed, and turning off the power supply circuit after the operation is completed.

[0002]

2. Description of the Related Art Conventionally, even in devices such as cameras,
An electronic circuit such as an IC is mounted and each operation is electronically controlled. Such electronic circuits are battery powered and there is a desire to minimize power consumption.

Therefore, normally, only the circuit for detecting the operation of the shutter, the operation of opening and closing the back cover, etc. is set in the standby state, and the power supply circuit for operating the other circuits is turned off. Then, when some operation is performed, the power supply circuit is turned on, a predetermined process is performed, and the power supply circuit is turned off after the process is completed.

Here, there are a signal detection circuit, a driver circuit, a logic circuit, and the like in the circuit which receives the power supply from the power supply circuit. For example, when the shutter is pressed, a circuit for detecting ON / OFF of the shutter is provided. When this operation is detected, the power supply circuit is turned on and power supply to various circuits is started. The logic circuit, after performing a predetermined initial operation,
Upon receiving a signal from the detection circuit for distance measurement, the lens position is determined, the driver circuit is controlled, and the lens is moved to a predetermined position to perform a focusing operation (autofocus operation).
Then, the shutter is opened and closed to expose the film, the film is wound up, and after such processing is completed, the logic circuit turns off the power supply circuit.

Among these operations, the operation when the switch is off will be described with reference to FIG. First, as shown in FIG. 3A, when the switch SW is turned off by operating the shutter, the switch is recognized in the logic circuit. However, as shown in FIG. During operation, the power supply circuit (logic power supply) remains on. Then, when the operation of the logic circuit is completed, the logic circuit turns off the logic power supply.

Here, the logic circuit operates using the logic pulse shown in FIG. 3D, which is created based on the signal from the oscillation circuit shown in FIG. 3C, as a clock. Then, the logic circuit must perform a reset operation as an initial operation at the start of the operation.

However, the oscillation circuit includes a capacitor, and the output level thereof gradually rises when the power is turned on. Therefore, the reset pulse can be obtained by comparing the output of this oscillation circuit with the voltage that rises immediately when the power is turned on. That is, the output of the oscillator fluctuates between V1 and V2 during operation, and drops to 0 when the power is off. Therefore, the switch SW
When the output voltage of the logic power supply rises when the
Compared with the voltage V1, which is lower than the voltages V1 and V2 generated from the output of the logic power supply that rises immediately, a reset pulse that is at a high level from 0 to the voltage V3 is generated, and thereby the logic circuit is generated. To reset. As a result, the logic circuit is reset when the power is turned on, and a predetermined operation is always performed.

[0008]

However, as described above, the oscillation circuit includes the capacitor, and its output gradually decreases even when the power is off. Therefore, even after the power supply circuit is turned off, the voltage does not fall below V3 for a while.
Therefore, after the power supply circuit is turned off, the oscillation circuit output is V
When a switch such as a shutter is operated at a bad timing (before the period shown by A in FIG. 3 from the switch-off) before 3 or less, as shown in FIG.
The logic circuit will start operating without generation of the reset pulse.

In such a case, for example, the storage content of the storage means in the logic circuit is unspecified, and there is a problem that various malfunctions may occur if the storage device operates as it is.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide an on / off control circuit capable of preventing the occurrence of malfunction regardless of the switch operation timing. And

[0011]

SUMMARY OF THE INVENTION The present invention includes an output transistor which operates in response to turning on and off of a switch operated from the outside, a logic power supply which is turned on by a signal from the output transistor and outputs a predetermined voltage, A logic circuit that receives the output voltage of the logic power supply and performs a predetermined process according to the operation of the switch, and when the process is completed, turns off the logic power supply to end the voltage output, and the switch During the predetermined period from the off operation to the stop of the output of the logic power supply, the capacitor to be charged, and during the predetermined discharge period until the output voltage of the capacitor reaches a predetermined value, the output voltage from the capacitor causes Suppressing means for suppressing the operation of the output transistor.

Further, an oscillator circuit that oscillates when supplied with a voltage from the logic power source and an output from this oscillator circuit are compared with a predetermined threshold value, and when the output voltage of the logic power source rises, the output of the oscillator circuit is A reset pulse generation circuit that generates a reset pulse until it reaches a predetermined threshold value or more, and, during a predetermined discharge period of the capacitor, the output of the oscillation circuit is stopped when the output of the logic power supply is stopped. It is characterized in that it is longer than a period in which the reset pulse generation circuit drops below a threshold value.

The suppressing means is connected to the base of the output transistor and is turned on by the output voltage of the capacitor to fix the base of the output transistor to a predetermined potential to suppress its operation. It is characterized by having.

[0014]

As described above, according to the present invention, the suppressing means is provided and the operation of the output transistor is prohibited for a predetermined period. Therefore, the period from when the logic power supply is turned off to when it is turned on can be set to a predetermined length or longer.

For this reason, when the rise of the output of the logic power supply is dampened and a reset pulse is generated by utilizing this, the reset pulse can be reliably generated when the logic circuit is reset.

That is, the voltage of the output of the oscillation circuit having a built-in capacitor which is operated by the output of the logic power supply gradually rises as the power supply is turned on, and a predetermined oscillation operation is started. Therefore, by comparing the output of this oscillation circuit with a predetermined threshold value, it is possible to obtain a reset pulse which is at a high level for a predetermined period until the predetermined threshold value is reached.

However, the voltage of the output of the oscillator gradually rises when the power source rises, and also gradually drops when the power source is turned off. Therefore, after the logic power is turned off, the switch is turned on before the oscillator output falls to the threshold for generating the reset pulse,
When the logic circuit starts operating based on this, the logic circuit may start operating without the reset pulse being generated, resulting in malfunction.

However, according to the present invention, the suppressing means prohibits the operation of the output transistor and the operation of the logic power supply for a predetermined period after the output of the logic power supply is stopped by the voltage charged in the capacitor. This solves the above-mentioned problems.

Further, by fixing the base of the output transistor to a predetermined potential with another transistor, the suppressing means can be constituted by a simple means.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing the overall configuration of the embodiment, in which a battery 10 outputs a voltage VB. The logic power supply 12 receives the voltage VB from the battery 10 and outputs the logic voltage VREG. This logic voltage VREG serves as a power supply for operating the logic circuit 14 and the like.

The switch SW receives the voltage VB from the battery 10 at one end, and the other end is connected to the terminal P1.
The terminal P1 is connected to the ground via the resistors R1 and R2, and the connection point of the resistors R1 and R2 is connected to the base of the NPN type output transistor Q1 via the adjustment resistor R3. Therefore, when the switch SW is turned on, the voltage at the connection point of the resistors R1 and R2 becomes a predetermined high level, and the output transistor Q1 is turned on. The output transistor Q1 has an emitter connected to the ground and a collector connected to the logic power supply 12. Then, by the output transistor Q1, the logic power source 1
2 starts its operation. For example, a switch for starting the operation of the logic power supply 12 is turned on when a current flows through the output transistor Q1.

On the other hand, the voltage VREG of the logic power supply 12 is supplied to the logic circuit 14, and the logic circuit 14
Receives the supply of the voltage VREG and performs various processes. Also,
The oscillator circuit 16 also receives the supply of the voltage VREG from the logic power supply 12, performs a predetermined oscillation operation, and supplies its output signal to the logic circuit 14. The oscillator circuit 16 has a terminal P
A predetermined oscillating operation is carried out by using a capacitor 16a externally attached via No.4. The logic circuit 14 is
Create a logic pulse from the oscillation output of the oscillator circuit 16,
This logic pulse operates as a clock.

Further, since it does not matter if the logic power supply 12 is turned off while the logic circuit 14 is performing a predetermined process, the logic circuit 14 can control the turning off of the logic power supply 12. That is, the logic power supply 12 starts its operation when the output transistor Q1 is turned on, but it is not turned off even when the output transistor Q1 is turned off, and is turned off in response to the processing end signal from the logic circuit 14.

Further, a reset pulse generation circuit 18 is connected to the oscillation circuit 16. The reset pulse generation circuit 18 is composed of a comparator that compares the output from the oscillation circuit 16 with a predetermined threshold value, and outputs a reset pulse when the output of the oscillation circuit 16 is less than or equal to the predetermined threshold value.

On the other hand, the logic circuit 14 turns off the logic power supply 12 when a predetermined operation is completed, and
After the switch SW is turned off and the output transistor Q1 is turned off, a high level signal is input to the terminal P3 until the logic power supply 12 is turned off.

An NPN transistor Q is connected to the terminal P3.
The base of the transistor Q2 is connected, and the collector of the transistor Q2 is connected to the voltage VB via the resistors R4 and R5. Therefore, this transistor Q2 will be turned on if the terminal P3 is at a high level.

A capacitor C is connected to a connection point between the collector of the transistor Q2 and the resistor R4 via a terminal P2. The other end of the capacitor C is connected to the battery voltage VB. Therefore, when the transistor Q2 is off, the terminal P2 is kept at VB and the capacitor C
The voltage between both ends of is zero. On the other hand, transistor Q
When P2 is on, the terminal P2 is connected to the ground, so that it is charged to the voltage VB across the capacitor C.

The connection point of the resistors R6 and R7 is connected to the base of a PNP type transistor Q3. The emitter of the transistor Q3 is connected to the voltage VB, and the collector is connected to the ground via the resistors R6 and R7. Therefore, the transistor Q3 turns on when the transistor Q2 is on.

The connection point of the resistors R6 and R7 is connected to the base of the NPN transistor Q4. Therefore, transistor Q4 turns on when transistor Q3 is on. The collector of the transistor Q4 is connected to the connection point of the resistors R1 and R2 described above. Resistors R1 and R
The connection point of 2 is connected to the base of the output transistor Q1 via the resistor R3. When the transistor Q4 is on, the base of the output transistor Q1 is grounded and the output transistor Q1 is always off. That is, when the transistor Q4 is on, the output transistor Q1 is not turned on even if the switch SW is on. Thus, the transistor Q4 functions as a suppressing transistor that suppresses the operation of the transistor Q1.

The base of the transistor Q2 is connected to the connection point of the resistors R8 and R9, the other end of the resistor R8 is connected to the ground, and the other end of the resistor R9 is connected via a PNP type transistor Q5. It is connected to the output voltage VREG of the logic power supply 12. That is, the transistor Q5
A resistor R9 is connected to the collector of the
Connected to REG. Therefore, by supplying a low-level signal to the base of the transistor Q5 while the logic power supply 12 is operating and turning on the transistor Q5, the transistor Q2 can be turned on and the transistors Q3 and Q4 can be turned on. It is possible to inhibit the output transistor Q1 from being turned on even if the SW is turned on.

The operation of such a circuit will be described with reference to FIG. First, when the switch SW is turned off, the potential of the terminal P1 drops to the ground level. This turns off the output transistor Q1, which is recognized by the logic circuit 14. The logic circuit is switch S
A predetermined process is performed according to the turning off of W. At this time, a high level signal is supplied to P3.

The high level of P3 turns on the transistors Q2, Q3 and Q4, and the output transistor Q1.
The off state of is fixed as it is. On the other hand, when the transistor Q2 is turned on, the terminal P2 drops to the ground level, and the voltage across the capacitor is charged to VB.

Then, the logic circuit 14 includes a switch S.
When the processing corresponding to the turning off of W is completed, the logic power supply 12
Is turned off and the high level output to the terminal P3 is stopped.

As a result, the transistor Q2 is turned off and the voltage at the base of the transistor Q3 also rises. However, a capacitor C is connected to the collector of the transistor Q2, and when the transistor Q2 is on, the voltage across the capacitor C is VB. Therefore, even if the transistor Q2 is turned off, the capacitor C
Push down the voltage on the collector side of the transistor Q2.
Then, since the current is supplied to the capacitor C via the resistors R4 and R5, the voltage of the terminal P2 gradually rises.

In this way, a predetermined current flows through the resistor R5 until the voltage at the terminal P2 rises to V5.
The base of the transistor Q3 is maintained at the low level, and the transistor Q3 maintains the ON state. Therefore, the operation of the logic power supply is stopped, the transistor Q4 is turned on for a predetermined period even after the voltage of the terminal P3 is lowered, and the turning on of the output transistor Q1 is prohibited. Therefore, the transistor Q
No. 1 is prohibited from being turned on for a period indicated by B after the switch SW is turned off.

The oscillation circuit 16 is operated by the logic power supply 12, and the output OC of the oscillation circuit 16 drops when the logic power supply 12 is turned off. Then, in the present embodiment, as described above, the transistor Q4 remains turned on by the action of the capacitor C for a predetermined period after the logic power supply 12 is turned off, and the output transistor Q1 is not turned on. Therefore, the logic power supply 12 is not turned on by turning on the output transistor Q1. Therefore, the logic power supply 12 is turned on after the output OC of the oscillation circuit 16 becomes a predetermined low level.

If a predetermined time elapses after the logic power supply 12 is turned off, the output OC of the oscillator circuit 16 always drops to the ground level. Therefore, when the switch SW is next turned on and the output transistor Q1 is turned on, the reset pulse generation circuit 18 outputs a reset pulse during the period until the output of the oscillation circuit 16 reaches the threshold value V3.

As described above, according to this embodiment, when the switch SW is turned on by starting the operation of the logic circuit 14 by inhibiting the switch SW from being turned on for a predetermined period, the reset pulse generating circuit is operated. A reset pulse is always generated. Therefore, it is possible to prevent the occurrence of malfunction in the logic circuit 14.

[0039]

As described above, according to the present invention,
Suppression means is provided to inhibit the operation of the output transistor for a predetermined period. Therefore, the period from when the logic power supply is turned off to when it is turned on can be set to a predetermined length or longer.

Therefore, even when the reset pulse is generated at the rising of the voltage, the reset pulse can be surely generated, and the malfunction of the logic circuit can be suppressed.

Further, by fixing the base of the output transistor to a predetermined potential with another transistor, the suppressing means can be constituted by a simple means.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an example.

FIG. 2 is a timing chart showing the operation of the embodiment.

FIG. 3 is a timing chart showing an operation of a conventional example.

[Explanation of symbols]

 10 Battery 12 Logic Power Supply 14 Logic Circuit 16 Oscillation Circuit 18 Reset Pulse Generation Circuit Q1 Output Transistor

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tomio Kurosu 2-16-20 Shimura, Itabashi-ku, Tokyo Stock Company Copal (72) Inventor Yoshitaka Shimoyamada 2-16-20 Shimura, Itabashi-ku, Tokyo Stock Association Company Copal

Claims (3)

[Claims] 1. An output transistor which operates according to on / off of a switch operated from the outside, a logic power supply which is turned on by a signal from the output transistor and outputs a predetermined voltage, and an output voltage of the logic power supply. A logic circuit that receives supply of power, performs predetermined processing according to the operation of the switch, and when the processing is completed, turns off the logic power supply to end voltage output, and outputs the logic power supply from the switch off operation. During a predetermined period until the capacitor is stopped and during a predetermined discharge period until the output voltage of the capacitor reaches a predetermined value, the output voltage from the capacitor suppresses the operation of the output transistor. An on-off control circuit comprising: a suppressing unit. 2. The circuit according to claim 1, further comprising: an oscillation circuit that oscillates when supplied with a voltage from the logic power supply, and an output from the oscillation circuit is compared with a predetermined threshold value to output the output of the logic power supply. A reset pulse generation circuit that generates a reset pulse until the output of the oscillation circuit rises above a predetermined threshold value when the voltage rises, the output of the logic power supply during a predetermined discharge period of the capacitor. An on / off control circuit characterized in that an output of an oscillation circuit is longer than a threshold value in a reset pulse generation circuit due to stoppage for a longer period. 3. The circuit according to claim 1, wherein the suppressing unit is connected to the base of the output transistor and is turned on by the output voltage of the capacitor, thereby turning on the base of the output transistor. An on / off control circuit having a suppressing transistor which is fixed to a predetermined potential and suppresses its operation.