JPH07282023A - Data transfer amount variable processor and system using the same - Google Patents

Abstract

PURPOSE:To reduce the use rate of a communication bus and to improve the processing ability of a multiprocessor by providing a memory access control part executing the access making data transfer amounts to be different in a memory bus and a transfer bus for a processor. CONSTITUTION:The processor 100, is provided with a judgement unit for memory space range designation 101, a memory access control 102, a memory bus control 103, a transfer bus control 104, a prefetch unit 105, an instruction cache unit 106, a data cache unit 107 and an arithmetic unit 108. It is judged whether data to be accessed is in a distributed memory corresponding to the processor 100 or in the other memory. For executing the access based on the judgement, the data transfer amount of access is changed, namely, the data transfer amount to the transfer bus 111 is reduced compared to that to the memory bus 110. Thus, the use time of the transfer bus 111 per one time becomes short, the use rate of the transfer bus 111 is reduced and a high speed processing can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, and more particularly to a variable data transfer amount processor in a shared distributed memory.

[0002]

2. Description of the Related Art As a conventional multiprocessor system having a shared distributed memory, JP-A-56-155465, JP-A-1-134656, JP-A-2-244253, and JP-A-4-326453.
As described in No. 3, a plurality of processors and a shared memory device are connected by a communication (transfer) bus so that all or part of the physical address space can be accessed from each processor.

In these known techniques, the processor or the instruction processing device including the processor and the distributed memory accesses the data space to be accessed to its own distributed memory memory space or to another distributed memory memory space. If it is in its own distributed memory space, the access request is output to its own distributed memory device, and if it is not in its own distributed memory space, the access request is output to another distributed memory device through the communication bus.

[0004]

The multiprocessor system having the shared distributed memory shown in the above-mentioned prior art has a low number of requests for the communication bus as compared with an access to a single memory in which data is not distributed. The system can provide.

However, there is no description about the transfer amount of data or command (hereinafter, command is also treated as data) for one communication bus request.

Further, it is becoming common for a processor to have a cache memory built therein. In such a processor or system, there is no description of the relationship between the access when there is no cache hit and the prefetch that causes the memory access to the data that will be used in the future.

A first object of the present invention is to reduce the number of bus requests and optimize the transfer amount per time in a distributed shared memory type multiprocessor system in order to shorten the time occupied by the communication bus. , Lowering the usage rate of the communication bus and improving the processing capacity of the entire multiprocessor.

Further, a second object of the present invention is to perform a pre-fetch as much as possible while preventing a bus neck of a communication bus in a distributed shared memory type multiprocessor system so that the processing capability of the entire multiprocessor is improved. It is to provide a system to improve.

[0009]

In order to achieve the above first object, a distributed memory that holds data in a distributed manner is accessed through a memory bus, and at least one other distributed memory is accessed through a transfer bus. The processor is characterized in that it has a memory access control unit that accesses the memory bus and the transfer bus with different amounts of data transferred.

Further, in order to achieve the above-mentioned second object, a distributed memory for distributing and holding data is accessed via a memory bus, and at least one other distributed memory is accessed via a transfer bus. A processor for processing data, wherein the processor is an operation unit for processing data, a cache memory unit for holding a part of the data held in the distributed memory, and the cache according to the processing of the operation unit. A prefetch unit for writing data to the memory unit, and if the data written in the cache memory unit by the prefetch unit is not the data accessed by the arithmetic unit, the prefetch unit performs the next processing of the arithmetic unit. In response to writing the next data to the cache memory unit, the next write data is It has a memory access control unit that determines whether the data is held in a distributed memory or another distributed memory, and accesses the memory bus and the transfer bus with different data transfer amounts. To do.

[0011]

According to the first feature described above, it is determined whether the data to be accessed is in the distributed memory corresponding to the processor or another distributed memory, and based on the determination, the access data transfer is performed. The amount is changed, that is, the data transfer amount to the transfer bus is made smaller than the data transfer amount to the memory bus. As a result, the usage time of each transfer bus is shortened, and as a result, the usage rate of the transfer bus is reduced, and high-speed processing is achieved by the processor or the entire system.

Further, the second purpose is that the processor performs a memory access in advance to the cache memory having a copy of the data in the main memory and the data which will be used in the future according to the processing of the processor. When the prefetch request prefetch data does not exist, the prefetch unit has a preceding prefetch unit, and it is determined whether or not the requested address is within the memory space of the distributed memory corresponding to the processor, and the memory to be accessed according to this determination result. The data transfer amount according to the space, that is, generally, the data transfer amount to the transfer bus is made smaller than the data transfer amount to the memory bus for access. This allows the transfer bus 1
The usage time per operation is shortened, and as a result, the usage rate of the transfer bus is reduced.

Further, the memory access by the pre-fetch is not performed to the memory device outside the instruction processing means. As a result, the number of accesses to the transfer bus is reduced, and as a result, the usage rate of the transfer bus is reduced.

By thus reducing the usage rate of the transfer bus, the number of multiprocessors can be increased or the bus waiting time can be reduced to improve the system performance.

[0015]

1 is a block diagram of a processor according to this embodiment. 100 is a processor, 101 is a determination unit for specifying a memory space range, 102 is memory access control, 103
Is a memory bus control, 104 is a transfer bus control, 105 is a prefetch unit, 106 is an instruction cache unit,
107 is a data cache unit, and 108 is an arithmetic unit. The buses connected to the outside from the processor are the memory bus 110 and the transfer bus 111.

FIG. 2 shows the configuration of a shared distributed memory type multiprocessor using the processor shown in FIG. The processor 201, the distributed memory-1 (205), and the memory bus 215 connecting them constitute one instruction processing unit, and a plurality of them are provided and a transfer bus 21 is provided between the processors.
Connect with 3. 201 to 204 are the processors shown in FIG. 1, 205 to 208 are distributed memories, and 209 is I / O.
The controllers 210 to 212 are composed of I / O devices such as a display, a printer and a disk. Focusing on the processor-1 (201), the transfer bus 111 of the processor 100 of FIG. 1 is the transfer bus 213 of FIG.
Connected to the memory bus 11 of the processor 100 of FIG.
0 is connected to the memory bus 215, and the same applies to the processors 202 to 204.

The address space of the distributed memory of FIG. 2 is shown in FIG. The system of this embodiment has a physical address of 4 Gbytes and has a memory map I / O configuration. Therefore, the address space seen from each processor (210 to 204) is 4 Gbytes, and the address X'F00000
00 to X'FFFFFFFF is the I / O space. The distributed memories 205 to 208 in FIG. 2 are allocated the mounting address spaces of the distributed memories shown in FIG. 3 and are mounted on the respective distributed memories.

First, the basic operation of the multiprocessor system will be described with reference to FIGS. 1 to 3, and then the detailed operation inside the processor will be described.

In FIG. 2, considering the processor-1 as a reference, the processor-1 has the address X'00000010.
When accessing the address 0, the processor-1 recognizes that it is an access to the distributed memory-1 directly connected to the processor-1, and the processor-1 activates the memory bus 215. Distributed memory-1
Access (205). On the other hand, processor-1
When accessing the address X'4F000000, the processor-1 recognizes that it is an access to the transfer bus under the control of the processor-1.
Processor-1 activates the transfer bus 213. Processors-1 through 4 (201-204) are constantly monitoring the transfer bus, and in this case, processors-2 through 4 check to see if they are accessing distributed memory directly connected to each processor. In this example, the processor-2 recognizes that it is an access to the distributed memory-2 directly connected to it and receives data. The processor-2 connects the transfer bus and the memory bus 216 inside the processor-2 in preparation for accessing the distributed memory-2 from the data received from the transfer bus. By such a series of operations, the processor-1 (201) and the transfer bus (21
3), the processor-2 (202), the memory bus 216, and the distributed memory-2 (206) can be connected and accessed. Further, the processor-1 has the address X'F10.
When accessing the address 00000, the processor-1 recognizes that the access is to the transfer bus under the control of the processor-1, and the processor-1 activates the transfer bus 213. In this embodiment, the I / O controller 209 monitors the transfer bus 213, recognizes that the access is to the I / O area, and receives the data. After that, the I / O controller 209 changes the I / O device 2
The transfer bus and the I / O bus are connected in the I / O controller 209 to access 10 to 212. Through such a series of operations, the processor-1 (201), the transfer bus (213), the I / O controller 209, the I / O bus (214), and the I / O devices (210 to 212) are connected and accessed. You can

In the multiprocessor of this embodiment, a cache memory is built in each processor, and each processor has a snoop cache structure for monitoring the transfer bus as a matching means for always matching the data in the main memory. In this embodiment, when a processor confirms the data consistency with the cache memory in another processor, it outputs a CCC (cache coherent check) request. The CCC request is broadcast over the transfer bus with the address to be checked. In this embodiment, since the address array inside the processor has two ports, it is possible to check the internal operation independently of each processor. In addition, the processor
Even when the processor 1 makes a cache miss and is accessing the distributed memory -1 from the processor-1, the CCC request from another processor can be independently executed.

Next, a detailed operation will be described, centering on the characteristic part of the present invention inside the processor.

The operation of basic instructions of the processor 100 shown in FIG. 1 will be described with reference to FIGS. FIG. 4 shows a detailed configuration of the arithmetic unit 108. Arithmetic unit 108
Is a register 1301, an arithmetic unit 1302, an instruction buffer register 1303, an instruction decoder 1304, a program counter 1305, a branch ADDER 1306, a load instruction byte aligner 1308, a store instruction byte aligner 1307, and an interrupt processing address generator 13.
09, latches 1310a-k for executing the pipeline,
It is composed of a pipeline control 1312, an address generation circuit 1313 for conditional branch nottaken.

FIG. 5 shows the configuration of the instruction cache unit 106. Reference numeral 1201 is a logical address latch, 1202 is an instruction TLB, 1203 is an address cache address array, 1204 is an address storage memory, 1205 is a data storage buffer and prefetch buffer, 1206 is an instruction operand storage memory, 1207 is an instruction cache control unit, 1210. Is a TLB VPN (virtual page) comparator, 1211 is a TLB protection information comparator, 1212 is an address array comparator, and 1213.
Is composed of selectors. The TLB and the instruction cache adopt a direct map method, the instruction TLB has 128 entries, and the capacity of the instruction cache is 1K entry and 32K bytes.

FIG. 6 shows the configuration of the data cache unit 106. 1001 is a logical address latch, 1002
Is a TLB for data, 1003 is an address array for data cache, 1004 is an address storage buffer, 1005
Is a data storage buffer, 1006 is a data operand storage memory, 1007 is a data cache control unit, 10
10 is a TLB VPN (virtual page) comparator, 1
011 is a TLB protection information comparator, 1012
Is a comparator for address array, 1013 is a selector, 10
Reference numeral 14 is a comparator for CCC (cache coherence check). The TLB and the instruction cache adopt the direct map method, the data TLB has 128 entries, and the capacity of the data cache is 1K entry and 32K bytes.

The pipeline operation is executed in 6 stages as shown in FIG. The instruction set has operation instructions between registers, branch instructions, load instructions, and store instructions used in general RISC. Since the basic operation of these instructions is not directly related to the present invention, only the instruction fetch and data fetch portions related to memory access will be described.

In the IF stage, in the instruction cache unit 106, the instruction address 123 from the arithmetic unit 108 is transferred to the logical address latch 1201 as shown in FIG.
, And the instruction fetch request 124 activates the instruction cache unit 106. The logical address is divided into a block address of 2-4 bits, a block address of 5-14 bits, and a page address of 12-31 bits. In normal operation, the page address is T
The logical address is converted to a physical address by the LB. The page address of 12-31 bits is 12-18
The entry in the instruction TLB is selected by bits, and the read address 1202a and the address of 19-31 bits are compared via the comparator 1210, and when they match, the TLB
It becomes a hit. Further, the protection information 1202c is read out from the selected entry and checked through the management register and the comparator 1211. Address are 1203
Is 5-14 bits of the logical address and 1 in the address array
Select one of the K entries. The physical address page (PPN) 1203a read out and the physical address page (PPN) 1202b read out from the instruction TLB are compared by the comparator 1212, and when they match, a cache hit occurs.

The instruction cache address array is 8
The four sub-block valid bits 1203b are stored so that processing can be performed in byte units. FIG. 8A shows the internal information of 1203b per entry. Furthermore, FIG.
The combination of BV1 to 4 is shown in (b). A constraint is set that allows only consecutive sub-blocks in the same block. On the other hand, the instruction operand storage memory 1206 selects one of the 1K entries in the instruction operand storage memory with 5-14 bits of the logical address. The selected 32-byte instruction operand is added to the block address 2
If -8 is selected by -5 bits, a 4-byte instruction is sent to the instruction buffer register 1303 in the arithmetic unit 108 through the operand bus 122.

By the way, the load instruction is the operation unit 1
The data address 126 from 08 is set in the logical address latch 1001 as shown in FIG.
Starts up on 7. The logical address is divided into a block address of 2-4 bits, a block address of 5-14 bits, and a page address of 12-31 bits. The page address is converted from the logical address to the physical address by the TLB. The page address of 12-31 bits selects an entry in the data TLB by 12-18 bits, and the read address 1002a and the address of 19-31 bits are compared via the comparator 1010. It becomes a hit. Further, the protection information 1002c is read out from the selected entry and checked through the management register and the comparator 1011.
The address array 1003 selects one of the 1K entries in the address array by 5-14 bits of the logical address. Physical address page (PPN) 100 read out
3a and the physical address page (PPN) 1002b read from the data TLB are compared by the comparator 1012, and when they match, a cache hit occurs.

The data cache address array stores four sub-block valid bits 1003b so that processing can be performed in units of 8 bytes. The sub-block has the same structure as the instruction cache. On the other hand, the data storage memory 1006 selects one of the 1K entries in the data storage memory with 5-14 bits of the logical address. When the selected 32 bytes of data are further selected to 1/8 by the address 2-5 bits in the block, a 4-byte instruction is sent to the arithmetic unit 108 through the data bus 125.

In the operation of the store instruction, the data address 126 from the arithmetic unit 108 is set in the logical address latch 1001 at the E stage, and the data request 12
4 (store request) activates the data cache unit. In the T stage, the data to be written is sent from the arithmetic unit 108 through the data bus 125 to the data cache unit 107 and stored in the data storage buffer 1005. Comparator 1010, 1011, 1
As a result of 012, TLB hit, protection hit,
If it is a cache hit, it is written to the data storage memory 1006 at the W stage of the store instruction and the instruction is completed.

As shown in this embodiment, in response to a memory access request from an arithmetic unit inside the processor, if data is present in the built-in cache memory, data corresponding to the memory access request can be supplied.

Next, returning to FIG. 1, memory access from the instruction cache unit 106 and the data cache unit 107 to the outside of the chip will be described with reference to FIGS.
1, described with reference to FIG.

FIG. 9 shows the configuration of the memory space range designation determination unit 101, which is a self-memory space lower limit value storage register 401 in a distributed shared address, a self memory space upper limit value storage register 402 in a distribution address, and an internal address bus 140. Circuit 40 for comparing the lower limit value register 401 with the lower limit value register 401
3, it comprises a comparison circuit 404 for comparing the internal address bus 140 and the upper limit register 402, and a judgment circuit for judging whether or not an internal address is contained in its own memory space.

FIG. 10 shows the configuration of the memory access control 102, which comprises a mask circuit 102a, a priority determination circuit 102c, a bus activation circuit and bus arbiter 102d, a prefetch interface control 191, an instruction cache unit interface control 1902, and a data cache unit interface control 1903. To be done.

FIG. 11 shows a memory bus control 103, which is a memory control circuit 501, a data buffer circuit 502, an address buffer circuit 503, switches 504, 505, and 5.
It is composed of 06.

FIG. 12 shows a transfer bus control 104, which includes a transfer bus control circuit 901, data buffer circuits 902 and 90.
3, address buffer circuits 904, 905, and switches 906 to 910.

Next, the operation when the instruction request 133 is asserted from the instruction cache unit 106 will be shown.

If a cache miss occurs as a result of comparison by the address comparator 1212 in the instruction cache unit 106, the instruction cache control unit 1207 causes the arithmetic unit 1 to operate.
08 is instructed to wait for pipeline processing (not shown in the figure), and an instruction fetch request is issued to the memory access control 102 through the signal 133. The address storage buffer 1204 generates a physical address and outputs it as an instruction address 139 to the internal address bus 140 via the selector 109. The memory space designating determination unit constantly monitors the internal address bus 140.

Judgment unit 101 for specifying memory space range
The operation of will be described. When starting up the system, each processor stores 40 pieces of data to be set in the lower limit value storage register 401 and the upper limit value storage register 402 by software.
Set via 6. The buses 407 for reading and 406 for writing are registers 1301 in the arithmetic unit.
Data can be transferred by using the transfer command for the control register (not shown in the figure). Each processor sets the lower and upper limits of each distributed memory that can be accessed directly via the memory bus. In the case of the present embodiment, the values shown in FIG. 13A are set according to FIG.

The comparison circuit 403 uses the internal address bus 140.
Operates to detect that is lower than or equal to the lower limit register 401. The comparison circuit 404 uses the internal address bus 1
It operates to detect that 40 is less than or equal to the upper limit register 401. The determination circuit 405 inputs the output 410 of the comparison circuit 403 and the output 420 of the comparison circuit 404, and determines that it is within the space of the directly connected distributed memory. The determined signal 139 is the memory access control 102.
Sent to. The determination circuit 405 can be realized by a logical product of the signal lines 410 and 420.

The request 133 from the instruction cache enters the priority determination circuit 102c. When several requests arrive at the same time, 102c orders the requests. When the request from the instruction cache is selected as a result of the priority determination, the signal 1907 is asserted. This signal is a request that the processor internal request has been selected to the outside. Bus startup circuit and bus arbiter 1
02d determines, together with requests 146 and 148 from the outside, which request has priority, and accepts the request with the highest priority. When request 1907 is accepted,
The bus start circuit and the bus arbiter 102d are the memory bus 1
The signal 139 determines which of 10 and the transfer bus 111 is to be activated. If 139 is asserted, a block transfer (32 bytes) request is output to the memory bus control 103 via the signal 145. If 139
Is negated, the sub-block transfer (8 bytes) request is output to the transfer bus control 104 through the signal 147. The reason why the transfer amount is different between the memory bus and the transfer bus is that the memory bus is a transfer means to the distributed memory that the processor can directly access, but the transfer bus is a transfer means to access the distributed memory of another processor. This is because the four processors are shared and the transfer bus usage rate is reduced by reducing the transfer amount.

Further, the priority determination circuit 102c outputs the signal 19
05 is asserted to notify the instruction cache unit interface control 1902 that the request has been accepted. The instruction cache unit interface control 1902 creates a signal responding to the instruction cache unit 106 by the signal 1905 and the signal 139 from the memory space range designation determination unit 101. 134a
Is a response signal and is asserted when the request is accepted. Reference numeral 134b is ancillary information, which is for responding whether the block transfer (32 bytes) or the sub-block transfer (8 bytes) is accepted. This 134
instruction cache unit 10 which has received a and 134b
6 knows that the request has been accepted and that the block size for the request is block transfer or sub-block transfer, and waits for data to arrive accordingly.

The operation when the request from the instruction cache memory is an access to the memory directly connected to the processor will be described. Memory bus control 103
Is activated by the memory bus request 145.
The operation of the memory bus control 103 is a signal 510, 516, 51 for switching the switch operation by reading and writing to the distributed memory.
Control using 7,518.

Next, the operation when the request from the instruction cache memory is an access to another distributed memory (that is, an access to the transfer bus) that is not an access to the memory directly connected to the processor will be described. The transfer bus control 104 is activated by the transfer bus request 147. The operation of the memory bus control 104 includes distributed memory not directly connected to the processor, read to I / O,
Write access, switch operation signal 930, 93
1, 933, 933, 934, 935 are used for control.

In the transfer bus control, the switches 909 and 910 are controlled so as to connect 111 and 142 when the transfer bus 11 is not activated by the request.
1 can be monitored through the internal cache coherent check address.

The data read from the memory bus or transfer bus as described above is transferred to the instruction cache unit 106 through the internal bus 141. At the same time, the control signal is
It is reported to the memory access control 102 from 146 or 148, and in response to this, it is transmitted to 102f and 134 and notified to the instruction cache unit 106.

Next, the data cache unit 107
Shows the operation when the data request 135 is asserted. The request 135 from the data cache enters the priority determination circuit 102c. If the request from the data cache is selected as a result of the priority determination, the signal 1907 in FIG. 10 is asserted. When the bus activation circuit 102d receives the request 1907, the bus activation circuit outputs a signal 1 indicating whether to activate the memory bus or the transfer bus.
It judges from 39. If 139 is asserted, a block transfer (32 bytes) request is output to the memory bus control 103 via the signal 145. If 139 is negated, a sub-block transfer (8 bytes) request is output to the transfer bus control 104 through the signal 147.

Further, the priority determination circuit 102c outputs the signal 19
Assert 06 to notify the data cache unit interface control 1903 that the request has been accepted. The instruction cache unit interface control 1903 creates a signal responding to the data cache unit 107 by the signal 1906 and the signal 139 from the memory space range designation determination unit 101. Thirteen
Reference numeral 6a is a response signal, which is asserted when the request is accepted. Reference numeral 136b is ancillary information, which is used to respond whether the block transfer (32 bytes) or the sub-block transfer (8 bytes) is accepted. This one
The data cache unit 107 that has received 36a and 136b knows that the request has been accepted and that the block size for the request is block transfer or sub-block transfer, and waits for data to arrive accordingly.

The operation when the request from the data cache memory is an access to the memory directly connected to the processor will be described. Memory bus control 10
3 is activated by the memory bus request 145. The operation of the memory bus control 103 controls the operation of the switch by reading and writing to the distributed memory 510, 516 and 516.
It controls using 517 and 518.

The operation in the case where the request from the instruction cache memory is an access to another distributed memory (that is, an access to the transfer bus) which is not an access to the memory directly connected to the processor will be described. Transfer bus control 10
4 is activated by the transfer bus request 147. The operations of the memory bus control 104 are distributed memory not directly connected to the processor, read / write access to I / O, switch operation signals, 930, 931 and 93.
2, 933, 934, 935 are used for control.

The data read from the memory bus or the transfer bus is transferred to the data cache unit 107 through the internal bus 141. At the same time, the control signal is 14
6 or 148 reports to the memory access control 102, and in response to this, the data is transmitted to 102f and 136 and notified to the data cache unit 107.

At the end of the request from the inside of the processor to access the external memory, a prefetch method will be described in which the prefetch that is predicted in advance is performed so that the data to be memory-accessed already exists in the cache memory. It should be noted that the prefetch method has a feature that it is not necessary to actually fetch it because it is a method of predicting and performing prefetching. In this embodiment, instruction prefetch and data prefetch are performed. The concept is shown in FIGS. 14 (a) and 14 (b). The instruction prefetch (a) prefetches the next block when the instruction cache unit 106 makes a cache miss. The arithmetic unit in the prefetch unit calculates the address of the next block, and the information obtained by the memory access is prefetched. It is stored in the buffer.

The data prefetch (b) uses the post-increment of load and store instructions and the pre-decrement function.

The instruction functions of the load instruction and the store instruction are shown in FIG.
5 shows.

In the instruction "LOAD", the displacement + general-purpose register (b) serves as an address, and the content indicated by the address is stored in the general-purpose register (t). In the instruction "STORE", the displacement + general-purpose register (b) serves as an address, and the content of the general-purpose register (r) is written to the memory pointed to by the address.

Furthermore, each instruction has two more variations by addressing. "--- PI"
Calculates the displacement + general-purpose register (b) at the same time as the address of the general-purpose register (b) without calculating the address, and stores the value in the general-purpose register (b). This addressing mode has a so-called post-increment function. “−−− PD” indicates that displacement + general-purpose register (b) together with address, displacement + general-purpose register (b) at the same time.
Is stored in the general-purpose register (b).
This addressing mode has a so-called pre-decrement function when the displacement has a negative value.

Data prefetch (b) is performed when there is no request from the processor to the data cache.
The data cache unit is accessed by the modified address. If the data cache unit hits, the prefetch is completed, but if it misses, memory access is performed.

Next, the prefetch method will be described in detail. FIG. 16 shows a prefetch unit 105, which is a predecrement arithmetic unit 1401, and an instruction prefetch arithmetic unit.
1402, prefetch control circuit 1403, data prefetch address buffer 1405, instruction prefetch address buffer 1406, and selector 1407.

The operation of instruction prefetch will be described. When the signal 129 reports that a cache miss has occurred, the missed instruction address information (physical address) is output to the prefetch unit via 128. The instruction prefetch arithmetic unit 1402 performs arithmetic operation of instruction address information + 32 bytes. The result is the address of the block following the missed block. This value is stored in the instruction prefetch address buffer 1406. After that, the prefetch request is sent from the prefetch control circuit 1403.
2 and the prefetch address 130 are output. The request 132 is sent to the mask circuit 102a in the memory access control 102. Here, 1909 of FIG. 12 is asserted by the output 139 of the determination unit 101 for specifying the memory space range, if the self-distributed memory directly connected to the processor is accessed. Further, the priority determination circuit 102c asserts the signal 1904 to notify the prefetch unit interface control 1901 that the request has been accepted and has not been masked.
The prefetch unit interface control 1901 is
Signal 1904 and memory space range designation determination unit 10
Signal 139 from the memory comparison unit 403-405 of 1
Produces a signal in response to the prefetch unit 105. Reference numeral 131a is a response signal, which is asserted when the request is accepted. Reference numeral 131b is attached information, which is used for responding whether or not it is masked.
The prefetch unit 105 that has received these 131a and 131b knows that the request has been accepted and that the request has not been masked, and further informs the instruction cache unit 106 via the signal 129.

When request 1909 is asserted,
The bus start-up circuit and the bus arbiter 102d are normally signal 1
A request 145 is output according to 39. As a result, the self-distributed memory is accessed and the internal data bus 141 is accessed.
Through the data storage buffer and the prefetch buffer 1205 of FIG. At the same time, the control signal is 146
Alternatively, it is reported to the memory access control 102 from 148, and in response to this, the data is transmitted to 102f and 131 and notified to the prefetch unit 105. It also informs the instruction cache unit 106 via signal 129.

On the other hand, in the mask circuit 102a, the output 139 of the memory space range designation determination unit 101 causes
If the other distributed memory or I / O access is recognized, 1909 in FIG. 10 is negated. When negated, it means that the request ends at this part and prefetching to the transfer bus is not performed.

Further, the priority determination circuit 102c outputs the signal 19
04 is asserted to notify the prefetch unit interface control 1901 that the request has been accepted and masked. The prefetch unit interface control 1901 creates a signal responding to the prefetch unit 105 by the signal 1904 and the signal 139 from the memory space range designation determination unit 101. 1
Reference numeral 31a is a response signal, which is asserted when the request is accepted. Reference numeral 131b is attached information, which is used for responding whether or not it is masked. This 131
prefetch unit 105 that received a and 131b
Knows that the request has been accepted and has been masked for that request, and also informs the instruction cache unit 106 via signal 129.

That is, the instruction profetch request is issued from the prefetch unit 105, but it is judged in the memory access control 102 whether or not it is the self-distributed memory space, access is permitted only in the self-distributed memory space, and other than that. Controls that access to the address space is not permitted. This prevents the transfer bus from being activated by the predicted prefetch, and has the effect of reducing the usage rate of the transfer bus.

Next, the data prefetch operation will be described. Data prefetch has two methods until the prefetch address is output.

The instructions "LOADPI" and "STOREPI" having the post-increment function pass through the path 1411 in FIG. 16 for the data prefetch because the output of the arithmetic unit 1302 in the arithmetic unit 108 is a modify address. It is stored in the address buffer 1405.

On the other hand, the instructions "LOADPD" and "STOREPD" having the pre-decrement function are the arithmetic units 10
Since the output of the arithmetic unit 1302 in 8 does not become the modified address, the arithmetic unit 1401 calculates the calculation result + displacement. The result becomes a modified address and is stored in the data prefetch address buffer 1405 via the selector 1407.

According to two methods, the logical address stored in the data prefetch address buffer 1405 is sent to the data cache unit 107 as the prefetch address 150. It is received by the address storage buffer 1004 in FIG. 6 and stored in the logical address latch 1001 through 1023. The subsequent operation is similar to that of the data cache unit 107. That is, if the data cache unit is hit, signal 129
The completion is reported to the prefetch unit 105 via. On the other hand, if a miss occurs, the block transfer (32 bytes) if the access is within the self-distributed memory, and the sub-block transfer (8 bytes) if it is another distributed memory or I / O.
Prefetch unit 105 via signal 129
To report completion.

That is, the data prefetch operation is different from the instruction prefetch operation in that the data prefetch request is issued from the prefetch unit 105. However, since the address is a logical address, the data cache unit 107 first checks whether the data exists. Check whether or not. Then, if it is a hit, the prefetch is completed. If it is a miss, similar to the operation of the data cache unit, it is determined in the memory access control 102 whether or not the memory space is a self-distributed memory space, and block-wise access is permitted only in the self-distributed space, and the other address spaces The access is controlled to allow access in sub-block units, and the prefetch is completed. This has the effect of shortening the predicted use time of the transfer bus by prefetching.

The access to the external memory from the inside of the processor according to this embodiment has been described above, but the improvement of this embodiment will be described.

A system with a fixed distributed memory capacity has an upper limit,
The lower limit registers 401 and 402 may be fixed by hardware (for example, ROM memory).

Further, if the comparison circuit 404 always detects that the internal address bus 140 is smaller than the upper limit value register 402, the address can be set as shown in FIG. 13B.

Further, the increment / decrement unit of the distributed memory is, for example, 2
If it is limited to the 16th power of 64 (64 Kbytes), the upper 16 bits can be compared, and the values set in the registers 401 and 402 are as shown in FIG. As a result, the comparison circuits 403 and 404, the lower limit and the upper limit registers 401 and 402
Can be all 16 bits and can be miniaturized. Further, the determination unit 1 for specifying the memory space range shown in FIG.
As a modification of 01, the upper limit value or lower limit value address (specific base address) and its memory space range may be newly set, and it may be detected whether or not the internal address bus is within the specified range.

In the present embodiment, the register 4 described above is used.
02 X 'E FFFFFFF, by setting the value of X'00000000 lower limit register 401, it is possible to easily construct a system of single processor configuration.

[0074] Further, in this embodiment, the register 402 in the X 'F FFFFFFF, by setting the value of the lower limit register 401 X'00000000, it is readily constructed the system of single processor configuration using no transfer bus it can.

Further, in the present embodiment, when a value of X'EFFFFFFF is set in the register 402 and a value of X'EFFFFFFF is set in the lower limit register 401, only the transfer bus other than the address X'EFFFFFFF (prohibited address in the system) should be used. Therefore, a conventional multiprocessor system can be easily constructed.

Further, generally, when the transfer bus is accessed in sub-block units, the bus use time becomes short. However, depending on the application that accesses consecutive addresses, the block bus access (32 bytes) takes less time to use the transfer bus than the sub block access four times (8 bytes × 4). . This is because the initial operation until transfer is inevitable. Therefore, the bus activation control 102 can be improved so that the self-distributed memory is accessed in sub-block units and the other distributed memories are accessed in block units.

Further, in the prefetch, the control of the instruction and the data is changed in the present embodiment, but it is also possible to make the same for both the instruction and the data by a simple modification. It is also possible to exchange control of instructions and data. Now, returning to this embodiment,
From a different point of view, the processor access request from the outside of the processor will be described. Processor access is divided into two.

(1) Access to the distributed memory of this processor from another processor.

(2) Cache coherent check from another processor to the data cache memory of this processor.

The operation (1) will be described. The processor constantly monitors whether the address on the transfer bus 111 is within the self-distributed memory range by the transfer bus control circuit 901 through 932 (having the same judgment circuit as the judgment circuit in the memory space range designation judgment unit). , Within the range, the transfer bus 111 recognizes that there is an access request from the processor, and the transfer bus control circuit 901 determines that the transfer bus request 1
48 is output to the bus activation circuit and arbiter 102d shown in FIG. 10 to request permission to use the internal bus. Subsequent operations are controlled so that the memory bus and the transfer bus pass data, and the memory transfer is completed.

Next, the operation (2) will be described. The cache coherent check from another processor to the data cache memory of this processor is performed by the bus 9 in FIG.
The address to be checked is sent to the data cache unit via 27, 142. In the data cache unit 107 in FIG. 6, the data address array 1003 checks whether or not the cache having the same address is updated. One of 1K entries is selected by bits 5-14 of address 144. The read physical address page and the upper 13-32 bit address are compared by the comparator 1014. The output 1037 and the coherency information of the cache are checked by the data cache control unit 1007. If there is a cache miss, or if there is a hit but it has not been updated, the operation ends. However, when it is hit and updated, it is necessary to write back the cache data to the memory. This always guarantees data consistency.

The data address array 1003 has a two-port structure, and normal processor operation and cache coherent check can be executed simultaneously. Further, even when the processor misses the cache and is accessing the self-distributed memory, the processes can be executed in parallel without stopping either process. This has the effect of improving the performance of the multiprocessor.

As an improvement of this embodiment, the relationship with the memory space range designation storage and the comparison unit when the memory configuration and the system configuration are changed will be described with reference to FIGS. 17, 18, 19, and 20.

FIG. 17 shows the memory space of each distributed memory implemented by being divided into several ranges. The determination unit 101 for specifying the memory space range in such a case
Is the lower limit value storage registers 401, 4 as shown in FIG.
50, upper limit value storage registers 402 and 451, comparators 403 and 452 that compare that the internal address bus is larger than the register value, comparators 404 and 453 that compare that the internal address bus is smaller than the register value, respectively. It is composed of a determination circuit 454 for determining a region. In the initial state, processor-1 sets the upper and lower limit addresses of the area starting from X'00000000 to 401 and 402, and the upper and lower addresses of the area starting from X'70000000 to 450 and 451. Thereby, the memory space range of the distributed memory-1 can be recognized.

FIG. 18 shows the system configuration when a cluster hierarchy is added. This system is a cluster
1 (1650) and cluster-2 (1651). Further, 1601-1604 are processors, 160
4 to 1607 are distributed memories, 1608 to 1609 are I / O
An O controller, 1610 to 1611 are inter-cluster communication controllers, and 1612 is a net network. The configuration of each distributed memory space of the system is the same as in FIG. At this time, the values shown in FIG. 13A are set in the lower limit register and the upper limit register for the memory space range designation determination unit.

The operation of this system is shown in FIG.
Considering the processor -1 as a reference, when the processor -1 accesses the address X'00000100, it is an access to the distributed memory -1, which is directly connected to the processor -1, by the control inside the processor -1. Recognizing this, the processor-1 activates the memory bus-1 and accesses the distributed memory-1 (1604) in block units.

On the other hand, the processor-1 sends the address X'4F
When an address of 000000 is accessed, the processor-1 recognizes that the access is to the transfer bus under the control of the processor-1, and the processor-1 activates the transfer bus 1624 in sub-block units. The processors-1, 2 (1601, 1602) constantly monitor the intra-cluster transfer bus-12, and in this case, it is checked whether or not the processor-2 is accessing the distributed memory directly connected to each processor. . In this example, the processor-2 recognizes that it is an access to the distributed memory-2 directly connected to it and receives data. The processor-2 connects the transfer bus and the memory bus-2 inside the processor-2 in preparation for accessing the distributed memory-2 from the data received from the transfer bus. By such a series of operations, the processor-1 (1601), the intra-cluster transfer bus-12 (1624), the processor-2
(1602), memory bus-2, distributed memory-2 (16
05) to be connected and accessible.

Further, the processor-1 determines that the address X'E
When accessing the address F000000, the processor-1 recognizes that it is an access to the transfer bus under the control of the processor-1, and the processor-1 activates the intra-cluster transfer bus-12 in sub-block units, The network 1612 is accessed through the inter-cluster communication controller-12 (1610). After that, the intra-cluster transfer bus-34 is accessed through the inter-cluster communication controller-34 (1611). Processor
3, 4 (1603, 1604) are intra-cluster transfer buses-
34 is constantly monitored, and in this case, it is checked whether the processors 3 to 4 are accessing the distributed memory directly connected to each processor. In this example, the processor
4 recognizes that it is an access to the distributed memory 4 directly connected and receives the data. The processor-4 connects the intra-cluster transfer bus-34 and the memory bus-4 inside the processor-4 in preparation for accessing the distributed memory-4 from the data received from the intra-cluster transfer bus-34. By such a series of operations, the processor-1 (1604), the intra-cluster transfer bus-12
(1624), inter-cluster communication controller-12 (1
610), network 1612, inter-cluster communication controller-34 (1611), intra-cluster transfer bus-34
(1625), processor-4 (1604), memory bus-4, and distributed memory-4 (1607) can be connected to and accessed.

As a further improvement of the system of FIG.
Judgment unit 10 for specifying memory space range of each processor
1 is configured to be able to determine the designated range of two spaces as shown in FIG. At this time, the values set in each register are shown in FIG.
Shown in 1. The point to be noted here is that the registers 401, 4
02 is the range of the self-distributed memory, and the register 450,
451 is the range of the distributed memory in the cluster. By doing so, finer control is possible. For example, the operation of the system shown in FIG.
Considering 1 as a reference, processor-1 is distributed memory-1
(1604) in block units (32 bytes), distributed memory-2 (1605) in two sub-block units (16 bytes), and distributed memories -3 to 4 (1606 to 1607). It is also possible to activate access in sub-block units (8 bytes). Specifically, if 139a is asserted by the determination circuit 454, block transfer is performed, 139a is negated, 1
Two sub-block transfers when 39b is asserted, 139
The bus activation control 102 controls so that subblock transfer is performed when both a and 139b are negated. That is, it is possible to change the block transfer amount for each of the self-distributed memory, the distributed memory in the cluster, and the distributed memory between the clusters. At this time, in addition to the address, data, and protocol control signals as the protocol of the transfer bus, it is necessary to be able to send the size of the transfer amount which is the unit of access together with the control signal.

Further, for the memory access by the preceding prefetch, the processor-1 uses the distributed memory-1 (1
Block unit (32 bytes) access to
Furthermore, distributed memory-2 and distributed memories-3 to 4 (160
It is also possible not to access 6 to 1607).

Although this embodiment considers only the primary cache memory, FIG. 22 shows processors 201 to 204.
Is a system configuration in the case where has a secondary cache. A feature is that each processor 201 to 204 is connected to the secondary cache memory (4101 to 4104) through a dedicated cache bus. The development of the present invention when each processor has the secondary cache configuration can be easily analogized by those skilled in the art, and therefore the description thereof will be omitted.

Further, FIG. 23 shows a block diagram of a multiprocessor configuration inside the processor as an improvement of FIG. This processor is an arithmetic unit
1, arithmetic unit-2, main signals are 4214, 4
221 is an instruction address bus, 4213 and 4220 are operand buses, 4215 and 4222 are control signals with the instruction cache, 4211 and 4224 are data address buses,
4210 and 4223 are data buses, 4212 and 4225
Is a control signal for the data cache. The instruction cache unit 106 and the data cache unit 107 have a two-port cache memory configuration, and the arithmetic unit 4201 and the arithmetic unit 4202 are multiprocessors that share a built-in cache memory. The present invention can be developed even when a multiprocessor configuration is adopted inside such a processor.

[0093]

The first effect of the present invention is to reduce the number of bus requests and optimize the transfer amount per time in a distributed shared memory type multiprocessor system in order to shorten the time occupied by the communication bus. To reduce the usage rate of the communication bus and improve the processing capacity of the multiprocessor as a whole.

Furthermore, the second effect of the present invention is that, in a processor system, the most important thing is that the data to be memory-accessed already exists in the cache memory, and the data to be used in the future is Prefetch that causes memory access in advance
It is an object of the present invention to provide a system for improving the processing performance of the entire multiprocessor by performing as much as possible without causing a bus neck of the transfer bus.

[Brief description of drawings]

FIG. 1 is a block diagram of a processor according to an embodiment.

FIG. 2 is a configuration of a shared distributed memory multiprocessor using the processor shown in FIG.

3 is an address space of the distributed memory of FIG.

FIG. 4 shows a configuration of an arithmetic unit 108.

FIG. 5 shows the configuration of the instruction cache unit 106.

FIG. 6 shows a configuration of a data cache unit 107.

FIG. 7: Pipeline operation.

FIG. 8 is internal information of a sub-block effective bit.

FIG. 9 is a configuration of a memory space range designation determination unit 101.

FIG. 10 shows a configuration of memory access control.

FIG. 11 is a configuration of a memory bus control 103.

FIG. 12 shows a configuration of a transfer bus control 104.

FIG. 13 is an address value set in each of the system configuration lower and upper limit registers.

FIG. 14 is a conceptual diagram of instruction and data prefetching.

FIG. 15 is an instruction function of a load instruction and a store instruction.

16 is a configuration of a prefetch unit 105. FIG. System configuration when cluster hierarchy is added.

FIG. 17 is a memory space of each distributed memory when implemented by being divided into a plurality of ranges.

FIG. 18 is a system configuration when a hierarchy is formed by clusters.

FIG. 19 shows a configuration of a memory space range designation determination unit 101 capable of determining designated ranges of two spaces.

20 is a determination circuit having the configuration of FIG.

FIG. 21 is an address value set in each lower limit and upper limit register of the system configuration when a hierarchy is formed by clusters.

FIG. 22 is an example of a system having a two-tier cache.

FIG. 23 shows an example of an on-chip multiprocessor.

[Explanation of symbols]

100 ... Processor, 101 ... Judgment unit for specifying memory space range, 102 ... Memory access control, 103 ... Memory bus control, 104 ... Transfer bus control, 105 ... Prefetch unit, 106 ... Instruction cache unit, 1
07 ... Data cache unit, 108 ... Arithmetic unit, 110 ... Memory bus, 111 ... Transfer bus, 122 ...
Operand bus, 123 ... Instruction address, 125 ... Data bus, 126 ... Data address, 130 ... Prefetch address, 131 ... Response signal to request 132, 132 ... Prefetch request, 133 ... Instruction address request, 134 ... Response corresponding to request 133 Signal, 135 ... Data address request output from data cache unit, 136 ... Response signal to request 135, 137 ... Instruction address output from instruction cache unit, 139 ... Memory space range designation storage, output from comparison unit Range designation result signal, 140 ... Internal address bus, 141 ... Data cache unit 107, instruction cache unit 106, memory bus control 103, transfer bus control 104
Internal data bus connecting 145 ... Memory bus activation request output from bus activation control, 147 ... Transfer bus activation request, 201-204 ... Processor shown in FIG. 1, 205-208 ... Distributed memory, 209 ... I / O controller, 210-212 ... display, printer,
I / O devices such as disks, 213 ... Transfer bus, 21
4 ... I / O bus, 215-218 ... Each processor 201
To 204 connect to distributed memories 205 to 208.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Michio Morioka 7-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory

Claims (14)

[Claims] 1. A processor for processing distributed data by accessing a distributed memory, which holds data in a distributed manner, via a memory bus, and at least one other distributed memory via a transfer bus. Is a variable data transfer amount processor having a memory access control unit that accesses the memory bus and the transfer bus by making the data transfer amount different. 2. A processor for processing data by accessing a distributed memory, which holds data in a distributed manner, via a memory bus, and at least one other distributed memory via a transfer bus to process data. Determines whether the data to be accessed is held in the distributed memory or in the other distributed memory, and if it is held in the distributed memory, the data is accessed with the first transfer amount via the memory bus. A variable data transfer amount processor having a memory access control unit for accessing the second transfer amount via the transfer bus if it is held in the other distributed memory. 3. A processor which processes distributed data by accessing a distributed memory for holding data in a distributed manner via a memory bus and accessing at least one other distributed memory via a transfer bus. Holds the address space information of all distributed memories, and holds the address of the data accessed by the processor based on the address space information whether the data to be accessed is held in the distributed memory or in another distributed memory. If the memory space range determination unit determines whether or not the memory space range determination unit determines whether or not the memory space range determination unit determines whether or not the memory space range determination unit determines whether or not the memory space range determination unit determines whether or not the memory space range determination unit determines whether or not the memory space range determination unit determines whether or not the memory space range determination unit determines whether or not the memory space range determination unit determines whether or not it is stored in the distributed memory. Memory access with a second transfer amount via the transfer bus if held in distributed memory A variable data transfer processor having a control unit. 4. A processor for processing data by accessing a distributed memory, which holds data in a distributed manner, via a memory bus, and at least one other distributed memory via a transfer bus to process the data. Has a calculation unit for processing data and a cache memory unit for holding a part of the data held in the distributed memory, and if the cache memory unit does not hold the data accessed by the calculation unit, It has a memory access control unit that determines whether the data is held in the distributed memory or the other distributed memory, and accesses the memory bus and the transfer bus with different data transfer amounts. Variable data transfer processor. 5. A processor for processing distributed data by accessing a distributed memory holding distributed data through a memory bus and accessing at least one other distributed memory through a transfer bus. Has a calculation unit for processing data and a cache memory unit for holding a part of the data held in the distributed memory, and if the cache memory unit does not hold the data accessed by the calculation unit, It is determined whether the data to be accessed is held in the distributed memory or in the other distributed memory, and if it is held in the distributed memory, the data is accessed with the first transfer amount via the memory bus. , A memory access control unit for accessing at a second transfer amount via the transfer bus if held in the other distributed memory A variable data transfer amount processor having: 6. A processor for processing data by accessing a distributed memory, which holds data in a distributed manner, via a memory bus, and at least one other distributed memory via a transfer bus to process the data. Is a computing unit that processes data, a cache memory unit that holds a part of the data held in the distributed memory and determines whether the data that the computing unit accesses is held, and all distributed memories If the address data of the data to be accessed is determined not to be held in the cache memory unit, the address of the data to be accessed is determined based on the address space information. Memory space range determination unit that determines whether the data is stored in According to the determination of the memory space range determination unit, if the data is held in the distributed memory, the first transfer amount is accessed through the memory bus, and if it is held in the other distributed memory, the transfer bus A data transfer amount variable processor, comprising a memory access control unit for accessing at a second transfer amount via. 7. A processor for processing distributed data by accessing a distributed memory for holding data in a distributed manner via a memory bus and accessing at least one other distributed memory via a transfer bus. Has a calculation unit that processes data, a cache memory unit that holds a part of the data held in the distributed memory, and a prefetch unit that writes data to the cache memory unit according to the processing of the calculation unit. If the data written in the cache memory unit by the prefetch unit is not the data accessed by the arithmetic unit, the prefetch unit writes the next data in the cache memory unit according to the next processing of the arithmetic unit. In order to ensure that the data to be written next is stored in the distributed memory, A data transfer amount variable processor, comprising: a memory access control unit that determines whether or not the data is held in memory, and accesses the memory bus and the transfer bus by making the data transfer amount different. 8. A processor for processing data by accessing a distributed memory that holds data in a distributed manner via a memory bus and at least one other distributed memory via a transfer bus to process the data. Has a calculation unit that processes data, a cache memory unit that holds a part of the data held in the distributed memory, and a prefetch unit that writes data to the cache memory unit according to the processing of the calculation unit. If the data written in the cache memory unit by the prefetch unit is not the data accessed by the arithmetic unit, the prefetch unit writes the next data in the cache memory unit according to the next processing of the arithmetic unit. In order to ensure that the data to be written next is stored in the distributed memory, Memory is determined, and if it is retained in the distributed memory, access is performed with the first transfer amount via the memory bus,
A data transfer amount variable processor having a memory access control unit for accessing at a second transfer amount via the transfer bus if it is held in the other distributed memory. 9. A processor for processing distributed data by accessing a distributed memory for holding data in a distributed manner via a memory bus and accessing at least one other distributed memory via a transfer bus, the processor comprising: Is an arithmetic unit that processes data, a cache memory unit that holds a part of the data held in the distributed memory and determines whether the data accessed by the arithmetic unit is held, and Data is written to the cache memory unit according to the processing, and if the data written in the cache memory unit is not the data accessed by the calculation unit, the data is written to the cache memory unit according to the next process of the calculation unit. Of the prefetch unit that writes the data of and the address space information of all distributed memory, A memory space range determination unit that determines whether the next write data is stored in the distributed memory or in the other distributed memory based on the address space information,
According to the determination of the memory space range determination unit, if the memory is held in the distributed memory, the first data is transferred via the memory bus.
A data transfer amount variable processor, comprising: a memory access control unit for accessing the transfer amount according to the second transfer amount via the transfer bus if the memory access control unit accesses the transfer amount according to the second transfer amount. 10. The data transfer amount variable processor according to any one of claims 1 to 9, the data transfer amount variable processor is connected to the data transfer amount variable processor by a memory bus, and the distribution has different address areas of all address areas. A distributed processing system comprising a plurality of instruction processing units each comprising a memory, and the respective instruction processing units being connected by a transfer bus. 11. The distributed processing system according to claim 10 is used as one cluster, and the plurality of clusters are provided, each of the clusters being connected by an inter-cluster communication control unit and a communication net network, and information between the clusters. The transfer amount is
An information processing system, which is different from the data transfer amount in the distributed processing system. 12. The inter-cluster communication control unit according to claim 11, wherein an address, data, a protocol control signal, and a data transfer amount are set and transmitted as a transfer bus protocol to another cluster via the communication network. An information processing system characterized by: 13. The information processing system according to claim 12, wherein when the data transfer amount is zero, the access to the zeroed address space is stopped. 14. The cache memory according to claim 4, wherein the cache memory has a block size divided into n sub-blocks, and a data transfer amount is (0 to n) × block size. A characteristic information processing system.