JPH07288972A - Charge pump booster circuit - Google Patents

Abstract

PURPOSE:To widen the operating voltage range of the entire system by providing two charge pump booster circuits for doubling an input voltage and connecting them in cascade such that the output voltage from the prestage booster circuit is fed to the input of the next stage booster circuit. CONSTITUTION:Two charge pump booster circuits 1, 2 are provided and connected in cascade such that the output voltage from the prestage booster circuit 1 is fed to the input of the next stage booster circuit 2. Since each booster circuit 1, 2 produces an output voltage Vo=2Vi for an input voltage VI, when an input voltage -VI is fed to the booster circuit 1, an output -2Vi is fed to the input of the booster circuit 2 which then produces an output -4Vi. Consequently, a booster circuit at n-th stage produces an output -2<n>.Vi. This circuitry widen the operating voltage range of the entire system and produces a high output voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage boosting circuit, for example, for a liquid crystal display driver, and more particularly to a charge pump type boosting circuit.

[0002]

2. Description of the Related Art Conventionally, when a selection / non-selection voltage of a liquid crystal display driver for a medium-sized, small-sized, non-gradation liquid crystal panel is, for example, 1/3 bias, a double booster circuit as shown in FIG. with 3-times boosting circuit, the original power supply voltage (e.g., V _DD), the input voltage of the booster circuit (V _i), 2-fold boosted voltage (2V _i), 3-fold boosted voltage (3V _i) It was used by switching as it is depending on the display / non-display state. This method was effective for displaying a 7-segment type liquid crystal display and alphanumeric.
However, in recent years, the demand for liquid crystal displays in the world has increased, and it has become unsatisfactory to display only limited numbers and alphabets. For this reason, today's medium- and small-sized LCD panels have become dot-matrix liquid crystal display types, which include katakana, hiragana, kanji, and special characters.
It is becoming possible to display figures and the like. Since the dot matrix type liquid crystal display has many pixels and a large number of electrodes for driving the liquid crystal, a duty ratio larger than that of the 7 segment type (for example, 1/26, 1 / 32, 1/64, etc.), and the voltage between electrodes (common-segment voltage) at the time of selection is also increased. In the case of a dot matrix type liquid crystal display, the voltage level when not selected is subtly changed in order to obtain clear contrast. For example, as an example, when the TN type liquid crystal display has a 1/32 duty, the non-selection level is V5 / 7, 6V5 / 7 at the common terminal.
Then, the segment terminal becomes 2V5 / 7, 5V5 / 7.

Therefore, the liquid crystal display driver I has been conventionally used.
C is provided with a power supply input terminal at the time of selection / non-selection, generates a booster circuit using a switching regulator and an inductance outside the driver, and generates the boosted output as a voltage divided by a resistor, or divides the resistance. In order to improve the drivability of the applied voltage, a voltage follower reinforced one was input. In recent years, many liquid crystal display driver ICs have a built-in voltage dividing resistor, voltage follower, charge pump type double booster circuit / triple booster circuit constant voltage circuit, etc. in order to improve cost performance. It is like this.

However, when all of the above elements are incorporated in a liquid crystal display driver IC, it is not always optimal to use a double booster / three booster circuit as a booster circuit for the liquid crystal driver. The charge pump type double boosting / triple boosting circuit does not require a large L, but instead, the amount of C that stores electric charges is slightly increased. Compared with the one using a switching regulator, the cost is lower, the space factor is less used, and the conversion efficiency is higher.

[0005]

However, this method can boost the voltage up to three times the input voltage. For example, in order to obtain a maximum voltage of 7.5 V that does not reduce the contrast of the liquid crystal display, a voltage of 2.5 V must be input. That is, an input voltage of 2.5 V or less is outside the operating range of the entire system.
As a result, the operating range voltage is narrowed.

[0006]

SUMMARY OF THE INVENTION In order to solve the above-mentioned drawbacks of the prior art, the present invention has at least two charge pump type booster circuits for doubling an input voltage and outputting the boosted voltage. The operation of the entire system is performed by connecting each booster circuit in cascade so that the output voltage of the circuit becomes the input of the booster circuit of the next stage, and generating an output voltage that is 2 ⁿ times the input voltage of the booster circuit of the first stage. A means to widen the voltage range has been realized. For example, when n = 2, the number of externally attached capacitors is the same, and when the input voltage is 2.5V, the output voltage is 7.5V, whereas in the present invention, it is 10V and 4/3. A double higher output voltage can be obtained.

[0007]

With this structure, a higher voltage can be obtained with the same number of parts.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. First, a circuit for one stage that obtains twice the voltage will be described with reference to FIG. When the input control clock CK = 0, the driver PMOS transistor 9 is turned on, and the C ⁺ terminal is V _H.
It is charged to the electric potential. On the other hand, the driver NMOS transistor 10 is off, the transfer gate NMOS transistor 11 is on, and the transfer gate NMOS transistor 12 is on.
Is OFF, the C ^- terminal is charged to the V _I potential. V
_{At the O} terminal, the transfer gate NMOS transistor 12 is OF
Since it is F, the previous output potential is held.

When the input control clock CK = 1, the driver NMOS transistor 10 is turned on and the C ⁺ terminal is V
Charged to _I potential. On the other hand, the driver PMOS transistor 9 is off, the transfer gate NMOS transistor 11 is off, and the transfer gate NMOS transistor 1 is off.
Since 2 is ON, the C ^- terminal is C on the opposite side of the capacitor.
^{When the +} potential becomes the V _I potential, the potential becomes V _I + V _I = 2V _I due to the influence of the charge charged when CK = 0. This potential is output to the V _O terminal via the transfer gate NMOS transistor 12 as 2V _I.

By repeating the states of CK = 0 and 1 in this way, the potential of V _O = 2V _I is output.
Next, FIG. 1 will be described. As described above, assuming that the booster circuits 1, 2, and 3 have the input voltage V _I , the output voltage V _O =
Since leaving the output voltage level of 2V _I, when the input voltage of the booster circuit 1 and -V _i, the output is -2 V _i, since this voltage is input to the booster circuit 2, the output of the booster circuit 2 is 2
× (−2V _i ) = − 4V _i . Thus, the output of the final stage of the present invention comprising a step-up circuit of the n-stage becomes -2 ⁿ V _i.

Although FIG. 1 shows an example of a boosting circuit to the GND side, the negative side, the present invention is
It is needless to say that the boosting circuit on the positive side and the GND reference in which the type of the transfer gate and the connection of the driver MOS transistor are changed as shown in FIGS. 3 and 4 are also effective. In addition, the booster circuits 1, 2, 3, 50, 5
The input clocks of 1 and 52 may be input separately.

FIG. 5 is an example in which the clock input of the n-stage booster circuit is divided. As shown in FIG. 1, when the same clock input is input to the booster circuit of each stage, the output of the booster circuit of the first stage is 3-
During the state, the boosting circuit at the next stage boosts the voltage, so that the boosting efficiency becomes poor. This requires a backup capacitor for storing electric charges in the V _O terminal of each stage, which increases the cost of the entire system. In FIG. 5, a delay circuit and a gate are used so that the booster circuit in the previous stage boosts the voltage in the next stage while boosting the booster circuit in the previous stage. CKn serves as a clock input to the booster circuit of the nth stage. FIG. 6 is a timing chart of the circuit of FIG. With this configuration,
It eliminates the need to install a backup capacitor for each stage.

FIG. 7 shows the waveform of each part when n = 2.
The output V _O of the first stage is input to the input V _I of the second stage to obtain a quadruple voltage. FIG. 8 is a circuit diagram showing another embodiment of the present invention. It can be realized by changing the clock pulse widths of the clock pulses CK1, CK2, and CK3 in the logic circuit shown in FIG. 8 without using the delay circuit shown in FIG. 9 shows CK1,
It is a figure which shows the waveform of CK2, CK3, and _VOUT .

FIG. 10 shows a circuit for dividing the boosted voltage and outputting five voltages. The clock generation circuit 25 inputs the two clocks CK1 and CK2 independently to the booster circuits 26 and 27. The constant voltage circuit 48 outputs a constant voltage even if the power supply voltage of the liquid crystal display driver changes, so that the quadruple output V5 and the divided voltages V1 to V
This is to prevent the output voltage level of No. 4 from changing and the contrast of the liquid crystal display from changing. For example, to obtain V5 = 7.5V, V _i = 7.5 / 4≈
Set to 1.8V. With this setting, V _DD -V _SS
A stable contrast can be obtained as long as the potential difference is less than 1.8V. The constant voltage circuit can be connected as shown in FIG. However, in this case, the output of the constant voltage circuit needs to be 7.5V.

Of course, the final load of the booster circuits 26 and 27 includes the voltage dividing resistors 28 to 36, the voltage followers 39 to 42, and the capacitance between the COM / SEG driver terminal and the liquid crystal electrode.

[0016]

As described above, according to the present invention, the charge pump type booster circuits are connected in cascade, so that the number of external components of the conventional booster circuit is much higher than that of the conventional booster circuit for a low input voltage. It has an effect of obtaining an output voltage.

[Brief description of drawings]

FIG. 1 is a block diagram of the present invention.

FIG. 2 is a circuit diagram illustrating the present invention.

FIG. 3 is a block diagram of another embodiment of the present invention.

FIG. 4 is a circuit diagram of another embodiment of the present invention.

FIG. 5 is a block diagram of another embodiment of the present invention.

FIG. 6 is a timing chart showing the operation of another embodiment of the present invention.

FIG. 7 is a timing chart showing the operation of the present invention.

FIG. 8 is a block diagram of another embodiment of the present invention.

FIG. 9 is a timing chart showing the operation of another embodiment of the present invention.

FIG. 10 is a circuit diagram showing an embodiment of the present invention.

FIG. 11 is a circuit diagram showing another embodiment of the present invention.

FIG. 12 is a block diagram of a conventional booster circuit.

[Explanation of symbols]

1, 2, 3, 26, 27, 50, 51, 52 Booster circuit 7, 8, 56, 57 Level shifter 9, 60 Driver PMOS transistor 10, 61 Driver NMOS transistor 11, 12, 58, 59 Transfer gate NMOS Transistor 25 Clock generation circuit 28-36 Voltage dividing resistor 39-42 Voltage follower 48 Constant voltage circuit 70-73 Delay circuit 80-82 T flip-flop 83-85 D flip-flop with master output

Claims (3)

[Claims] 1. A charge pump type booster circuit that doubles and outputs an input voltage by repeating ON / OFF of an input control clock, and the output voltage of the booster circuit of the previous stage is the booster circuit of the next stage. A charge pump type booster circuit in which each booster circuit is connected in series so as to be an input of. 2. The input control clock of the booster circuit is from a clock generation circuit that outputs at least one clock output and a second clock output obtained by delaying the clock output by a delay circuit from independent output terminals. 2. The charge pump type booster circuit according to claim 1, wherein the clock is an output clock. 3. The input control clock of the booster circuit is composed of a T flip-flop and a D flip-flop with a master output, and is a clock output from a clock generation circuit which outputs from at least two independent output terminals. The charge pump type booster circuit according to claim 1.