JPH0724310B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0724310B2 JPH0724310B2 JP62014716A JP1471687A JPH0724310B2 JP H0724310 B2 JPH0724310 B2 JP H0724310B2 JP 62014716 A JP62014716 A JP 62014716A JP 1471687 A JP1471687 A JP 1471687A JP H0724310 B2 JPH0724310 B2 JP H0724310B2
- Authority
- JP
- Japan
- Prior art keywords
- internal circuit
- voltage
- semiconductor device
- external signal
- ground line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 24
- 230000015556 catabolic process Effects 0.000 claims description 14
- 238000010586 diagram Methods 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、静電破壊を防ぐ保護素子を有した半導体装置
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a protective element that prevents electrostatic breakdown.
従来の技術 近年、半導体装置は、大規模集積化に伴う微細化によ
り、従来以上の静電耐圧を有した半導体装置が要望され
ている。2. Description of the Related Art In recent years, there has been a demand for a semiconductor device having an electrostatic breakdown voltage higher than that of a conventional semiconductor device due to miniaturization accompanying large-scale integration.
以下に従来の静電破壊保護素子を有した半導体装置につ
いて述べる。A semiconductor device having a conventional electrostatic breakdown protection element will be described below.
第３図は、従来の半導体装置の静電破壊保護素子の構成
を示すものである。第３図において、１は外部信号入力
端子、２は保護抵抗、３はMOS型トランジスタ、４は内
部回路ブロック、５は等価的接地線配線抵抗を示してい
る。FIG. 3 shows a structure of a conventional electrostatic breakdown protection element of a semiconductor device. In FIG. 3, 1 is an external signal input terminal, 2 is a protection resistor, 3 is a MOS transistor, 4 is an internal circuit block, and 5 is an equivalent ground line wiring resistance.
以上の様に構成された半導体装置について、以下その動
作について説明する。The operation of the semiconductor device configured as described above will be described below.
まず、MOS型トランジスタ３のドレイン部31の、電圧電
流特性を第４図に示す。ドレイン部31に正の電圧が印加
された場合は、ブレークダウン電圧V1に達するまで電流
は流れない。また、負の電圧が印加された場合は、ドレ
イン・基板間のPN接合のビルトイン電圧V2に達した時点
で電流が流れだす。従って通常の使用においては、外部
信号はビルトイン電圧V2とブレークダウン電圧V1との間
で印加されるので、MOS型トランジスタ３は動作しな
い。しかし、外部信号入力端子１に、急峻な、サージ電
圧が、印加された場合は、前記各電圧V1,V2を越えるた
め、MOS型トランジスタ３に電流が流れ、そのドレイン
部31の電圧がブレークダウン電圧V1もしくはビルトイン
電圧V2近傍に抑えられ、内部回路に過大なサージ電圧が
印加されない。これにより、内部回路のサージ電圧によ
る破壊を防止する事ができる。First, FIG. 4 shows the voltage-current characteristics of the drain section 31 of the MOS transistor 3. When a positive voltage is applied to the drain part 31, no current flows until the breakdown voltage V 1 is reached. When a negative voltage is applied, a current starts flowing when the built-in voltage V 2 of the PN junction between the drain and the substrate is reached. Therefore, in normal use, since the external signal is applied between the built-in voltage V 2 and the breakdown voltage V 1 , the MOS transistor 3 does not operate. However, when a steep surge voltage is applied to the external signal input terminal 1, the voltages V 1 and V 2 are exceeded, so that a current flows through the MOS transistor 3 and the voltage of its drain portion 31 is increased. The breakdown voltage V 1 or the built-in voltage V 2 is suppressed, and excessive surge voltage is not applied to the internal circuit. This makes it possible to prevent the internal circuit from being damaged by the surge voltage.
発明が解決しようとする問題点 しかしながら上記の従来の構成では、外部信号入力端子
１と内部回路４とが半導体装置内で離れている場合に
は、等価的接地線配線抵抗５が無視できない大きさとな
り、過大なサージ電圧が印加されたときにMOS型トラン
ジスタ３に流れる電流ｉと、等価的接地線配線抵抗５の
抵抗値Ｒとの積で表わされる電位分だけ、MOS型トラン
ジスタ３のソース部32が変動し、サージ電圧をMOSトラ
ンジスタ３で十分抑制できないという欠点を有してい
た。その様子を第５図に示す。（ａ）は、外部信号入力
端子に印加されたサージ電圧波形であり、（ｂ）は、第
３図中のMOS型トランジスタ３のドレイン部31における
電圧波形である。通常、等価的接地線配線抵抗５が無視
できる程小さい場合は、図中点線で示されるように、印
加されたサージ電圧は、ブレークダウン電圧V1ならびに
ビルトイン電圧V2の間に、十分抑制される。しかし、接
地線配線抵抗が大きくなってくると、MOS型トランジス
タ３のソース部32の電位が、正のサージ電圧の場合は、
正の方向に、負のサージ電圧印加の場合は、負の方向
に、それぞれ、図中V3で示される分だけ変動し、したが
って、内部回路４に印加される電圧が増大する。これ
が、半導体装置のサージ耐圧を低下させる要因となるの
である。Problems to be Solved by the Invention However, in the above-described conventional configuration, when the external signal input terminal 1 and the internal circuit 4 are separated in the semiconductor device, the equivalent ground line wiring resistance 5 has a size that cannot be ignored. Therefore, the source portion of the MOS transistor 3 is as much as the potential represented by the product of the current i flowing through the MOS transistor 3 when an excessive surge voltage is applied and the resistance value R of the equivalent ground line wiring resistor 5. 32 fluctuates, and the surge voltage cannot be sufficiently suppressed by the MOS transistor 3. This is shown in FIG. (A) is a surge voltage waveform applied to the external signal input terminal, and (b) is a voltage waveform in the drain section 31 of the MOS transistor 3 in FIG. Normally, when the equivalent ground line wiring resistance 5 is negligible, the applied surge voltage is sufficiently suppressed between the breakdown voltage V 1 and the built-in voltage V 2 as shown by the dotted line in the figure. It However, when the ground line wiring resistance increases, if the potential of the source portion 32 of the MOS transistor 3 is a positive surge voltage,
When a negative surge voltage is applied in the positive direction, the negative surge voltage varies in the negative direction by the amount indicated by V 3 in the figure, and therefore the voltage applied to the internal circuit 4 increases. This is a factor that lowers the surge withstand voltage of the semiconductor device.
本発明は、上記従来の問題点を解決するもので、集積度
増大によるチップ寸法の増加によって、接地線配線抵抗
が増大しても、安全に静電破壊から保護する半導体装置
を提供することを目的とする。The present invention solves the above conventional problems, and provides a semiconductor device that safely protects from electrostatic breakdown even if the ground line wiring resistance increases due to an increase in chip size due to an increase in the degree of integration. To aim.
問題点を解決するための手段 この目的を達成するために、本発明の半導体装置は、外
部信号印加端子の近傍と、この外部信号が入力される内
部回路近傍との、複数箇所に静電破壊保護素子を有し、
これらのうち、内部回路近傍の静電破壊保護素子は、こ
の内部回路に対し、接地線配線抵抗を無視できる近接箇
所に設けた構成である。Means for Solving the Problems In order to achieve this object, the semiconductor device of the present invention has an electrostatic breakdown in a plurality of locations, in the vicinity of an external signal applying terminal and in the vicinity of an internal circuit to which the external signal is input. Has a protective element,
Of these, the electrostatic breakdown protection element near the internal circuit is provided in a location near the internal circuit where the ground line wiring resistance can be ignored.
作用 この構成によって、接地線電位の変動による、サージ耐
圧の低下を避けることが可能となり、サージから、半導
体装置を有効に保護することができる。Operation With this configuration, it is possible to avoid a decrease in surge withstand voltage due to fluctuations in the ground line potential, and it is possible to effectively protect the semiconductor device from a surge.
実施例 以下本発明の実施例について、図面を参照しながら説明
する。Embodiments Embodiments of the present invention will be described below with reference to the drawings.
第１図は、本発明の第１の実施例における半導体装置の
回路図を示したものである。第１図において、１は外部
信号入力端子、２は保護抵抗、３は外部信号入力端子近
傍のMOS型トランジスタ、４は半導体内部回路ブロッ
ク、５は等価的接地線配線抵抗、６は半導体内部回路の
接地線に近接して接続されたMOS型トランジスタであ
る。FIG. 1 is a circuit diagram of a semiconductor device according to the first embodiment of the present invention. In FIG. 1, 1 is an external signal input terminal, 2 is a protection resistor, 3 is a MOS transistor near the external signal input terminal, 4 is a semiconductor internal circuit block, 5 is an equivalent ground line wiring resistor, and 6 is a semiconductor internal circuit. Is a MOS-type transistor that is connected close to the ground line.
以上のように構成された半導体装置について、以下その
動作を説明する。The operation of the semiconductor device configured as described above will be described below.
外部信号印加端子１にサージ電圧が印加され、このと
き、等価的接地線配線抵抗５によって、外部信号入力端
子近傍のMOS型トランジスタ３のドレイン部32が変動
し、MOS型トランジスタ３で、充分に抑制されないま
ま、高電圧が内部回路４に印加されても、MOS型トラン
ジスタ６のドレイン部42の電圧は、同MOS型トランジス
タ６によって抑制されるために、内部回路４は、サージ
破壊から保護される。さらに、MOS型トランジスタ６の
ソース部41が変動しやすい状態であっても、MOSトラン
ジスタ６の接地線は、内部回路４の接地線と、同じよう
に変動するため、内部回路４は、サージ電圧から保護さ
れる。A surge voltage is applied to the external signal applying terminal 1, and at this time, the drain portion 32 of the MOS type transistor 3 near the external signal input terminal is changed by the equivalent ground line wiring resistance 5, and the MOS type transistor 3 is sufficiently operated. Even if a high voltage is applied to the internal circuit 4 without being suppressed, the voltage of the drain portion 42 of the MOS transistor 6 is suppressed by the MOS transistor 6, so the internal circuit 4 is protected from surge damage. It Further, even if the source section 41 of the MOS transistor 6 is easily changed, the ground line of the MOS transistor 6 changes in the same manner as the ground line of the internal circuit 4, so that the internal circuit 4 is not affected by the surge voltage. Protected from.
以上のように本実施例によれば、入力信号が印加される
内部回路に、接地線を共有したMOS型トランジスタを設
けたことにより、接地線配線抵抗が増大した場合でも、
有効にサージ電圧から内部回路を保護できる。As described above, according to the present embodiment, even when the ground line wiring resistance is increased by providing the MOS type transistor sharing the ground line in the internal circuit to which the input signal is applied,
It can effectively protect the internal circuit from surge voltage.
以下本発明の第２の実施例について図面を参照しながら
説明する。A second embodiment of the present invention will be described below with reference to the drawings.
第２図は、本発明を半導体記憶装置において実施した例
である。同図において、各符号1,2,3,4,5,6は第１図の
構成要素と対応するものであり、加えて７は、外部接地
端子,8は記憶部を示す。FIG. 2 shows an example in which the present invention is implemented in a semiconductor memory device. In the figure, reference numerals 1, 2, 3, 4, 5 and 6 correspond to the constituent elements of FIG. 1, in addition, 7 is an external ground terminal and 8 is a storage section.
上記のように構成された半導体装置について、以下に説
明する。The semiconductor device configured as described above will be described below.
第２図に示すように、半導体記憶装置では中心部の大部
分が記憶部８から成る。そのため、接地線は周辺部に沿
い長い距離にわたり配線される。外部接地端子７は、内
部回路ブロック４の近傍に設け、さらに、これに近接し
て、MOS型トランジスタ６を配し、外部信号入力端子１
に誘起されたサージ電圧が、MOS型トランジスタ３によ
り、充分に抑制されないまま内部回路ブロック４に印加
されるのをMOS型トランジスタ６によって防止してい
る。ここで、MOS型トランジスタ６は、電圧保護として
用いられるため、電流容量は大きくとる必要がない。従
って内部回路ブロック４内に配することもできる。As shown in FIG. 2, most of the central portion of the semiconductor memory device is composed of the memory unit 8. Therefore, the ground wire is laid along the periphery for a long distance. The external ground terminal 7 is provided in the vicinity of the internal circuit block 4, and the MOS type transistor 6 is arranged in the vicinity of the external ground terminal 7, and the external signal input terminal 1 is provided.
The MOS type transistor 6 prevents the surge voltage induced in the internal circuit block 4 from being applied to the internal circuit block 4 without being sufficiently suppressed by the MOS type transistor 3. Here, since the MOS transistor 6 is used for voltage protection, it is not necessary to have a large current capacity. Therefore, it can be arranged in the internal circuit block 4.
なお、第1,第２の実施例において、保護素子としてMOS
型トランジスタ3,6の２つを示したが、その間にさらに
複数の保護素子を入れてもよい。さらにこの保護素子
は、MOS型トランジスタでなくても、同等の機能をもつ
回路素子で良い。In addition, in the first and second embodiments, a MOS is used as a protection element.
Although two type transistors 3 and 6 are shown, a plurality of protective elements may be further inserted between them. Further, this protection element may be a circuit element having an equivalent function, instead of the MOS type transistor.
発明の効果 以上のように、本発明は、静電破壊保護素子を外部信号
印加端子の近傍と、半導体装置内部回路近傍で接地線配
線抵抗が無視しうる近い箇所との複数箇所に設けること
により、接地電位が配線抵抗のために変動しても、極め
て安定に静電破壊よりの保護が可能となる。また、内部
回路近傍の保護素子は、電圧保護を目的とするため、寸
法は、通常の内部回路と同程度で良いため、回路ブロッ
ク内に配置することが可能であり、本発明を用いること
による寸法の増加は皆無である。従って本発明は極めて
広い適用範囲を持ち、その実用的効果は大なるものがあ
る。EFFECTS OF THE INVENTION As described above, according to the present invention, by providing the electrostatic breakdown protection element at a plurality of positions in the vicinity of the external signal applying terminal and in the vicinity of the internal circuit of the semiconductor device where the ground line wiring resistance can be ignored. Even if the ground potential changes due to the wiring resistance, it is possible to extremely stably protect from electrostatic breakdown. Further, since the protection element near the internal circuit is intended for voltage protection, the dimensions may be about the same as a normal internal circuit, so that it can be arranged in the circuit block, and by using the present invention. There is no increase in size. Therefore, the present invention has an extremely wide range of application and its practical effects are great.
【図面の簡単な説明】 第１図は本発明の第１の実施例半導体装置の回路図、第
２図は本発明の第２の実施例半導体記憶装置のブロック
図、第３図は従来の半導体装置の回路図、第４図はゲー
ト部をソース部に接続したMOS型トランジスタのドレイ
ン電圧電流特性図、第５図はサージ電圧印加時の各部波
形図である。 １……外部信号印加端子、２……保護抵抗、３……MOS
型トランジスタ、４……内部回路、５……接地線配線抵
抗、６……MOS型トランジスタ、７……外部接地端子、
８……記憶部。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a block diagram of a semiconductor memory device according to a second embodiment of the present invention, and FIG. FIG. 4 is a circuit diagram of a semiconductor device, FIG. 4 is a drain voltage-current characteristic diagram of a MOS transistor in which a gate portion is connected to a source portion, and FIG. 5 is a waveform chart of each portion when a surge voltage is applied. 1 ... External signal application terminal, 2 ... Protection resistance, 3 ... MOS
Type transistor, 4 ... Internal circuit, 5 ... Ground wire wiring resistance, 6 ... MOS transistor, 7 ... External ground terminal,
8: Memory section.
Claims (1)
が入力される内部回路近傍との、複数箇所に静電破壊保
護素子を有し、かつ、前記内部回路近傍の静電破壊保護
素子は、この内部回路に対し、接地線配線抵抗を無視で
きる近接箇所に設けたことを特徴とする半導体装置。1. An electrostatic breakdown protection device having electrostatic discharge protection elements at a plurality of locations, in the vicinity of an external signal application terminal and in the vicinity of an internal circuit to which the external signal is input, and at the vicinity of the internal circuit. Is a semiconductor device characterized in that it is provided at a location close to the internal circuit where the ground line wiring resistance can be ignored.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62014716A JPH0724310B2 (en) | 1987-01-23 | 1987-01-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62014716A JPH0724310B2 (en) | 1987-01-23 | 1987-01-23 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63181469A JPS63181469A (en) | 1988-07-26 |
| JPH0724310B2 true JPH0724310B2 (en) | 1995-03-15 |
Family
ID=11868868
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62014716A Expired - Lifetime JPH0724310B2 (en) | 1987-01-23 | 1987-01-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0724310B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008227369A (en) * | 2007-03-15 | 2008-09-25 | Asahi Kasei Electronics Co Ltd | Electrostatic breakage protection circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59181044A (en) * | 1983-03-31 | 1984-10-15 | Toshiba Corp | Input protecting circuit |
| JPS6010767A (en) * | 1983-06-30 | 1985-01-19 | Fujitsu Ltd | Semiconductor device |
| JPS60115253A (en) * | 1983-11-28 | 1985-06-21 | Nec Corp | Semiconductor integrated circuit device |
| JPS61264749A (en) * | 1985-05-13 | 1986-11-22 | エツセ・ジ・エツセ・ミクロエレツトロニ−カ・エツセ・ピ・ア | Dynamic protective integrator |
-
1987
- 1987-01-23 JP JP62014716A patent/JPH0724310B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59181044A (en) * | 1983-03-31 | 1984-10-15 | Toshiba Corp | Input protecting circuit |
| JPS6010767A (en) * | 1983-06-30 | 1985-01-19 | Fujitsu Ltd | Semiconductor device |
| JPS60115253A (en) * | 1983-11-28 | 1985-06-21 | Nec Corp | Semiconductor integrated circuit device |
| JPS61264749A (en) * | 1985-05-13 | 1986-11-22 | エツセ・ジ・エツセ・ミクロエレツトロニ−カ・エツセ・ピ・ア | Dynamic protective integrator |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63181469A (en) | 1988-07-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |