JPH07234773A - Display controller - Google Patents

Abstract

PURPOSE:To display VGA data on the high resolution screen of an XGA specification at an optional position and in an optional size without rewriting VRAM. CONSTITUTION:The screen CRTC 161 generates a synchronizing signal, etc., for controlling the screen area 100 of a picture element 1024X768 in accordance with a screen parameter, and a window CRTC 162 controls the display of a window area 200 in accordance with a window parameter. When the screen CRTC 161 detects the display starting position of the window area 200, the window CRTC 162 starts the display control of the window area 200 so that VGA data is successively read out from the start address of VRAM 30 and converted to video data. The piece of video data is supplied to a display monitor in the display period of the window area so as to display video data in the window area 100.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device,
In particular, the present invention relates to a display control device that controls a display monitor used in a computer system such as a personal computer.

[0002]

2. Description of the Related Art Generally, a flat panel display such as a liquid crystal display or a plasma display, or a CRT display is used as a display monitor of a computer system such as a personal computer. Currently, these displays are controlled by VG
This is performed using a display controller called A (Video Graphics Array).

For this reason, many application programs started on a computer system also have this VG.
It is created to meet the specifications of A. The VGA display controller is provided with a mode such as 640 × 480 pixels and maximum simultaneous display of 256 colors.

However, in recent computer systems, DTP (DeskTop Publics) is used.
Hing) is required for advanced operation using a high-saturation screen, and the resolution and the number of display colors provided by VGA have become unsuitable for such operation.

Therefore, recent computer systems have an XGA (Extended Graphics) having a display mode capable of realizing a higher resolution display than VGA.
Array) display controllers have begun to be used. In this XGA specification display controller,
Since a high resolution mode such as 1024 × 768 pixels is prepared, many windows can be displayed on the same screen. Therefore, the display controller of this XGA specification is
It is possible to sufficiently provide the performance required for a graphical user interface that makes heavy use of window display including the operation of DTP.

By the way, in these display controllers,
To support different resolutions of XGA and VGA,
Using a multi-sync type CRT display 1
Switching between high-resolution display of 024 × 768 pixels and medium-resolution display of 640 × 480 pixels is performed. In this case, both high resolution data and medium resolution data are CR
By the synchronization processing in the T display, the entire display screen is displayed in the full screen mode.

However, for example, XGA specifications or S
When screens with different resolutions are frequently switched, such as when the VGA specification application program and the VGA specification application program are simultaneously executed and the screen data thereof are alternately switched and displayed, the CRT display is used. May cause a problem such as flickering on the display screen each time the switching is performed.

Displaying medium-resolution data while the CRT display is in the high-resolution mode can solve the problem of flicker associated with such synchronization. However, in this case, the medium resolution data is displayed in the corner of the screen, which causes a problem that the visual recognition of the data is deteriorated. This problem is 1024 × 7
The same occurs when displaying medium resolution data of 640 × 480 pixels on a flat panel display having a high resolution screen of 68 pixels, and the display position of the medium resolution data is fixed to a specific position within the high resolution screen. , Its display position cannot be changed by user's designation.

[0009]

Conventionally, when displaying data of lower resolution in a lower resolution than that on a high-resolution screen, the display position of the data is fixed at a specific position, and the display is performed. There was a drawback that the position could not be changed.

The present invention has been made in view of the above circumstances, and provides a display control device capable of displaying medium and low resolution data on a high resolution screen as a window having an arbitrary position and an arbitrary size. The purpose is to provide.

[0011]

Means and Actions for Solving the Problems
In a display control device for controlling a display monitor of a computer system, an image memory in which display data created by an application program executed by the computer system is stored from a predetermined storage start position, and various parameters instructed by the system. A rewritable parameter register group to which a value is set, a screen parameter that specifies the size of the entire display screen area that can be displayed on the display monitor, and a display start of a window area to be displayed in the entire display screen area. Parameter registers that set window parameters that specify the position and size,
A first display control circuit for controlling the entire display screen area in accordance with the screen parameter, wherein horizontal and vertical synchronization signals of the display monitor according to scanning timing for displaying the entire display screen area on the display monitor. For generating a coordinate address indicating a scanning position on the entire display screen according to the scanning timing, a window area display start position designated by the window parameter, and a value of the coordinate address. A first display control circuit including: means for generating a window area detection signal indicating that the scanning position on the entire display screen has reached the display start position of the window area based on the comparison result. Second display control circuit for controlling the window area according to the window parameter And a means for generating a display enable signal indicating a display period corresponding to the window area in response to the window area detection signal, and a means for responding to the window area detection signal from the storage start position of the image memory. A second display control circuit including means for generating a memory address for reading display data;
Means for reading the display data from a storage start position of the image memory according to a memory address generated from the second display control circuit and converting the display data into video data to be supplied to the display monitor;
A means for supplying the video data to the display monitor during a display period designated by the display enable signal so that the display data created by the application program is displayed in the window area. To do.

This display control device is provided with two display control circuits, a first display control circuit and a second display control circuit. The first display control circuit generates a synchronization signal for controlling the entire display screen area in accordance with screen parameters. The second display control circuit controls the display of the window area according to the window parameter. When the first display control circuit detects the window area, the second display control circuit starts the display control of the window area, whereby the display data is sequentially read from the storage start position of the image memory to obtain the video data. Is converted to. This video data is supplied to the display monitor during the display period of the window area defined by the display enable signal, whereby the video data is displayed in the window area.

In this case, the position and size of the window area can be changed programmatically by the value of the window parameter set in the parameter register group.
Therefore, it becomes possible to display the medium and low resolution data created by the application program on the high resolution display screen at any position and at any size.

Further, in this display control device, the data to be displayed in the window area is read from the data storage start position in the image memory by the application program. Therefore, the window display can be performed in a state where the existing application program is used as it is without changing the data storage position of the image memory.

Further, the display control device of the present invention has a mode in which the window parameter is used instead of the screen parameter. As a result, the parameter value used by the first display control circuit becomes the same as the window parameter value used by the second display control circuit, and the horizontal / vertical synchronizing signal corresponding to the size of the window area is generated. In this case, when the CRT display is used, the medium and low resolution data created by the application program is displayed in the full screen mode on the entire display screen of the CRT display.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the overall configuration of a display control system according to an embodiment of the present invention. This display control system 4 is, for example, 1024 × 768 dots, 256
XGA (eXtended) with display modes such as simultaneous color display
It is a display control system of the Graphics Array) specification and is connected to the CPU local bus 3 of the portable computer. The display control system 4 performs display control on both a flat panel display 40 that is standardly equipped in the portable computer main body and a color CRT display 50 that is detachably connected to the portable computer main body.

The display control system 4 includes a display controller 10 and a dual port image memory (V
RAM) 30 is provided. These display controller 10, dual port image memory (VRA
M) 30 is mounted on a circuit board (not shown).

The display controller 10 is an LSI realized by a gate array and is a main part of the display control system 4. The display controller 10 executes display control for the flat panel display 40 and the color CRT display 50 using a dual port image memory (VRAM) 30 according to an instruction from the host CPU 1. Further, the display controller 10 functions as a bus master and can directly access the system memory 2 of the computer.

Dual port image memory (VRAM) 3
0 has a serial port (serial DATA) used for serial access and a parallel port (DATA) for random access. The serial port (serial DATA) is used to read data for refreshing the display screen, and the parallel port (DA).
TA) is used to update image data. The dual-port image memory (VRAM) 30 is composed of a plurality of dual-port DRAMs and has 1 Mbyte to 4 Mbytes.
It has a storage capacity of M bytes. The dual port image memory (VRAM) 30 is used as a frame buffer, and image data to be displayed on the flat panel display 40 or the color CRT display 50 is drawn.

In this case, the XGA specification drawing data created by an application program or the like conforming to the XGA specification is stored from the top address of the dual port image memory (VRAM) 30 by the packed pixel method. This packed pixel system is a color information mapping format in which one pixel is represented by a plurality of consecutive bits on a memory, and for example, a system in which one pixel is represented by 1, 2, 4, 8 or 16 bits is adopted. . On the other hand, the VGA specification drawing data is created by an application program or the like conforming to the VGA specification, and the dual port image memory (VRAM) 3 by the memory plane method.
It is drawn from the start address of 0. This memory plane method is a method in which a memory area is divided into a plurality of planes designated by the same address and color information of each pixel is assigned to these planes. For example, if there are four planes, one pixel is a total of four bits, one bit for each plane.
It is represented by bit data.

A dual port image memory (VRA
Text data is also stored in M) 30. The text data for one character has a total size of 2 bytes including an 8-bit code and an 8-bit attribute in both the XGA and VGA specifications. The attribute is composed of 4-bit data that specifies the foreground color and 4-bit data that specifies the background color.

The display controller 10 includes a register control circuit 11 and a system bus interface 1.
2, a drawing coprocessor 13, a memory control circuit 14,
CRT controller (CRTC) 16, serial port control circuit 18, sprite memory 19, serializer 2
0, latch circuit 21, foreground / background multiplexer 22, graphic / text multiplexer 23, color palette control circuit 24, sprite color register 25, CRT video multiplexer 2
6, sprite control circuit 27, flat panel emulation circuit 28, and DAC (D / A converter)
It is composed of 35.

The register control circuit 11 receives an address and data from the system bus 3 via the system bus interface 12, decodes the address, and performs read / write control on various registers designated by the decoding result. The system bus interface 12 controls the interface with the host CPU 1 via the local bus 3, and supports not only the local bus but also a bus interface suitable for system buses of various specifications such as ISA, EISA, and Micro Channel. To do.

The drawing coprocessor 13 is a graphic accelerator, and in response to an instruction from the CPU 1,
It provides various drawing functions for drawing data in the dual port image memory (VRAM) 30. The drawing coprocessor 13 transfers a block of pixels such as BITBIL, draws a line, fills an area, and performs logic between pixels.
It has arithmetic operations, screen cutout, map mask, XY coordinate addressing, memory management function by paging, and the like. In this drawing coprocessor 13,
VGA / XGA compatible data operation circuit 131, two-dimensional address generation circuit 131, and paging unit 13
3 is provided.

The data operation circuit 131 performs data operations such as shift, logical arithmetic operation, bit mask, and color comparison, and also has a VGA compatible BITBLT function. The two-dimensional address generation circuit 131 generates an XY two-dimensional address for accessing a rectangular area or the like. The two-dimensional address generation circuit 131 also performs a region check and a conversion process to a linear address (real memory address) using segmentation or the like. The paging unit 133 is for supporting the same virtual memory mechanism as the CPU 1, and converts the linear address created by the two-dimensional address generation circuit 131 into a real address by paging when paging is valid. Further, when paging is invalid, the linear address becomes the real address as it is. The paging unit 133 has a TLB for paging.

The memory control circuit 14 is for controlling access to the dual port image memory (VRAM) 30, and is a dual port image memory (VRAM) according to a read / write request of image data from the CPU 1 or the drawing coprocessor 13. The access control of 30 parallel ports is performed, and the dual port image memory (VRA) is controlled according to the display position address from the CRTC 16.
M) Control of reading data from the serial port 30.

Further, the memory control circuit 14 has a frame buffer cache 141 built therein. The frame buffer cache 141 is used to speed up read / write of image data by the CPU 1 and the drawing coprocessor 13, and holds a part of the image data of the dual port image memory (VRAM) 30. To do. When the image data requested to be read by the CPU 1 or the drawing coprocessor 13 exists in the frame buffer cache 141, the image data is read from the frame buffer cache 141 and the CPU
1 or to the drawing coprocessor 13. In this case, read access via the parallel port of the dual port image memory (VRAM) 30 is not performed.

The CRT controller (CRTC) 16 is
Various display timing signals (horizontal synchronizing signal, vertical synchronizing signal, etc.) for controlling the flat panel display 40 or the CRT display 50, and a serial port (serial D) of the dual port image memory (VRAM) 30.
A display address for reading the image data to be displayed on the screen from the ATA) is generated. This CRT controller 1
6 has a screen CRTC 161 and a window CRT.
C162 is provided. Screen CRTC161
Is for controlling the entire display screen area (hereinafter referred to as a screen) that can be displayed on the display monitor of the flat panel display 40 or the CRT display 50, and the window CRTC 162 is an arbitrary screen defined within the screen. It controls a display area (hereinafter referred to as a window) of position and size. This CRT
The configuration of the controller 16 is a feature of the present invention, and details thereof will be described later with reference to FIG.

Serial port control circuit 18, sprite memory 19, serializer 20, latch circuit 21, foreground / background multiplexer 22, graphic / text multiplexer 23, color palette control circuit 24, sprite color register 25, CR
T video multiplexer 26, sprite control circuit 2
The flat panel emulation circuit 28 and the DAC (D / A converter) 35 constitute a display control circuit 300 for displaying the image data of the dual port image memory (VRAM) 30 on the flat panel display 40 or the CRT display 50. To do.

The serial port control circuit 18 generates a serial clock SCK and an output enable signal SOE for controlling the data read timing from the serial data port of the dual port image memory (VRAM) 30. The memory control circuit 18 also controls access to the sprite memory 19 and sprite display timing control.

In the sprite memory 19, sprite data is written in the graphic mode, and fonts are written in the text mode. In the text mode, the code of the text data read from the dual port image memory (VRAM) 30 is supplied to the sprite memory 19 as an index, and the font corresponding to the code is read.

The serializer 20 is a parallel / serial conversion circuit for dividing parallel pixel data for a plurality of pixels into pixel units (serial) and outputting the same. In the graphic mode, the serializer 20 serializes the dual port image memory (VRAM) 30. The memory data read from the port and the sprite data read from the sprite memory 19 are respectively parallel / serial converted,
In the text mode, the font data read from the sprite memory 19 is parallel / serial converted.

The latch circuit 21 is for delaying the attribute output timing by the delay time of conversion from code data to font data, and is a dual port image memory (VRAM) in the text mode.
The attribute of the text data read from 30 is held. The foreground / background multiplexer 22 selects one of the foreground color (front color) and the background color (background color) of the attribute in the text mode. This choice is for serializer 2
The font data values output from 0 are controlled by "1" (foreground) and "0" (background). The graphic / text multiplexer 23 is for switching between the graphic mode and the text mode. In the graphic mode, the memory data output from the serializer 20 is selected, and in the text mode, the foreground / background multiplexer 22 is selected. Select an output.

The color palette control circuit 24 is for performing color conversion of graphic or text data. The color palette control circuit 24 includes a two-stage color palette table. The first color palette table is composed of 16 color palette registers. Each color palette register contains
6-bit color palette data is stored. The second color palette table is composed of 256 color palette registers. Each color palette register stores 18-bit color data composed of 6 bits for each of R, G, and B.

In the graphic mode, 8-bit / pixel XGA specification memory data is sent directly to the second color palette table without passing through the first color palette table, where R, G and B are each 6 Converted to color data composed of bits. Also,
The 4-bit / pixel VGA memory data is first sent to the first color palette table, where it is converted into 6-bit color data and output. And
To this 6-bit color data, 2-bit data output from the color selection register built in the color palette control circuit 19 is added, whereby a total of 8-bit color data is obtained. After that, the 8-bit color data is sent to the second color palette table, where it is converted into color data of 6 bits for each of R, G, and B.

On the other hand, in the text mode, XG
Text data of both A and VGA can be read via R, R, and R via the first and second two-stage color palette tables.
It is converted into color data composed of 6 bits for each of G and B.

In the XGA graphics mode, there is a direct color mode in which one pixel is composed of 16 bits. In this case, the memory data of 16 bits / pixel does not go through the color palette control circuit 24. Are directly supplied to the CRT video multiplexer 26.

The sprite color register 25 stores sprite display data designating a sprite display color such as a hardware cursor. The CRT video multiplexer 26 selects the CRT video display output, and selects the output of the color palette control circuit 24, the direct color output from the serializer 20, the sprite display data, or the external video data. This selection operation is controlled by the display timing signal from the CRTC 16. The external video data is, for example, video data such as a moving image input from outside the display control system 4. The sprite control circuit 27 outputs the sprite display data of the sprite color register 25 according to the sprite data that is parallel / serial converted by the serializer 20.

Flat panel emulation circuit 28
Converts the CRT video output to produce flat video data for flat panel display 40. DA
The C 35 converts the CRT video data output from the CRT video multiplexer 26 into analog R, G, B signals and supplies the analog R, G, B signals to the CRT display 50.

Next, referring to FIG. 2, a screen CRT
The principle of display control using the C161 and the window CRTC 162 will be described. The screen area 100 is the entire display screen (1024 × 768 pixels) that can be displayed on a display monitor compatible with high resolution of XGA specifications, which is the entire panel of the flat panel display 40 or the CRT.
It corresponds to the display area of the display 50 in the high resolution mode. The window area 200 is an application display area, and has a size of 640 × 480 pixels corresponding to an application program of VGA specifications, for example. The display start position of this window area 200 is coordinate (X
w, Yw).

In this case, the screen area 100 is controlled by the screen CRTC 161 and the window area 200 is controlled by the window CRTC 162.

That is, the screen CRTC 161 is
1024 × 7 specified by screen parameters
A horizontal / vertical synchronizing signal for controlling a 68-pixel screen is generated, and a window display start position coordinate (Xw, Y) designated by a coordinate address indicating a scan position on the screen area 100 and a window parameter is generated.
w), and when they match, a window detection signal is generated. The window CRTC 162 starts its operation in response to the window detection signal and controls the display of the window area 200 according to the window parameter.

In this case, the window CRTC 162 is
The window size specified by the window parameter is controlled as the entire screen, and a display address for reading VGA data from the first line of the VRAM 30 drawn by the application program is generated. The value of this display line is updated by +1 for each line scanning unit of 640 dots.

Therefore, by changing the window display start position coordinates and the window size designated by the window parameter, the screen area 1
00, a window area 200 having an arbitrary position and an arbitrary size can be allocated, and VGA data created by an application program can be displayed in the window area 200. Also, the window area 2
Border colors and the like are displayed in areas other than 00.

Next, a specific structure of the CRTC 16 will be described with reference to FIG. As shown, CRTC16
Is a parameter register group 101, a screen counter group 102, a screen comparator 103, a parameter multiplexer 104, a window counter group 105,
Window comparator 106, timing control circuit 1
07, and a display address generation circuit 108.

Here, the screen counter group 102 and the screen comparator 103 are the screen CRTC.
161 and includes a window counter group 105, a window comparator 106, and a display address generation circuit 1
08 belongs to the window CRTC 162. Further, the parameter register group 101, the parameter multiplexer 104, and the timing control circuit 107 are shared by the screen CRTC 161 and the window CRTC 162.

The parameter register group 101 is a group of readable / writable registers connected to the data bus defined in the local bus 3. Here, there are screen parameters for CRT, screen parameters for flat panel, And the window parameters for the CRT / flat panel are set. FIG. 4 shows an example of types of registers provided in the parameter register group 101.

The screen parameter for the CRT is a parameter for defining the display screen size of the CRT in the high resolution mode, and this parameter is CR.
T screen parameter register group such as horizontal / vertical total register, horizontal / vertical display end register, horizontal / vertical blanking register, horizontal / vertical sync register, horizontal sync skew register for specifying the total number of horizontal characters / vertical lines Is set to.

The screen parameters for the flat panel are parameters for defining the display screen size of the entire panel and the like. These parameters are flat panel screen horizontal / vertical total register, horizontal / vertical display end register, horizontal / vertical. It is set in a parameter register such as a blanking register, a horizontal / vertical sync register, and a horizontal sync skew register.

The window parameter is for defining the size of the window area in both the CRT and the flat panel, and this parameter is the window horizontal / vertical total register, horizontal / vertical display end register, horizontal / vertical blanking. register,
It is set in the horizontal / vertical sync register and the horizontal sync skew register.

Further, the parameter register group 101 is provided with a window display start position coordinate register, an external video display start position coordinate register, a window size register indicating horizontal / vertical total of the external video window, and a display control register. . The display control register includes various mode registers such as a register for switching the display of the CRT / flat panel and a register for specifying the full screen mode.

Here, horizontal / vertical total, horizontal / vertical display end, horizontal / vertical blanking, horizontal / vertical
For the meaning of vertical sync and horizontal sync skew, see C
Since it is a well-known RT control parameter, its detailed description is omitted here.

In FIG. 3, the screen counter group 10
Reference numeral 2 indicates a scan position in the screen area 100, which includes a pixel counter 102a, a horizontal counter 102b, a vertical counter 102c, and a frame counter 102d. Pixel counter 102a
Is for counting the pixel positions in one character according to the pixel clock CKP, and the count-up operation is performed in pixel units. The horizontal counter 102b is
The number of characters in the horizontal direction is counted according to the pixel clock CKP, and the count-up operation is performed in pixel units. The vertical counter 102c counts the number of lines in the vertical direction according to the vertical clock CKV, and counts up in units of lines. The vertical clock CKV is generated every time the pixel clock CKP for one line is generated. The frame counter 102d performs a count-up operation for each screen in accordance with the vertical clock CKV. Frame counter 10
The 2d output (FRCNT) is used for blinking control, dither control for each frame, and the like.

The screen comparator 103 compares the CRT screen parameter or the flat panel screen parameter value of the parameter register group 101 with the value of the screen counter group 102 to make a screen area 1.
The scanning position within 00 is detected, and the scanning position detection signal is supplied to the timing control circuit 107. Further, the screen comparator 103 compares the window display start position coordinates and the external video display start position coordinates of the parameter register group 101 with the values of the screen counter group 102 to detect the window display start position and the external video display start position. I do. When the scanning position on the screen coincides with the window display start position, the screen comparator 103 generates a window area detection signal.

The parameter multiplexer 104 selects a parameter value to be supplied to the screen comparator 103 according to the display mode. For example, when displaying on the flat panel display 40, the flat panel screen parameter is selected and the CRT display 5
When displaying 0, window parameters are used for full screen display, and CRT is used for displaying VGA data in high resolution mode without full screen display.
Screen parameters are selected. On the other hand, the window parameter is always supplied to the window comparator 106.

The window counter group 105 is for indicating the scan position in the window area 200, and includes the pixel counter 105a and the horizontal counter 105.
b, a vertical counter 105c. The pixel counter 105a counts the pixel position in one character in the window area 200 according to the pixel clock CKP, and counts up in pixel units. The horizontal counter 105b counts the number of characters in the horizontal direction in the window area 200 according to the pixel clock CKP, and counts up in units of pixels. The vertical counter 105c counts the number of lines in the vertical direction in the window area 200 according to the vertical clock CKV, and counts up in units of lines.

The window comparator 106 detects the scanning position in the window area 200 by comparing the window parameter value of the parameter register group 101 and the value of the window counter group 102, and sends the scanning position detection signal to the timing control circuit 107. Supply. Further, the window comparator 106 compares the window vertical total value with the value of the vertical counter 105c, and when they match, supplies a reset signal to the address generation circuit 108.

The timing control circuit 107, based on the in-screen scanning position detection signal from the screen comparator 103, outputs a horizontal / vertical synchronizing signal (Sync), VR.
AM30 refresh start signal (Refresh),
VRAM 30 transfer cycle start signal (Transfer)
r), blink control signal (Blink), external video window display enable signal (Movie), in-screen hardware cursor display enable signal (Cur)
Sor) is generated. Also, the timing control circuit 107
Generates a window display enable signal (Display) and an in-window hardware cursor display enable signal (Cursor) based on the in-window scanning position detection signal from the window comparator 106.

Here, the external video window display enable signal (Movie), the hardware cursor display enable signal (Cursor), and the window display enable signal (Display) are used to display the external video window, the hardware cursor, and the window area, respectively. It is a display enable signal that designates a period, and includes a horizontal display period signal and a vertical display period signal.

The address generation circuit 108 calculates the RA of the VRAM 30 based on the window parameter, the count output of the horizontal counter 105b, and the line compare signal.
Generate the display address for the M to SAM data transfer cycle. That is, in the transfer cycle of the VRAM 30, one line (eg 10
Data of 24 pixels) is transferred to the SAM, and the line to be transferred is determined by the display address from the address generation circuit 108. The value of this display address is
The count is incremented by +1 from the start address indicating line 1, and when the value reaches 480 lines is reached, the count value is returned to the start address by the reset signal. Also,
This count-up operation is performed every time the count output of the horizontal counter 105b indicates 640 dots.

Next, the display timing control operation by the CRTC 16 of FIG. 3 will be described with reference to the timing chart of FIG. Here, as shown in FIG. 2, it is assumed that a medium resolution window area 200 screen of 640 × 480 dots of VGA specifications is displayed on a screen area 100 of 1024 × 768 dots of XGA specifications. It is assumed that the coordinates of the display start position of the window area are specified by (Xw, Yw).

In FIG. 5, (a) is a horizontal synchronizing signal (H-SYNC) supplied from the timing control circuit 107 to the display monitor, and (b) is within one horizontal scanning period generated by the timing control circuit 107. Is a window display enable signal (H-Display). 1024 × 7 of XGA specifications in the screen area 100
When displaying a high resolution screen of 68 dots, the screen area 100 is scanned so that data display of 1024 dots is executed within one horizontal line defined by the horizontal synchronizing signal (H-SYNC). In synchronization with this scanning timing, from the horizontal counter 102b and the vertical counter 102c, an X address (X-ADDR) and a Y address (X-ADDR) indicating the scanning position on the screen area 100 as shown in (c) and (d), respectively, are displayed. Y-ADDR) is output. The X address (X-ADDR) is sequentially incremented according to the dot to be scanned. In addition, the Y address (Y-
ADDR) is incremented each time the display line to be scanned is updated.

(E), (f), (g), (h), (i)
Are Y coordinates indicating scanning positions = Y0 to Yw−1,
Y coordinate = Yw, Y coordinate = Yw + 1, Y coordinate = Yw + 48
VR when 0, Y coordinate = Yw + 481 to Y767
It shows the AM access timing. here,
“XX” indicates a data transfer cycle for transferring VGA data from the RAM of the VRAM 30 to the SAM. This data transfer cycle is set in the horizontal blanking period, as shown in the figure, and the display address is updated for the data transfer cycle every horizontal blanking period.

In the data transfer cycle, data (1024 dots) for one line of the VRAM 30 designated by the display address is read. Y coordinate = Y0 to Y
In the range of w−1 and the range of Yw + 481 to Y767, only the CRTC 161 operates and the window CRTC
162 is not operated. Y coordinate = Yw to Yw + 480
In the range of, by the control of the window CRTC162,
The display address for the data transfer cycle is generated. The value of this display address is incremented by +1 every time the horizontal counter 105b counts 640 dots. Then, the data for 640 dots of the 1024 dots is the window display enable signal (H-Display).
It is displayed on the display during the period y).

As described above, by using the CRTC 16 of FIG. 3, the 640 × 480 dot medium resolution data of the VGA specification is displayed in the window area 200 designated by the window parameter. Therefore, FIG.
, The display start position coordinates and the window size (total number of horizontal characters, total number of vertical lines) are changed according to the window parameters.
VGA data can be displayed in an arbitrary size at an arbitrary position on the screen 100 of 4 × 768 dots. In this case, if the window size is made smaller than 640 × 480 dots, only a part of the medium resolution data of 640 × 480 dots of the VGA specification is displayed in the window area 200.
Will be displayed inside.

Such control of the display position of the window area 200 is similarly performed for the external video data. The operation of the entire display controller 10 shown in FIG. 1 will be described below with reference to FIGS. 7 and 8 by taking an example in which VGA data, external video data, and a hardware cursor are displayed in a superimposed manner.

FIG. 7 schematically shows the relationship between the data flow in the display controller 10 of FIG. 1 and the timing control by the two CRTCs 161 and 162.
Here, the sprite display start position coordinates for displaying the hardware cursor are (Xs, Ys), the display start position coordinates of the external video window for displaying the external video data are (Xv, Yv), and are created by the application program. It is assumed that the window area start position coordinates for displaying the data such as the displayed VGA are designated as (Xw, Yw).

These coordinate data (Xs, Ys), (X
v, Yv), (Xw, Yw) are comparators 103a, 103b, 103 in the screen comparator 103.
c is compared with the X address of the horizontal counter 102b and the Y address of the vertical counter 102C, respectively.

First, when the value of the vertical counter 102C coincides with Ys, the sply display timing circuit 107a of the timing control circuit 107 operates and the enable signal is given to the sprite display circuit 27. The sprite display circuit 27 outputs the value of the sprite color register 25 as sprite display data according to the sprite data read from the sprite memory 19 via the serializer 20. Next, when the value of the horizontal counter 102b matches Xs, the splice display timing circuit 10
7a is a hardware cursor display enable signal (C
ursor) is generated. This hardware cursor display enable signal (cursor) is sent to the CRT video multiplexer 26, whereby the sprite display data is selected as video data.

When the value of the vertical counter 102C coincides with Yv, the external video display timing circuit 107b of the timing control circuit 107 operates. Then, when the value of the horizontal counter 102b coincides with Xv, the external video window display enable is enabled. A signal (Movie) is generated. This external video window display enable signal (M
Ovie) is sent to the CRT video multiplexer 26, which selects the external video data as the video data.

Similarly, the value of the vertical counter 102C is Yw.
Window CRTC162 is activated, V
A display address for reading VGA data from the RAM 30 is generated. The VGA data is displayed by the display control circuit 30.
0 converts to CRT video data. Then
When the value of the horizontal counter 102b matches Xw, the window CRTC 162 generates a window display enable signal (Display). The window display enable signal (Display) is sent to the CRT video multiplexer 26, which selects VGA data.

By such a video data selection operation, as shown in FIG. 8, a VGA application window area 200, an external video window area 500 such as a moving picture, a hardware area, etc. are displayed on a screen area 100 of 1024 × 768 pixels. A sprite area 400 such as a wear cursor can be displayed in an overlapping manner. In this case, priority control is performed in the overlapping display portion, and one of the VGA application window area 200, the external video window area 500, and the sprite area 400 is selected.
Only one data item is selected. In the figure, the case where the sprite, the external video window, and the VGA application are displayed in the priority order is shown. Such priority control can be easily realized, for example, by providing a calculation circuit between the display period signals in the control input stage of the CRT video multiplexer 26.

Further, for the control for displaying the border color in the area other than the VGA application window area 200, a circuit for generating the border color data is provided in the display control circuit 300, and the border color data is windowed by the multiplexer 26. Display enable signal (Di
This can be achieved by selecting during the non-occurrence of (spray). In this case, the control of the multiplexer 26 is
A signal indicating a border area can be generated from the horizontal / vertical synchronization signal and the horizontal / vertical display enable signal (Display), and the signal can be used.

As described above, the display controller 10 is provided with the two display timing control circuits of the screen CRTC 161 and the window CRTC 162, and the screen CRTC 161 controls the screen area 100 of 1024 × 768 pixels according to the screen parameters. To generate a sync signal for
The window CRTC 162 controls the display of the window area 200 according to the window parameter. When the display start position of the window area 200 is detected by the screen CRTC 161, the window CRTC 16
2, the display control of the window area 200 is started,
By this, from the start address of VRAM30 to VG
The A data is sequentially read and converted into video data. This video data is supplied to the display monitor during the display period of the window area defined by the window display enable signal (Display), whereby the video data is displayed in the window area.

In this case, the position and size of the window area 200 can be changed programmably by the value of the window parameter set in the parameter register group. Therefore, the medium resolution data created by the VGA application program can be displayed on the high resolution display screen at any position and at any size.

Further, since the data is read from the start address corresponding to the drawing start position on the VRAM 30 by the application program, the window display can be performed in the state where the existing application program is used as it is without changing the data storage position of the VRAM 30. I can do it.

Further, the parameter multiplexer 104
By supplying the window parameter instead of the screen parameter to the screen CRTC 161, the parameter value used in the screen CRTC 161 becomes the same as the window parameter value used in the window CRTC 162, and the horizontal / vertical corresponding to the size of the window area 200. A sync signal is generated. In this case, if the CRT display 50 is used,
The 640 × 480 pixel data created by the VGA application program is transferred to the CRT display 5
It can be displayed in the full screen mode on the entire 0 display screen.

Since the window CRTC 162 can be realized by a gate circuit almost similar to the screen CRTC 161, it is possible to design the window CRTC 162 that effectively uses the circuit layout of the conventional CRTC.

In the above embodiment, the case where the VGA window is displayed on the XGA specification screen has been described, but SVGA (Super Video Graphi) is used.
You may comprise so that the window of VGA may be displayed on the screen of (csArray).

9 to 12 are block diagrams showing a third embodiment of the present invention. A screen CRTC 161 and an application window C are provided on the CRTC 16 shown in FIG.
RTC 162 and external video window CRTC 163
It has and. According to this embodiment, the normal resolution (for example, VGA data), the high resolution (for example, XGA data), and the external video data can be superimposed and displayed at an arbitrary position in an arbitrary size. Screen CRTC1
A display address generator 102d is provided at 61. In the image memory 30, in addition to the display data from the CPU 1, display data from the accelerator, digital external video data obtained by converting analog external video data into digital data via the A / D converter 33, and digital video from a video CD. The data is selected by the multiplexer 31 and taken into the image memory 30. The display address from the screen CRTC 161 and the external video window CRTC 163 are stored in the image memory 30.
And the display address from the application window CRTC 162 are selected by the multiplexer 35 and input. Video display control circuit 3
Reference numeral 7 is composed of a circuit for converting the input YUV signal into an RGB signal, an enlarging / reducing circuit, and the like.

FIG. 10 is a detailed block diagram of the screen CRTC 161, FIG. 11 is a detailed block diagram of the external video CRTC 163, and FIG. 12 is a detailed block diagram of the application window CRTC 162. The external video window CRTC 163 and the application window CRTC 162 have the same internal configuration. Screen CRTC 161, external video window CRTC 163, application window CRTC
Since the function of each unit of 162 is substantially the same as that of FIG. 3, the same reference numerals are given and the description thereof is omitted.

FIG. 13 is a block diagram showing a fourth embodiment of the present invention, in which a screen CRTC 161 and an external video window CRTC 163 are provided to display the normal resolution display data and the external video data in an overlapping manner. Show. In this embodiment, for example, VGA data and moving image data can be displayed at any position and at any size. The operation of each unit in this embodiment is the same as that in the third embodiment, and the description thereof is omitted.

[0083]

As described above, according to the present invention, medium and low resolution data can be displayed on a high resolution screen as a window of arbitrary position and arbitrary size without rewriting VRAM. It will be possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of a display control device according to an embodiment of the present invention.

FIG. 2 is a screen C provided in the display control device of FIG.
The figure for demonstrating the principle of the display control using RTC and window CRTC.

FIG. 3 is a screen C provided in the display control device of FIG.
The block diagram which shows an example of a concrete structure of RTC and window CRTC.

FIG. 4 is the screen CRTC and window C of FIG.
The figure for demonstrating the parameter register group referred by RTC.

FIG. 5 is the screen CRTC and window C of FIG.
7 is a timing chart illustrating a display timing control operation executed by the RTC.

FIG. 6 is a diagram showing an example of a correspondence relationship between the window parameter value of FIG. 2 and the display position of the window area.

7 is a block diagram schematically showing the relationship between the flow of data and the timing control by CRTC in the case where overlay display is performed by the display control device of FIG.

8 is a diagram showing an example of a display screen when overlay display is performed by the display control device of FIG.

FIG. 9 shows a data flow in the display controller 10 and a screen CRTC for superimposing display of VGA data, XGA data and external video data,
Application window CRTC and external video CR
The figure which shows typically the relationship with timing control by TC.

10 is a detailed block diagram of the screen CRTC shown in FIG.

11 is a detailed block diagram of the external video CRTC shown in FIG.

FIG. 12 is an application window CR shown in FIG.
The block diagram of the detail part of TC.

FIG. 13 shows a data flow in the display controller 10 and a screen CRTC and an external video CRT when the VGA data and the external video data are superimposed and displayed.
The figure which shows the relationship with the timing control by C typically.

[Explanation of symbols]

4 ... Display control system, 10 ... Display controller, 12 ... System interface, 14 ... Memory control circuit, 16 ... CRTC, 30 ... VRAM, 101 ... Parameter register group, 102 ... Screen counter group,
103 ... Screen comparator, 104 ... Parameter multiplexer, 105 ... Window counter group, 10
6 ... Window comparator, 107 ... Timing control circuit, 108 ... Display address generating circuit, 161, ... Screen CRTC, 162 ... Window CRTC.

Claims (9)

[Claims] 1. A display control device for controlling a display monitor of a computer system, comprising: an image memory in which display data created by an application program executed by the computer system is stored from a predetermined storage start position; A rewritable parameter register group in which various instructed parameter values are set,
A parameter register group in which screen parameters that specify the size of the entire display screen area that can be displayed on the display monitor and window parameters that specify the display start position and size of the window area to be displayed in the entire display screen area are set. And a first display control circuit for controlling the entire display screen area according to the screen parameter, wherein the horizontal and vertical directions of the display monitor are adjusted according to a scanning timing for displaying the entire display screen area on the display monitor. A means for generating a synchronization signal, a means for generating a coordinate address indicating a scanning position on the entire display screen according to the scanning timing, a window area display start position designated by the window parameter, and a value for the coordinate address. And the comparison result A first display control circuit including means for generating a window area detection signal indicating that the scanning position on the entire display screen has reached the display start position of the window area based on the result; A second display control circuit for controlling the window area, which is responsive to the window area detection signal to generate a display enable signal indicating a display period corresponding to the window area, and to respond to the window area detection signal. And a second display control circuit including means for generating a memory address for reading the display data from the storage start position of the image memory, and the second display control circuit according to the memory address generated by the second display control circuit. The display data is read from the storage start position of the image memory and the display data is displayed. Means for converting into video data to be supplied to a monitor; and the video data during the display period designated by the display enable signal so that the display data created by the application program is displayed in the window area. And a means for supplying the display monitor. 2. The parameter register group is provided,
A register in which a second window parameter for designating a display start position and a window size of a second window area for displaying externally supplied external video data in the entire display screen area; Of the display control circuit, compares the window area display start position designated by the second window parameter with the coordinate address value, and based on the comparison result, the scanning position on the entire display screen is Second
Second indicating that the display start position of the window area has been reached
Means for generating a window area detection signal, and a second display control circuit provided in the second display control circuit for indicating a display period corresponding to the second window area in response to the second window area detection signal. Means for generating a display enable signal, and supplying the external video data to the display monitor during a display period designated by the second display enable signal so that the external video data is displayed in the second window area. The display control device according to claim 1, further comprising: 3. The parameter register group is provided,
A register in which a full-screen mode parameter that specifies whether to display the display data in the full-screen mode on the display monitor is set; and when the full-screen mode is specified by the full-screen mode parameter, the window area is 2. The display control device according to claim 1, further comprising means for switching a parameter value referenced by the first display control circuit from the screen parameter to the window parameter so as to be displayed in a full screen mode. . 4. The display monitor is a flat panel display having a first resolution, display data of a second resolution lower than the first resolution is stored in the image memory, and the screen parameter is the flat screen display. The window parameter includes the total number of horizontal characters and the total number of vertical lines in the display screen area for displaying at the first resolution on the panel display, and the window parameter is the display start position of the window area where the display data at the second resolution is to be displayed and The display control device according to claim 1, wherein the display data created by the application program includes the total number of horizontal characters and the total number of vertical lines, and is the display data of the second resolution. 5. A hardware cursor display enable signal is output when the coordinate address indicating the scanning position on the entire display screen matches the coordinate address indicating the hardware cursor display start position, thereby displaying the hardware cursor. The display control device according to claim 1, further comprising a hardware cursor display timing circuit for performing the above. 6. A display control device for controlling a display monitor of a computer system, comprising: an image memory in which display data created by an application program executed by the computer system is stored from a predetermined storage start position; A rewritable parameter register group in which various instructed parameter values are set,
Screen parameters that specify the size of all display screen areas that can be displayed on the display monitor, application window parameters that specify the display start position and size of the window area of the application program to be displayed in the entire display screen area, and the all A parameter register group in which external video window parameters for designating a display start position and a size of a window area of external video data to be displayed in the display screen area are set, and a first register for controlling the entire display screen area according to the screen parameter A display control circuit for generating horizontal and vertical synchronizing signals for the display monitor in accordance with a scanning timing for displaying the entire display screen area on the display monitor; Means for generating a coordinate address indicating a scanning position on the entire display screen, the application window area display start position designated by the application window parameter and the value of the coordinate address are compared, and based on the comparison result. Means for generating an application window area detection signal indicating that the scanning position on the entire display screen has reached the display start position of the application window area; and an external video window area display start position specified by the external video window parameter. And a value of the coordinate address are compared with each other, and an external video window area detection signal indicating that the scanning position on the entire display screen has reached the display start position of the external video window area is generated based on the comparison result. A first display including means and A control circuit and a second display control circuit for controlling the application window area according to the application window parameter, the display enable signal indicating a display period corresponding to the application window area in response to the application window area detection signal. A second display control circuit including: means for generating a memory address for reading the display data from the storage start position of the image memory in response to the application window area detection signal; A third display control circuit for controlling the external video window area according to an external video window parameter, the third display control circuit displaying a display period corresponding to the external video window area in response to the external video window area detection signal. A third display control circuit including means for generating a enable signal and means for generating a memory address for reading the display data from the storage start position of the image memory in response to the external video window area detection signal. And reading the display data from a storage start position of the image memory according to a memory address generated from a display control circuit selected from the second and third display control circuits, and displaying the display data on the display monitor. Means for converting to video data for supply; the display enable signal such that display data created by the application program in the application window area and the external video data in the external video window area are displayed. During the display period specified by Display control device according to claim the serial video data to and means for supplying to said display monitor. 7. A hardware cursor display enable signal is output when the coordinate address indicating the scan position on the full display screen matches the coordinate address indicating the hardware cursor display start position, thereby displaying the hardware cursor. 7. The display control device according to claim 6, further comprising a hardware cursor display timing circuit for performing the above. 8. A display control device for controlling a display monitor of a computer system, comprising: an image memory in which display data created by an application program executed by the computer system is stored from a predetermined storage start position; A rewritable parameter register group in which various instructed parameter values are set,
Screen parameters that specify the size of the entire display screen area that can be displayed on the display monitor, and external video window parameters that specify the display start position and size of the window area of the external video data to be displayed in the entire display screen area A parameter register group to be set, and a first display control circuit for controlling the entire display screen area according to the screen parameter, wherein the first display control circuit controls the entire display screen area according to a scanning timing for displaying the entire display screen area on the display monitor. Means for generating horizontal and vertical synchronizing signals of a display monitor, means for generating a coordinate address indicating a scanning position on the entire display screen in accordance with the scanning timing, and an external video window specified by the external video window parameter. Start area display A position is compared with the value of the coordinate address, and an external video window area detection signal indicating that the scanning position on the entire display screen has reached the display start position of the external video window area is generated based on the comparison result. A second display control circuit for controlling the external video window area in accordance with the external video window parameter, the external display device including: Means for generating a display enable signal indicating a display period corresponding to the video window area, and generating a memory address for reading the display data from the storage start position of the image memory in response to the external video window area detection signal. A second display control circuit including means for operating the second display control circuit; Means for reading the display data from the storage start position of the image memory according to the memory address, and converting the display data into video data for supplying to the display monitor; and the external video data in the external video window area. A display control device for supplying the video data to the display monitor during a display period designated by the display enable signal so as to be displayed. 9. A hardware cursor display enable signal is output when the coordinate address indicating the scanning position on the entire display screen matches the coordinate address indicating the hardware cursor display start position, thereby displaying the hardware cursor. 9. The display control device according to claim 8, further comprising a hardware cursor display timing circuit for performing the above.