JPH07220485A - Semiconductor nonvolatile memory - Google Patents

Abstract

PURPOSE:To obtain a semiconductor nonvolatile memory in which high rate read operation is realized while enhancing the data retaining capacity. CONSTITUTION:A nonvolatile memory is provided with a high rate read mode in addition to a normal read mode wherein the read voltage is set higher for the high rate read mode than for the normal read mode and the operating time for high rate read mode is measured by means of a timer circuit 2. When the measured operating time reaches a preset time, a refresh circuit 3 functions to erase/rewrite a memory cell array 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile memory, for example, a semiconductor nonvolatile memory device such as a flash EEPROM.

[0002]

2. Description of the Related Art Conventionally, for example, by injecting electrons into a floating gate, data "1" /
The flash EEPROM that judges "0" is a normal N
OR type, DINOR (DIvided bit line NOR) type, NAN
Classified as D type.

NOR type and DINOR type flash E
In the EPROM, at the time of data reading, the selected word line is set to 3V to 5V, the unselected word line is set to 0V, the selected bit line is set to 1V to 2V, and the unselected bit line is set to 0V.
When reading data from the NAND flash EEPROM, the selected word line is 0 V and the non-selected word line is 3 V.
V to 5V, selected bit lines are set to 2V to 3V, and unselected bit lines are set to 0V.

As described above, the set voltage of the selected word line and bit line in the read mode in the NOR type and DINOR type flash EEPROM is programmed into the non-programmed cells by the so-called soft write channel hot electron injection. It is set to a low level because there is a risk of

In addition, a NAND flash EEPROM
In the read mode, the set voltage of the non-selected word line and the selected bit line is low because the so-called read gate disturb in which the data of the non-programmed cell on the non-selected word line is programmed by FN tunneling may occur. It is set in the eye.

[0006]

With respect to these read disturbs, it is general to guarantee the DC bias for 10 years assuming the worst case. Therefore, the bias voltage at the time of reading is inevitable. Get lower. as a result,
In a normal flash memory read operation, the mask R
The present situation is that the access time is significantly slower than that of OM and the like.

By the way, it is a very strict standard to guarantee 10 years of DC in terms of disturb at the time of reading, and it is an excessive specification in most applications of the flash memory. That is, it is extremely difficult to use the memory cell at a specific address only for 10 years.

As means for improving the data retention capability, for example, in the case of a floating gate type non-volatile memory, a first gate insulating film between the substrate and the floating gate and a second gate insulating film between the floating gate and the control gate are used. There is a method in which the thickness of the gate insulating film is set to, for example, about 10 nm to 20 nm to make it difficult for electrons in the floating gate to be discharged. But,
This method further increases the delay of access time.

As a non-volatile memory, there is a MONOS type memory instead of a floating gate type memory.
This type of non-volatile memory originally has a low data retention capacity, and it is almost impossible to retain data for 10 years or more.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor nonvolatile memory device capable of high-speed operation and capable of improving the data retention capacity.

[0011]

In order to achieve the above object, the semiconductor nonvolatile memory device of the present invention has a high speed read mode in addition to the normal read mode, and the read voltage in the high speed read mode is normally read. A circuit for setting the voltage higher than the read voltage in the mode is provided.

Further, the semiconductor nonvolatile memory device of the present invention has a detection circuit for detecting the progress state of the disturb at the time of reading, and a refresh circuit for rewriting to the memory cell according to the detection result of the detection circuit. . Further, the detection circuit detects the progress state of disturb during reading in the high-speed reading mode.

Further, in the semiconductor nonvolatile memory device of the present invention, the detection circuit measures the elapsed time after the high speed read mode is set, and outputs the elapsed signal to the refresh circuit when the measured time reaches a preset time. The refresh circuit is composed of a timer circuit, and the memory cell is rewritten by the input of the elapsed signal.

In the semiconductor nonvolatile memory device of the present invention, the detection circuit counts the number of accesses in the high speed read mode, and outputs a count signal to the refresh circuit when the count value reaches a preset value. The refresh circuit is configured by a circuit and rewrites the memory cell by inputting the count signal.

Further, in the semiconductor nonvolatile memory device of the present invention, a circuit for rereading with a read voltage set higher than the normal read voltage after the normal read operation is compared with the normal read data and the reread data. And a refresh circuit that outputs a mismatch signal when both data do not match, and a refresh circuit that rewrites the memory cell by inputting the mismatch signal.

[0016]

According to the present invention, in the high speed read mode,
The read voltage is set higher than the read voltage in the normal read mode, and the read operation is performed.

Further, according to the present invention, by the detection circuit,
For example, the progress state of disturb during high-speed reading is detected, and the refresh circuit rewrites the memory cell as a refresh operation according to the detection result of the detection circuit.

Further, according to the present invention, the detection circuit is composed of a timer circuit. In this timer circuit, the elapsed time after the high-speed read mode is set is measured, and when the measured time reaches a preset time, the elapsed signal is sent. It is output to the refresh circuit. Then, the refresh circuit rewrites the memory cell.

Further, according to the present invention, the detection circuit is composed of a counting circuit. In this counting circuit, the number of accesses in the high-speed read mode is counted, and when the count value reaches a preset value, the count signal is refreshed. It is output to the circuit. Then, the refresh circuit rewrites the memory cell.

Further, according to the present invention, subsequent to the normal read operation, rereading is performed with a read voltage set higher than the normal read voltage. Then, the read data at the time of normal read and the read data at the time of re-read are input to the comparison circuit, and the two data are compared.
As a result of the comparison, when the two data do not match, a mismatch signal is generated and output to the refresh circuit. With the input of the mismatch signal, the refresh circuit rewrites the memory cell.

[0021]

First Embodiment FIG. 1 is a block diagram showing a first embodiment of a semiconductor nonvolatile memory device with a high speed read mode and a refresh function according to the present invention. In FIG. 1, 1
Is an operation mode discrimination control circuit, 2 is a timer circuit, 3 is a refresh circuit, and 4 is a memory cell array.

The operation mode discriminating control circuit 1 erases, writes, and reads data according to the input of the signal S _IN from the outside.
And each operation mode of high-speed reading is determined, and a voltage according to each operation mode is supplied to a predetermined word line and bit line of the memory cell array 4. This device
The read mode includes a high-speed read mode in addition to the normal read mode. In the high-speed read mode, a voltage higher than the voltage supplied to the memory cell array 4 during the normal read is supplied to perform the high-speed read.

In the high speed read mode, the timer circuit 2 measures the elapsed time after the high speed read mode is set from the output of the operation mode discrimination control circuit 1, and when the measured time reaches a preset time, the elapsed signal S ₂ is output. Output to the refresh circuit 3. Then, the measurement time cumulatively added in parallel with the output of the elapsed signal S ₂ is reset.

When the refresh circuit 3 receives the output signal S ₂ from the timer circuit 2,
All bits are collectively erased / rewritten to refresh.

The memory cell array 4 is composed of, for example, a NOR type flash EEPROM, a DINOR type flash memory, or a NAND type flash EEPROM. This device has a normal read mode and a high-speed read mode as read modes, and the voltages applied to the word line and the bit line are different in each read mode.

The following are NOR type, DINOR type and NAN
Bias conditions at the time of normal reading and high-speed reading of each D-type flash EEPROM are shown in FIGS.
Will be explained step by step with reference to.

First, referring to FIG. 2 and FIG.
The bias conditions for normal read in
And Fig. 5 explains the bias conditions during high-speed reading.
Reveal In the circuit diagrams of FIGS. 2 and 4, WL
₁~ WL₃Is the word line, BLS ₁~ BLS₃, BLD₁
~ BLD₃Is the bit line, MT₁₁~ MT₃₃Is a memory cell
Shows each transistor.

In the NOR type flash EEPROM, when the memory cell transistor MT ₂₂ is selected at the time of normal reading, as shown in FIGS. 2 and 3, the selected word line WL ₂ is 3V to 5V and the unselected word line WL ₂ is not selected. WL ₁ and WL ₃ are 0V, selected bit line BLD ₂ is 1V
2V, the unselected bit lines BLS ₁ ~BLS _3, BL
D ₁ and BLD ₃ are set to 0V, respectively. On the other hand, when the memory cell transistor MT ₂₂ is selected at the time of high-speed reading, as shown in FIGS. 4 and 5, the selected word line WL ₂ is 5V to 7V and the unselected word lines WL ₁ and WL are WL. ₃ is 0V, selected bit line BLD ₂ is 3
V-4V, unselected bit lines BLS ₁ -BLS ₃ , BLD
₁ and BLD ₃ are set to 0V, respectively.

Next, referring to FIGS. 6 and 7, DINOR type
FIG. 8 shows the bias condition at the time of normal reading in FIG.
And Fig. 9 shows the bias conditions for high-speed reading.
Explain. In addition, in the circuit diagrams of FIG. 6 and FIG.
SL₁₁, SL_{twenty one}Is the select gate line, WL₁₁~ WL₁₈, WL
_{twenty one}~ WL₂₈Is the word line, MBL₁₁, MBL₁₂Is the main bit
Line, SBL₁₁, SBL₁₂, SBL_{twenty one}, SBL_{twenty two}Is a debit
Line, SRL₁₁, SRL₁₂, SRL_{twenty one}, SRL_{twenty two}Is common
Source line, ST₁₁, ST₁₂, ST_{twenty one}, ST_{twenty two}Is a selection game
Transistor, MT₁₁₁~ MT₁₁₈, MT₁₂₁~ MT
₁₂₈, MT₂₁₁~ MT ₂₁₈, MT₂₂₁~ MT₂₂₈Is a memo
Recell transistors are shown respectively.

In the DINOR type flash EEPROM
In normal read operation, memory cell transition
Star MT₁₁₄If you select
So that the selected word line WL₁₄3V-5V, non-selective
Wire line WL₁₁~ WL₁₃, WL ₁₅~ WL₁₈, WL_{twenty one}~ WL
₂₈Is 0V, selected bit line MBL₁₁Is 1V to 2V, non-selected
Bit line MBL₁₂To 0V, select gate line SL₁₁Is 3 ~
5V, unselected gate line SL_{twenty one}Are set to 0V respectively
Be done. On the other hand, when reading at high speed,
Recell transistor MT₁₁₄If you select
And as shown in FIG. 9, the selected word line WL₁₄Is 5V ~
7V, unselected word line WL₁₁~ WL₁₃, WL₁₅~ W
L₁₈, WL_{twenty one}~ WL₂₈Is 0V, selected bit line MBL₁₁But
3V to 4V, unselected bit line MBL₁₂To 0V,
Air line SL₁₁To 3-5V, unselected gate line SL_{twenty one}Is 0
Respectively set to V.

Next, referring to FIG. 10 and FIG.
Figure shows the bias conditions for normal reading in the mold
12 and FIG. 13 show bias conditions for high-speed reading.
Will be described. The circuit diagrams of FIG. 10 and FIG.
At SL₁₁, SL₁₂, SL_{twenty one}, SL _{twenty two}Is a selection game
Line, WL₁₁~ WL₁₈, WL_{twenty one}~ WL₂₈Is the word line, B
L₁₁, BL ₁₂Is a bit line, ST₁₁₁, ST₁₁₂, ST
₁₂₁, ST₁₂₂, ST₂₁₁, ST₂₁₂, ST₂₂₁, ST
₂₂₂Is a select gate transistor, MT₁₁₁~ MT₁₁₈，
MT_{12 1}~ MT₁₂₈, MT₂₁₁~ MT₂₁₈, MT₂₂₁~
MT₂₂₈Are memory cell transistors
It

In the NAND type flash EEPROM, when the memory cell transistor MT ₁₁₄ is selected at the time of normal reading, as shown in FIGS. 10 and 11, the selected word line WL ₁₄ is 0 V and the unselected word line WL _{11 is} selected. _{~WL 13, WL 15 ~WL 18,} WL 21 ~WL 28 is 3V to 5V, the selected bit line BL ₁₁ 2V to 3V, the unselected bit line BL ₁₂ is 0V, the select gate line SL _11, SL ₁₂
Is set to 3-5V, and the non-selected gate lines SL ₂₁ and SL ₂₂ are set to 0V. On the other hand, when the memory cell transistor MT ₁₁₄ is selected at the time of high-speed reading, as shown in FIGS. 12 and 13, the selected word line WL ₁₄ is 0 V, the unselected word lines WL _{11 to} WL ₁₃ ,
_{WL 15 ~WL 18, WL 21 ~WL} 28 is 5V to 7V, the selected bit line BL ₁₁ 3V to 5V, the non-selected bit line BL ₁₂ 0
V, the select gate lines SL ₁₁ and SL ₁₂ are set to 5 to 7 V, and the non-select gate lines SL ₂₁ and SL ₂₂ are set to 0 V, respectively.

Next, the operation of the configuration of FIG. 1 will be described.
First, the external signal S_INOperation mode judgment control time
Path 1 erases, writes, and reads based on the input signal
And the operation mode of high-speed reading is determined.
It Then, a predetermined word line in the memory cell array 4
The voltage corresponding to the determined operation mode is supplied to the
It For example, the judgment operation mode is the normal read mode
If the memory cell array 4 is of DINOR type,
Optional word line WL₁₄Is 3V-5V, unselected word line WL ₁₁
~ WL₁₃, WL₁₅~ WL₁₈, WL_{twenty one}~ WL₂₈Is 0V, select
Optional bit line MBL₁₁1V to 2V, unselected bit line MB
L₁₂To 0V, select gate line SL₁₁Is unselected for 3-5V
Optional gate line SL_{twenty one}Are set to 0V, respectively. to this
Read data from the desired memory cell transistor
Will be issued.

On the other hand, the discrimination operation mode is high-speed reading.
In the output mode, when the memory cell array 4 is a DINOR type
If the selected word line WL₁₄Is 5V to 7V, non-selected word
Line WL₁₁~ WL₁₃, WL₁₅~ WL₁₈, WL_{twenty one}~ WL₂₈
Is 0V, selected bit line MBL ₁₁Is 3V-4V, non-selected
Line MBL₁₂To 0V, select gate line SL₁₁Is 3-5
V, non-selected gate line SL_{twenty one}Are set to 0V respectively
It This allows the desired memory cell transistor
Data is read out at high speed and the timer circuit 2
The time elapsed after setting the high-speed reading mode is measured.
And the measured values are accumulated. Then, the timer circuit 2 measures
When the operating time under the specified high-speed read mode is set
When the time reaches, the elapsed signal S from the timer circuit 2₂Reflex
Output to the output circuit 3. In addition, the timer circuit 2 is
Issue S₂The measurement time accumulated cumulatively in parallel with the output of
Is set.

When the refresh circuit 3 receives the output signal S ₂ from the timer circuit 2, it is judged that the progress of the read disturb has reached a level at which rewriting is necessary.
All bits in the memory cell array 4 are collectively erased /
A refresh operation is performed by rewriting.

As described above, according to this embodiment,
In the flash EEPROM, a high-speed read mode is provided in addition to the normal read mode, the read voltage is set higher in the high-speed read mode than in the normal read mode, and the operation time in the high-speed read mode is set by the timer circuit 2. Measure and erase / refresh as a refresh operation when the measured time reaches a preset time
Since the rewriting is performed, the high-speed reading operation can be realized while improving the data holding capacity.

[0037]

Second Embodiment FIG. 14 is a block diagram showing a second embodiment of a semiconductor nonvolatile memory device with a high speed read mode and a refresh function according to the present invention. The present embodiment is different from the above-described first embodiment in that instead of using the timer circuit 2 as the circuit for detecting the read disturb in the high speed read mode, the number of word line accesses in the high speed read mode is counted and the access count is The access number counting circuit 5 that outputs the count signal S ₅ when the number of times set in advance is reached is provided, and refreshing by erasing / rewriting is performed based on the signal S ₅ .

The other structure is the same as that of the first embodiment, and the same effects as those of the above-described first embodiment can be obtained.

The word line may be divided into a plurality of blocks, and a word line access frequency counting circuit may be added to each block to refresh each word line block.

[0040]

Third Embodiment FIG. 15 is a block diagram showing a third embodiment of the semiconductor nonvolatile memory device according to the present invention. The present embodiment is different from the above-described first and second embodiments in that after the normal read operation is performed, the reread operation is performed with a read voltage higher than that in the normal read, and the read data by the normal read and the reread are performed. The comparison circuit 6 is provided instead of the timer circuit 2 and the access number counting circuit 5 so that the refresh operation is performed if the read data is compared with the read data.

That is, the comparison circuit 6 has the predetermined data of the memory cell array 4 in the normal read mode and the data read from the predetermined memory cell of the memory cell array 4 and the re-read mode following the normal read operation. The data read from the memory cell is compared, and if the two do not match, the mismatch signal S ₂ is output to the refresh circuit 3.
Output to.

In such a configuration, the external signal S_INBut
In the input operation mode determination control circuit 1,
Based on the erase, write, and read operation modes,
Another is done. Then, the predetermined cell of the memory cell array 4 is
According to the operation mode that is determined for the word line and the bit line.
Voltage is supplied. For example, for a memory cell array
After being written, the normal read operation
Check if desired memory contents are written
Is done. In this normal read mode, the memory cell array
When the ray 4 is DINOR type, the selected word line WL₁₄
Is 3V-5V, unselected word line WL₁₁~ WL₁₃, WL₁₅
~ WL₁₈, WL_{twenty one}~ WL₂₈Is 0V, selected bit line MBL
₁₁1V to 2V, unselected bit line MBL₁₂Is set to 0V
Optional gate line SL₁₁To 3-5V, unselected gate line SL _{twenty one}
Are set to 0V, respectively. This will give you the desired memo.
When data is read from the recell transistor
Then, the read data is input to the comparison circuit 6.

Next, the operation mode determination control circuit 1
The read voltage is higher than the read voltage during normal read.
It is set to a higher value and rereading is performed. For example memo
If the re-cell array 4 is DINOR type, the selected word
Line WL₁₄5V to 7V, unselected word line WL₁₁~ W
L₁₃, WL₁₅~ WL₁₈, WL_{twenty one}~ WL ₂₈Is 0V, select
Line MBL₁₁3V to 4V, unselected bit line MBL₁₂
To 0V, select gate line SL₁₁Is 3-5V, non-selective
Air line SL_{twenty one}Are set to 0V, respectively. By this
Data from the desired memory cell transistor at high speed
The read data is read and the read data is compared again.
Entered in.

In the comparison circuit 6, the data read from the predetermined memory cell of the memory cell array 4 and the data read from the predetermined memory cell of the memory cell array 4 in the re-read mode performed following the normal read operation. The data is compared. The result of this comparison, for example, typically read data is "0", re-read data is "1", mismatch signal S ₆ when both do not match is output to the refresh circuit 3.

When the refresh circuit 3 receives the output signal S ₆ from the comparison circuit 6,
The same writing is performed again. After that, the re-read operation is performed again with a high read voltage, and the refresh operation is repeated until the normal read data and the re-read data match.

As described above, according to this embodiment,
For example, even if the data holding capacity is reduced in a small number of bits among a large number of bits, it can be recovered by a refresh operation, and the data holding capacity can be improved. In particular, it is effective for a device such as a MONOS type non-volatile memory which is said to have insufficient data retention capability.

[0047]

As described above, according to the present invention,
There is an advantage that a high-speed read operation can be realized and the data holding capacity can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a semiconductor nonvolatile memory device with a high-speed read mode and a refresh function according to the present invention.

FIG. 2 is a circuit diagram showing bias conditions during normal reading in a NOR flash EEPROM.

FIG. 3 is a diagram showing a bias condition during normal reading in a NOR flash EEPROM.

FIG. 4 is a circuit diagram showing bias conditions during high-speed reading in a NOR flash EEPROM.

FIG. 5 is a diagram showing bias conditions during high-speed reading in a NOR flash EEPROM.

FIG. 6 is a circuit diagram showing bias conditions during normal reading in the DINOR type flash EEPROM.

FIG. 7 is a diagram showing a bias condition during normal reading in a DINOR type flash EEPROM.

FIG. 8 is a circuit diagram showing a bias condition at the time of high-speed reading in the DINOR type flash EEPROM.

FIG. 9 is a diagram showing a bias condition during high-speed reading in a DINOR type flash EEPROM.

FIG. 10 is a circuit diagram showing bias conditions during normal reading in a NAND flash EEPROM.

FIG. 11 is a diagram showing bias conditions during normal reading in a NAND flash EEPROM.

FIG. 12 is a circuit diagram showing a bias condition at the time of high-speed reading in the NAND flash EEPROM.

FIG. 13 is a diagram showing bias conditions during high-speed reading in a NAND flash EEPROM.

FIG. 14 is a block diagram showing a second embodiment of a semiconductor nonvolatile memory device with a high speed read mode and a refresh function according to the present invention.

FIG. 15 is a third semiconductor nonvolatile memory device according to the present invention.
It is a block diagram showing an example of.

[Explanation of symbols]

 1 ... Operation mode discrimination control circuit 2 ... Timer circuit 3 ... Refresh circuit 4 ... Memory cell array 5 ... Access count circuit 6 ... Comparison circuit

[Procedure amendment]

[Submission date] April 22, 1994

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 6

[Correction method] Change

[Correction content]

[Figure 6]

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Correction target item name] Figure 8

[Correction method] Change

[Correction content]

[Figure 8]

Claims (6)

[Claims] 1. A semiconductor nonvolatile memory device having a high-speed read mode in addition to a normal read mode and including a circuit for setting a read voltage in the high-speed read mode higher than a read voltage in the normal read mode. 2. The semiconductor non-volatile memory device according to claim 1, further comprising: a detection circuit for detecting a progress state of disturb at the time of reading, and a refresh circuit for rewriting to a memory cell according to a detection result of the detection circuit. . 3. The semiconductor non-volatile memory device according to claim 2, wherein the detection circuit detects a progress state of disturb during reading in the high-speed read mode. 4. The detection circuit is composed of a timer circuit which measures the elapsed time after setting the high-speed read mode and outputs an elapsed signal to the refresh circuit when the measured time reaches a preset time. 4. The semiconductor nonvolatile memory device according to claim 2, wherein the memory cell is rewritten by inputting a progress signal. 5. The detection circuit is composed of a counting circuit that counts the number of accesses in a high-speed read mode and outputs a count signal to a refresh circuit when the count value reaches a preset value. 4. The semiconductor nonvolatile memory device according to claim 2, wherein the memory cell is rewritten by inputting a count signal. 6. A circuit for performing re-reading with a read-out voltage set higher than the normal read-out voltage after a normal read-out operation, and comparing the normal read-out data with the re-read out data, and when both data do not match. A semiconductor nonvolatile memory device comprising: a comparison circuit that outputs a mismatch signal; and a refresh circuit that rewrites a memory cell by inputting a mismatch signal.