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JPH07226414A - Method of sealing semiconductor device, and resin-sealed semiconductor device - Google Patents

Method of sealing semiconductor device, and resin-sealed semiconductor device

Info

Publication number
JPH07226414A
JPH07226414A JP1565894A JP1565894A JPH07226414A JP H07226414 A JPH07226414 A JP H07226414A JP 1565894 A JP1565894 A JP 1565894A JP 1565894 A JP1565894 A JP 1565894A JP H07226414 A JPH07226414 A JP H07226414A
Authority
JP
Japan
Prior art keywords
resin
semiconductor element
circuit board
sealing
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1565894A
Other languages
Japanese (ja)
Inventor
Shinji Takei
信二 武井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP1565894A priority Critical patent/JPH07226414A/en
Publication of JPH07226414A publication Critical patent/JPH07226414A/en
Pending legal-status Critical Current

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To provide a method of reliable resin sealing of a semiconductor chip placed in a given position on a circuit board. CONSTITUTION:A method of sealing a semiconductor chip 1 on a circuit board 3 with resin comprises the steps of placing a solid piece of resin 9, and heating and compressing the solid piece of resin. Since the semiconductor chip is placed face down, its face with electrodes is not covered with resin. Further, the whole semiconductor chip on the circuit board, except the chip surface with electrodes, is molded with resin.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は半導体素子の樹脂封止
方法および樹脂封止型半導体装置に関し、特に回路基板
に実装された半導体素子の樹脂封止方法および樹脂封止
型半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin encapsulation method for a semiconductor element and a resin encapsulation type semiconductor device, and more particularly to a resin encapsulation method for a semiconductor element mounted on a circuit board and a resin encapsulation type semiconductor device.

【0002】[0002]

【従来の技術】半導体装置の回路基板への実装は、従来
から種々な方法が採用されてきた。最も確実で容易な方
法として、半導体素子を樹脂の圧縮成形(トランスファ
成形)により封止した半導体パッケージの外部導出リー
ドを、半田付けによって回路基板に接続する方法があ
る。しかしこの方法は実装密度があまり高くないという
欠点がある。
2. Description of the Related Art Various methods have been conventionally used for mounting a semiconductor device on a circuit board. As the most reliable and easy method, there is a method of connecting the external lead-out of a semiconductor package in which a semiconductor element is sealed by resin compression molding (transfer molding) to a circuit board by soldering. However, this method has a drawback that the packaging density is not very high.

【0003】そこで樹脂封止されない裸の半導体素子を
回路基板の所定の位置に導電性ペーストで固定接続後、
半導体素子の電極と回路基板の回路パターンとを金属細
線で接続し、液状樹脂を滴下して被覆する非圧縮による
樹脂封止方法も行われている。この方法では裸の半導体
素子を使用するので実装密度をあげることができる。
Therefore, a bare semiconductor element not resin-sealed is fixedly connected to a predetermined position on the circuit board with a conductive paste,
A resin encapsulation method by non-compression in which an electrode of a semiconductor element and a circuit pattern of a circuit board are connected by a thin metal wire and a liquid resin is dropped and covered is also used. In this method, since a bare semiconductor element is used, the packaging density can be increased.

【0004】さらに上記の液状樹脂を滴下して被覆する
方法に換えて、トランスファ成形用の金型に半導体素子
を搭載した回路基板を挟持し、溶融可塑化した樹脂を圧
力をかけて半導体素子部分に流入させて圧縮成形する方
法も行われている。
Further, instead of the above method of dropping and coating the liquid resin, a circuit board on which a semiconductor element is mounted is sandwiched in a transfer molding die, and the molten plasticized resin is pressed to apply the semiconductor element portion. There is also used a method of injecting into and compressing.

【0005】[0005]

【発明が解決しようとする課題】上記のように外部リー
ドを有する樹脂封止型半導体装置を回路基板に半田付け
する方法は、パッケージ外形の小型薄型化に限界がある
ため、回路基板の実装密度向上の障害になる。また半田
付け方法として半導体装置全体を高温で加熱する赤外線
リフロー方式が主流になっており、加熱時の樹脂パッケ
ージのクラックが大きな問題となっている。実装密度の
向上の観点からは、半導体素子を直接回路基板に取り付
け封止する方法が好ましい。
The method of soldering the resin-encapsulated semiconductor device having the external leads to the circuit board as described above has a limit in reducing the size and thickness of the package. It is an obstacle to improvement. As a soldering method, an infrared reflow method in which the entire semiconductor device is heated at a high temperature has become the mainstream, and cracking of the resin package during heating has become a serious problem. From the viewpoint of improving the mounting density, a method of directly mounting and sealing the semiconductor element on the circuit board is preferable.

【0006】現在回路基板に直接取り付けられた半導体
素子を封止する方法としては、(1)液状の樹脂を半導
体素子表面およびボンディング部分に滴下して硬化させ
る、(2)シート状の固体状樹脂を半導体素子上に置き
加熱溶融して被覆する、(3)トランスファ成形による
樹脂封止、等がある。(1)(2)の場合非圧縮成形の
ため回路基板と樹脂の密着力が圧縮成形に比べ劣るこ
と、樹脂の流動性低下を招くため充填剤を多く含有させ
ることができず、樹脂の成形収縮による半導体素子への
応力を低減させることに限界がある等の問題がある。
At present, as a method for sealing a semiconductor element directly attached to a circuit board, (1) a liquid resin is dropped onto the surface of the semiconductor element and a bonding portion to be cured, and (2) a sheet-like solid resin. Is placed on a semiconductor element to be heated and melted for coating, and (3) resin sealing by transfer molding is available. In the case of (1) and (2), the adhesion between the circuit board and the resin is inferior to that of the compression molding due to non-compression molding, and the resin cannot be contained in a large amount because the fluidity of the resin is deteriorated. There is a problem that there is a limit to reducing the stress on the semiconductor element due to the contraction.

【0007】一方(3)のトランスファ成形では金型を
用いるため回路基板の寸法や回路基板上での半導体素子
の位置が制約されること、またトランスファ成形のため
樹脂の流動性も考慮する必要があり、成形収縮低減の為
のフィラー高充填化と流動性を両立させるためには、球
状フィラー、微細フィラー等の特殊フィラーを用いなけ
ればならず、樹脂価格が高くなるといった問題がある。
On the other hand, in the transfer molding of (3), since the mold is used, the size of the circuit board and the position of the semiconductor element on the circuit board are restricted, and it is necessary to consider the fluidity of the resin for the transfer molding. Therefore, in order to achieve both high filler filling for reducing molding shrinkage and fluidity, special fillers such as spherical fillers and fine fillers have to be used, which causes a problem that the resin price increases.

【0008】本発明は上記事情に鑑みてなされたもの
で、回路基板上の任意の位置に搭載された半導体素子に
対し、密着性が良くかつ信頼性が高い樹脂封止を容易に
形成する手段と、それに基づく新しい樹脂封止型半導体
装置を提供しようとするものである。
The present invention has been made in view of the above circumstances, and is a means for easily forming a resin encapsulation having good adhesion and high reliability with respect to a semiconductor element mounted at an arbitrary position on a circuit board. And a new resin-encapsulated semiconductor device based on it.

【0009】[0009]

【課題を解決するための手段】上記目的を達成するため
に本発明の樹脂封止方法では、回路基板に搭載された半
導体素子の樹脂封止方法において、前記半導体素子上に
固体状樹脂を載置する工程と、前記固体状樹脂を加熱圧
縮成形する工程とを具備することを特徴としている。
In order to achieve the above object, in the resin sealing method of the present invention, in the resin sealing method for a semiconductor element mounted on a circuit board, a solid resin is mounted on the semiconductor element. It is characterized by comprising a step of placing and a step of heat compression molding the solid resin.

【0010】加えて前記半導体素子がフェースダウンで
実装され、その電極面が前記固体状樹脂で被覆されない
ことを他の特徴としている。さらに本発明の樹脂封止型
半導体装置では、配線回路が形成された回路基板と、こ
の回路基板にフェースダウンで実装された半導体素子
と、この半導体素子をその電極面を除いて被覆する封止
樹脂とを具備することを特徴としている。
Another feature is that the semiconductor element is mounted face down and its electrode surface is not covered with the solid resin. Further, in the resin-sealed semiconductor device of the present invention, a circuit board on which a wiring circuit is formed, a semiconductor element mounted face down on the circuit board, and a sealing for covering the semiconductor element except its electrode surface And a resin.

【0011】[0011]

【作用】本発明の樹脂封止方法では固体状の樹脂を簡易
な金型を用いて加熱圧縮成形するので、加熱により一時
的に粘度が下がり流動化した樹脂が、圧縮により回路基
板と充分に密着する。図8は従来のポッティングによる
封止と圧縮成形による封止とを、プレッシャークッカー
テスト(2気圧、121℃)での累積不良率で比較した
ものである。ポッティングによる封止は非圧縮成形のた
め密着性に劣り早期に不良が発生するのに対し、圧縮成
形による封止は密着性に優れ、信頼性が飛躍的に向上す
る。
In the resin sealing method of the present invention, the solid resin is heated and compression-molded by using a simple mold. Therefore, the resin whose viscosity is temporarily lowered by heating and becomes fluidized is sufficiently compressed with the circuit board. In close contact. FIG. 8 compares the conventional potting sealing and compression molding sealing in terms of cumulative defective rate in a pressure cooker test (2 atm, 121 ° C.). Sealing by potting is non-compression molding and has poor adhesion and causes defects early, whereas sealing by compression molding has excellent adhesion and dramatically improves reliability.

【0012】また前記金型はトランスファ成形金型に比
べ簡易なものでよいので、回路基板上のほぼ任意の位置
に圧縮成形によって半導体素子を樹脂封止することがで
きる。前記固体状の樹脂として熱可塑性樹脂や半硬化状
態の熱硬化性樹脂を用いれば、フィルム状として取り扱
えるので作業性が向上する。
Since the mold may be simpler than the transfer molding mold, the semiconductor element can be resin-sealed at almost any position on the circuit board by compression molding. When a thermoplastic resin or a semi-cured thermosetting resin is used as the solid resin, it can be handled as a film, so that workability is improved.

【0013】また半導体素子を回路基板にフェースダウ
ンで取り付け、両者の間に空気の逃げ道を作らない状態
で前記固体状樹脂の圧縮成形を行うと、回路基板と半導
体素子電極面との間への樹脂の侵入を防止できる。その
結果半導体素子が機械的な応力に弱い微細な電極面を有
する場合は、樹脂により電極面を傷めることがなくなり
信頼性が向上する。
If the semiconductor element is mounted face down on the circuit board and the solid resin is compression-molded in a state in which an air escape path is not formed between the two, a gap between the circuit board and the electrode surface of the semiconductor element is formed. The resin can be prevented from entering. As a result, when the semiconductor element has a fine electrode surface which is weak against mechanical stress, the electrode surface is not damaged by the resin, and the reliability is improved.

【0014】[0014]

【実施例】次に本発明の実施例を図を参照して説明す
る。図1〜図3は本発明の第1の実施例の製造工程を模
式的に示した断面図である。図1において1は半導体素
子でその表面にはAuのバンプ電極2が形成されてい
る。前記バンプ電極2は転写バンプ法やめっき法で形成
することができる。3は両面に銅箔で配線回路が形成さ
れたガラスエポキシ基材の回路基板である。回路基板と
しては他にセラミック基材に導電性ペーストの印刷によ
り回路を形成した厚膜基板や、蒸着等で回路を形成した
薄膜基板を使用することもできる。
Embodiments of the present invention will now be described with reference to the drawings. 1 to 3 are sectional views schematically showing the manufacturing process of the first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a semiconductor element, on the surface of which a bump electrode 2 of Au is formed. The bump electrode 2 can be formed by a transfer bump method or a plating method. Reference numeral 3 is a circuit board of a glass epoxy base material on which wiring circuits are formed of copper foil on both sides. As the circuit board, it is also possible to use a thick film board having a circuit formed by printing a conductive paste on a ceramic substrate or a thin film board having a circuit formed by vapor deposition or the like.

【0015】前記回路基板3の1主面の半導体素子1が
搭載される位置には、前記バンプ電極2に対応するリー
ド電極4が形設されており、表面はAuめっきされてい
る。さらにこのリード電極4の接続部を除いた部分はソ
ルダーレジスト5で覆われている。また前記回路基板3
の半導体素子1の直下にはガス抜きの為のベントホール
6が設けられている。前記バンプ電極2と前記リード電
極4は位置合わせ後当接され熱圧着で接合されている。
A lead electrode 4 corresponding to the bump electrode 2 is formed at a position where the semiconductor element 1 is mounted on one main surface of the circuit board 3, and the surface is plated with Au. Further, the portion excluding the connecting portion of the lead electrode 4 is covered with the solder resist 5. Also, the circuit board 3
A vent hole 6 for venting gas is provided immediately below the semiconductor element 1. The bump electrodes 2 and the lead electrodes 4 are brought into contact with each other after alignment and joined by thermocompression bonding.

【0016】次に図2は樹脂封止の工程を模式的に示し
た断面図で、半導体素子1が搭載された回路基板3はホ
ットプレート7の上に載置される。前記半導体素子1の
周囲にはこれを囲繞する固定金型8が載置され、図示し
ない固定具により固定される。前記固定金型8はクッシ
ョン性のあるソルダーレジスト5の上に載置されるの
で、回路基板3との密着性が良好に保たれる。
Next, FIG. 2 is a cross-sectional view schematically showing the resin sealing process, in which the circuit board 3 on which the semiconductor element 1 is mounted is placed on the hot plate 7. A fixed die 8 surrounding the semiconductor element 1 is placed around the semiconductor element 1 and fixed by a fixture (not shown). Since the fixed mold 8 is placed on the solder resist 5 having a cushioning property, good adhesion with the circuit board 3 is maintained.

【0017】次に固定金型8の開口部内に固体状の封止
樹脂9が投入される。この固体状の封止樹脂9としては
熱可塑性樹脂や半硬化状態(Bステージ)の熱硬化性樹
脂が使用でき、ポリフェニレンサルファイド樹脂、ポリ
サルフォン樹脂、ポリイミド樹脂、シリコーン樹脂、エ
ポキシ樹脂等が好ましい。
Next, the solid sealing resin 9 is put into the opening of the fixed mold 8. As the solid sealing resin 9, a thermoplastic resin or a thermosetting resin in a semi-cured state (B stage) can be used, and polyphenylene sulfide resin, polysulfone resin, polyimide resin, silicone resin, epoxy resin or the like is preferable.

【0018】Bステージ状態のエポキシ樹脂の場合は前
記ホットプレート7の温度を170ないし190℃に設
定して置くと、前記エポキシ樹脂は加熱されて溶融す
る。この封止樹脂9の上部には、前記固定金型8の開口
部に嵌合する可動金型10がセットされ所定の圧力(エ
ポキシ樹脂の場合8ないし10MPa)で前記封止樹脂
9を加圧する。この結果溶融状態になった封止樹脂9は
半導体素子1と回路基板3の隙間に侵入する。回路基板
3にはベントホール6が形成されているので、空気はこ
のベントホール6から排出されホットプレート7と回路
基板3の隙間に逃げる。その結果図3に断面的に示すよ
うに、樹脂9が空隔を埋め樹脂封止が完成する。
In the case of the epoxy resin in the B stage, if the temperature of the hot plate 7 is set to 170 to 190 ° C., the epoxy resin is heated and melted. A movable mold 10 that fits into the opening of the fixed mold 8 is set on the upper part of the sealing resin 9, and the sealing resin 9 is pressed with a predetermined pressure (8 to 10 MPa in the case of an epoxy resin). . As a result, the molten sealing resin 9 enters the gap between the semiconductor element 1 and the circuit board 3. Since the circuit board 3 has the vent hole 6, air is discharged from the vent hole 6 and escapes into the gap between the hot plate 7 and the circuit board 3. As a result, as shown in a sectional view in FIG. 3, the resin 9 fills the gap and the resin sealing is completed.

【0019】この樹脂封止の際使用する固定金型8の大
きさは、半導体素子1のチップサイズが15×15mm
程度の場合は外径40×40mm、内径20×20mm
程度であり、この領域には前記半導体素子1以外の表面
実装部品の搭載は禁止されるが、比較的小面積であり実
装上の制約よりも圧縮封止の効果の方が大きい。
The size of the fixed mold 8 used for this resin encapsulation is such that the chip size of the semiconductor element 1 is 15 × 15 mm.
In the case of about 40 x 40 mm outer diameter, 20 x 20 mm inner diameter
Although the surface mounting components other than the semiconductor element 1 are prohibited to be mounted in this region, the area is relatively small and the compression sealing effect is larger than the mounting restriction.

【0020】次に本発明の第2の実施例を図4を参照し
て説明する。図3は樹脂封止方法を説明した断面図であ
るが、基本的構成は図2と同様なので同一部分には同一
番号を付して説明は一部省略する。本実施例では回路基
板3’にベントホールが形成されておらず、半導体素子
1の表面(電極形成面)が封止樹脂9’によって被覆さ
れない中空モールド成形された状態を形成することがで
きる。半導体素子1が微細な電極面を有し、封止樹脂が
直接触れることにより半導体素子1へのダメージが予想
される場合等に有効な構成である。
Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a cross-sectional view for explaining the resin sealing method, but since the basic structure is the same as that of FIG. 2, the same parts are designated by the same reference numerals and the description thereof is partially omitted. In this embodiment, a vent hole is not formed in the circuit board 3 ', and the surface (electrode forming surface) of the semiconductor element 1 can be formed in a hollow mold in which it is not covered with the sealing resin 9'. This is an effective configuration when the semiconductor element 1 has a fine electrode surface and damage to the semiconductor element 1 due to direct contact with the sealing resin is expected.

【0021】接続された半導体素子1のバンプ2の高さ
が10μm、めっきが施された端子配線4の高さが32
μm、合計42μmの隙間が半導体素子1と回路基板3
の間にできるが、本発明の圧縮成形を行えば封止樹脂
9’が半導体素子1の各辺から均等に流れ、半導体素子
の表面側に滞留し中空成形が可能である。回路基板3の
表面に設けられた凹部11は、滞留した空気の溜まり場
として設けたものであり必ずしも必要なものではない。
The height of the bumps 2 of the connected semiconductor element 1 is 10 μm, and the height of the plated terminal wiring 4 is 32.
The gap of 42 μm in total is the semiconductor element 1 and the circuit board 3.
However, if the compression molding of the present invention is performed, the sealing resin 9'flows evenly from each side of the semiconductor element 1 and stays on the surface side of the semiconductor element to enable hollow molding. The concave portion 11 provided on the surface of the circuit board 3 is provided as a reservoir for the accumulated air and is not always necessary.

【0022】また樹脂の充填材の最大粒径、粒度分布を
調整することにより、上記の隙間からの樹脂の流入を防
ぐことができる。図5は充填材としてシリカを使用した
場合におけるシリカの最大粒径と流動可能クリアランス
の最小値の関係を示したもので、前記の例の42μmの
隙間の場合には55μm以上の充填材を含有させればよ
いことがわかる。
Further, by adjusting the maximum particle size and particle size distribution of the resin filler, it is possible to prevent the resin from flowing through the above-mentioned gap. FIG. 5 shows the relationship between the maximum particle size of silica and the minimum value of flowable clearance when silica is used as the filler. In the case of the gap of 42 μm in the above example, the filler contains 55 μm or more. I understand that I should do it.

【0023】また図6はシリカ体積分率(Vol%)と
成形収縮率、あるいはスパイラルフローとの関係を示し
ている。トランスファ成形の場合はスパイラルフローが
80cm以上必要であり、従ってシリカの含有は65V
ol%が限界であるが、本発明の圧縮成形の場合はスパ
イラルフローが80cm以下でも封止は可能であり、シ
リカを65Vol%以上含有させ、トランスファ成形よ
りも成形収縮を低減させることができる。
FIG. 6 shows the relationship between the silica volume fraction (Vol%) and the molding shrinkage or the spiral flow. In the case of transfer molding, a spiral flow of 80 cm or more is required, so the silica content is 65 V
Although the limit is ol%, in the case of the compression molding of the present invention, sealing is possible even with a spiral flow of 80 cm or less, and silica can be contained in an amount of 65 Vol% or more to reduce molding shrinkage as compared with transfer molding.

【0024】つぎに本発明の第3の実施例を図7に示
す。図7は樹脂封止が完了した状態を示す断面図であ
り、テープキャリアに接続された半導体素子を使用した
例である。図において半導体素子21に接続されサポー
トリング22に保持されたリード23は回路基板24の
1主面に形設された端子配線25に接続されている。2
6はソルダレジストである。27は封止樹脂であり、実
施例1と同様の方法で圧縮成形されている。28はベン
トホールでこの場合半導体素子21の下面がダイマウン
トのため使用できないので、ダイパッド29を避けた場
所に設けられている。 この様に半導体素子をフェース
アップで取り付けた場合にも本発明の封止方法を適用す
ることができる。半導体素子21の回路基板24への取
付け前に、半導体素子21のバーンインや特性検査を充
分に実施したい場合等には有効な実装方法である。半導
体素子21をフェースダウンで取り付けてもよく、中空
モールド成形にしてもよいことはいうまでもない。
Next, a third embodiment of the present invention is shown in FIG. FIG. 7 is a cross-sectional view showing a state where the resin sealing is completed, which is an example using a semiconductor element connected to a tape carrier. In the figure, the leads 23 connected to the semiconductor element 21 and held by the support ring 22 are connected to the terminal wirings 25 formed on one main surface of the circuit board 24. Two
6 is a solder resist. Reference numeral 27 denotes a sealing resin, which is compression molded by the same method as in the first embodiment. Reference numeral 28 is a vent hole, and in this case, since the lower surface of the semiconductor element 21 cannot be used because it is a die mount, it is provided at a place avoiding the die pad 29. In this way, the sealing method of the present invention can be applied even when the semiconductor element is mounted face up. This is an effective mounting method when it is desired to sufficiently carry out burn-in or characteristic inspection of the semiconductor element 21 before mounting the semiconductor element 21 on the circuit board 24. It goes without saying that the semiconductor element 21 may be attached face down or may be formed by hollow molding.

【0025】[0025]

【発明の効果】以上説明したように本発明の樹脂封止方
法は、圧縮成形によって樹脂封止されているため回路基
板との密着性に優れ、従来の液状樹脂によるポッティン
グ封止に比べすぐれた耐湿性が得られる。また簡易な金
型を使用するので回路基板上のほぼ任意の位置に圧縮成
形による樹脂封止が可能になる。
As described above, the resin encapsulation method of the present invention is excellent in adhesion to the circuit board because it is resin-encapsulated by compression molding, and is superior to conventional potting encapsulation with liquid resin. Moisture resistance can be obtained. Further, since a simple mold is used, resin molding by compression molding can be performed at almost any position on the circuit board.

【0026】また半導体素子の微細化が進むと、樹脂の
成形収縮によって発生する応力や冷熱サイクル等の熱応
力により半導体素子がダメージを受ける場合があるが、
本発明の中空モールドを採用すればこれらを回避するこ
とができる。
Further, as miniaturization of the semiconductor element progresses, the semiconductor element may be damaged by the stress generated by the molding shrinkage of the resin or the thermal stress such as the cooling / heating cycle.
These can be avoided by using the hollow mold of the present invention.

【0027】中空モールド成形に使用される封止材料
は、トランスファ成形に使用される材料に比べ流動性を
考慮する必要がなく、充填材の増量が容易である。従っ
て成形収縮を低減でき、放熱性をも向上できるので半導
体素子の発熱による劣化も低減できる。
The encapsulating material used for hollow molding does not need to take fluidity into consideration as compared with the material used for transfer molding, and the amount of the filler can be easily increased. Therefore, molding shrinkage can be reduced and heat dissipation can be improved, so that deterioration of the semiconductor element due to heat generation can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例に係わる半導体装置の回
路基板への接続状態を示す断面図。
FIG. 1 is a cross-sectional view showing a connection state of a semiconductor device according to a first embodiment of the present invention with a circuit board.

【図2】本発明の第1の実施例に係わる圧縮成形工程を
示す断面図。
FIG. 2 is a sectional view showing a compression molding step according to the first embodiment of the present invention.

【図3】本発明の第1の実施例に係わる樹脂封止が完了
した状態を示す断面図。
FIG. 3 is a cross-sectional view showing a state where resin sealing according to the first embodiment of the present invention is completed.

【図4】本発明の第2の実施例に係わる圧縮成形工程の
実施態様と、圧縮成形が完了し中空モールドが形成され
た状態を示す断面図。
FIG. 4 is a sectional view showing an embodiment of a compression molding process according to the second embodiment of the present invention and a state in which the compression molding is completed and a hollow mold is formed.

【図5】本発明の第2の実施例に係わる充填材最大粒径
と樹脂流動(入り込み)可能クリアランスとの関係を示
すグラフ。
FIG. 5 is a graph showing the relationship between the maximum particle size of the filler and the clearance through which resin can flow (enter) according to the second embodiment of the present invention.

【図6】本発明の第2の実施例に係わる充填材体積分率
と成形収縮率との関係を示すグラフ。
FIG. 6 is a graph showing the relationship between the filler volume fraction and the molding shrinkage rate according to the second example of the present invention.

【図7】本発明の第3の実施例に係わる樹脂封止が完了
した状態を示す断面図。
FIG. 7 is a sectional view showing a state in which resin sealing according to a third embodiment of the present invention is completed.

【図8】非圧縮成形(ポッティング)と圧縮成形のプレ
ッシャクッカーテストにおける累積不良率を比較したグ
ラフ。
FIG. 8 is a graph comparing the cumulative defective rate in the pressure cooker test of non-compression molding (potting) and compression molding.

【符号の説明】[Explanation of symbols]

1 … 半導体素子 2 … バンプ電極 3 … 回路基板 4 … 端子配線 5 … ソルダーレジスト 6 … ベントホール 7 … ホットプレート 8 … 固定金型 9 … 固体状樹脂 10 … 可動金型 1 ... Semiconductor element 2 ... Bump electrode 3 ... Circuit board 4 ... Terminal wiring 5 ... Solder resist 6 ... Vent hole 7 ... Hot plate 8 ... Fixed mold 9 ... Solid resin 10 ... Movable mold

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 回路基板に搭載された半導体素子の樹脂
封止方法において、前記半導体素子上に固体状樹脂を載
置する工程と、前記固体状樹脂を加熱圧縮成型する工程
とを具備することを特徴とする半導体素子の樹脂封止方
法。
1. A resin sealing method for a semiconductor element mounted on a circuit board, comprising: a step of placing a solid resin on the semiconductor element; and a step of heat compression molding the solid resin. A resin encapsulation method for a semiconductor element, comprising:
【請求項2】 前記半導体素子がフェースダウンで実装
され、その電極面が前記固体状樹脂で被覆されないこと
を特徴とする請求項1記載の半導体素子の樹脂封止方
法。
2. The resin encapsulating method for a semiconductor element according to claim 1, wherein the semiconductor element is mounted face down and the electrode surface thereof is not covered with the solid resin.
【請求項3】 配線回路が形成された回路基板と、この
回路基板にフェースダウンで実装された半導体素子と、
この半導体素子をその電極面を除いて被覆する封止樹脂
とを具備することを特徴とする樹脂封止型半導体装置。
3. A circuit board on which a wiring circuit is formed, and a semiconductor element mounted face down on the circuit board,
A resin-encapsulated semiconductor device, comprising: a sealing resin that covers the semiconductor element excluding its electrode surface.
JP1565894A 1994-02-10 1994-02-10 Method of sealing semiconductor device, and resin-sealed semiconductor device Pending JPH07226414A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1565894A JPH07226414A (en) 1994-02-10 1994-02-10 Method of sealing semiconductor device, and resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1565894A JPH07226414A (en) 1994-02-10 1994-02-10 Method of sealing semiconductor device, and resin-sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPH07226414A true JPH07226414A (en) 1995-08-22

Family

ID=11894841

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1565894A Pending JPH07226414A (en) 1994-02-10 1994-02-10 Method of sealing semiconductor device, and resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPH07226414A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1190448A4 (en) * 1999-05-14 2004-11-24 Hestia Technologies Inc Chip package with molded underfill
JP2013232580A (en) * 2012-05-01 2013-11-14 Dow Corning Toray Co Ltd Thermosetting film-like silicone sealing material
WO2014208044A1 (en) * 2013-06-28 2014-12-31 株式会社デンソー Electronic device and method for manufacturing said electronic device
WO2016006392A1 (en) * 2014-07-09 2016-01-14 株式会社村田製作所 Electronic component-embedded module

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1190448A4 (en) * 1999-05-14 2004-11-24 Hestia Technologies Inc Chip package with molded underfill
JP2013232580A (en) * 2012-05-01 2013-11-14 Dow Corning Toray Co Ltd Thermosetting film-like silicone sealing material
WO2014208044A1 (en) * 2013-06-28 2014-12-31 株式会社デンソー Electronic device and method for manufacturing said electronic device
JP2015009466A (en) * 2013-06-28 2015-01-19 株式会社デンソー Electronic device and method for manufacturing electronic device
US20160183405A1 (en) * 2013-06-28 2016-06-23 Denso Corporation Electronic device and method for manufacturing the electronic device
US9795053B2 (en) 2013-06-28 2017-10-17 Denso Corporation Electronic device and method for manufacturing the electronic device
WO2016006392A1 (en) * 2014-07-09 2016-01-14 株式会社村田製作所 Electronic component-embedded module
US10707403B2 (en) 2014-07-09 2020-07-07 Murata Manufacturing Co., Ltd. Electronic component-containing module

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