JPH07226392A - Semiconductor substance subjected to electrochemical etching - Google Patents

Abstract

PURPOSE:To provide a semiconductor substrate which is subjected to electrochemical etching by which especially a small thickness part is processed with a high precision. CONSTITUTION:An N-type semiconductor layer 13 is formed on the surface of a P-type semiconductor wafer 12 to form a semiconductor substrate 11. A separation belt 15 is formed in the semiconductor layer 13 so as to mark off a chip arranging region 14 from an outer circumferential region 141 surrounding the region 14. The separation belt 15 is formed by filling a trench which is formed so as to reach the surface of the P-type semiconductor wafer 12 from the surface of the semiconductor layer 13 by etching with dielectric material. That is, the outer circumferential region 14 in which current leakage generating parts 19 such as defective parts of P-N junctions exist is electrically separated from the chip arranging region 14 by the separation belt 15 and the generation of leakage currents from P-N junctions in the chip arranging region 14 can be avoided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate which is subjected to electrochemical etching in the manufacturing process of a semiconductor device so that a thin portion such as a pressure sensor or an acceleration sensor can be etched with high accuracy.

[0002]

2. Description of the Related Art In forming a pressure sensor, an acceleration sensor or the like using a semiconductor substrate, for example, Japanese Patent Laid-Open No. 63-29 is known.
As shown in Japanese Patent No. 2071, the use of electrochemical etching has been extensively studied for the purpose of improving the processing accuracy of the thin portion. Specifically, P
An n-type semiconductor layer is formed on the surface of the semiconductor wafer of the type by epitaxial growth, and a PN junction is formed as an etching stop region between the semiconductor wafer and the semiconductor layer. Then, etching is performed in a state where a voltage is set between the semiconductor wafer and the semiconductor layer, and the etching is stopped while leaving a desired thin portion. In such an etching process, in order to obtain a uniform thickness in the plane of the semiconductor wafer, it is necessary to apply a voltage uniformly to the etched portion.

However, even if a voltage is applied to a semiconductor wafer having a PN junction of a semiconductor layer formed by epitaxial growth or the like, it is difficult to supply and set a uniform voltage over the entire surface of the wafer. That is, in a semiconductor substrate having a PN junction formed in this manner, if there is a defective portion of the junction or an exposed portion of the junction, a current leaks at the junction at this portion. As a result, the voltage on the entire surface of the wafer cannot be made constant.

Unlike the central portion of the peripheral edge of the semiconductor wafer, normal epitaxial growth is likely to be impaired, and the PN junction is exposed at the outer peripheral edge.
Therefore, P in the outer peripheral edge portion of the semiconductor wafer
Many current leaks occur at the N-junction.

[0005]

The present invention has been made in view of the above points, and in particular, the influence of voltage fluctuation on the processing region due to current leakage from the PN junction at the outer peripheral edge of the semiconductor wafer is certain. Electrochemical etching that suppresses the etching, and performs etching with a uniform voltage applied to the entire surface of the semiconductor wafer that is the object to be etched, in particular, with a high degree of accuracy in etching the thin portion. It is intended to provide a semiconductor substrate in which

[0006]

A semiconductor substrate to be subjected to electrochemical etching according to the present invention is provided on a surface portion of a semiconductor wafer of a first conductivity type with a PN between the surface and the semiconductor wafer.
A second conductivity type semiconductor layer formed so as to form a bond is formed, and a separation band is formed so as to surround the outer periphery of the processed region of the semiconductor layer and reach the surface of the semiconductor wafer. An insulating isolation region is formed outside the processed region of the layer and electrically isolated from the processed region. Here, the separation band is formed of a dielectric separation layer in which a dielectric material is embedded in a groove formed to reach the surface of the semiconductor wafer, or a P ⁺ diffusion layer.

[0007]

In the semiconductor substrate having such a structure, for example, a semiconductor layer in which a semiconductor layer formed by n-type epitaxial growth is formed on the surface of a P-type semiconductor wafer and a PN junction is formed between them is used. It In this semiconductor substrate, an insulating isolation region electrically isolated by the isolation band is formed particularly in the peripheral portion of the semiconductor layer where current leakage is likely to occur in the junction portion, and therefore the PN in this insulating isolation region is formed. Even if there is a portion where a current leak may occur in the junction, this insulation isolation region is only made to have the same potential as the semiconductor wafer portion, and a current leak occurs between the semiconductor wafer in the processing region where the chip etc. are formed. Is suppressed. That is, the substrate voltage is applied and set uniformly in the region where the etching process needs to be performed, so that the electrochemical etching can be performed with high accuracy.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 11 denotes a semiconductor substrate on which a large number of semiconductor chips are arranged and formed, or various sensor mechanisms are processed. The semiconductor substrate 11 is mainly composed of a semiconductor wafer 12 made of, for example, P-type silicon. And
An n-type semiconductor layer 13 is formed on the surface of the semiconductor wafer 12 by, for example, epitaxial growth, and a PN junction is formed over the entire surface between the semiconductor layer 13 and the semiconductor wafer 11.

In the semiconductor substrate 11 thus constructed, for example, an array region 14 of semiconductor chips is set while leaving the peripheral portion thereof. A separation band 15 is formed so as to surround the periphery of the chip array region 14. Is formed. This separator 15
For example, R. I. E. To the n-type semiconductor layer 13 by P
A groove reaching the surface of the semiconductor wafer 12 of the mold is formed by etching, and a dielectric substance such as SiO ₂ or SiN is formed inside the groove.
Alternatively, it is composed of a dielectric isolation layer formed by burying polycrystalline silicon together with these dielectric materials.

An n ⁺ type diffusion layer for forming an ohmic electrode is formed on the surface of the n type semiconductor layer 13 in the chip array region 14.
16 is formed, and the electrode 17 is formed on the surface of the diffusion layer 16.
A DC power supply 18 is connected between the electrode 17 and the P-type semiconductor wafer 12.

In the semiconductor substrate 11 composed of the P-type semiconductor wafer 12 and the n-type semiconductor layer 13 as described above, a separation band is formed.
If there is not 15, the leak generating part 19 corresponding to the outer peripheral edge part
In this case, a large amount of current leakage may occur. However, the outer peripheral part of the n-type semiconductor layer 13 including the leak generating part 19 becomes an outer peripheral region 141 electrically insulated from the central chip array region 14 by the separation band 15, and the leak generating part 19 is formed.
Even if a current leak may occur between the outer peripheral region 141 and the P-type semiconductor wafer 12, the outer peripheral region 141
Is only made to have the same potential as the P-type semiconductor wafer 12. Therefore, current leakage is effectively suppressed between the chip array region 14 of the n-type semiconductor layer 13 and the P-type semiconductor wafer that are electrically separated by the separation band 15.

The separation band 15 formed by the dielectric layer is
The n-type semiconductor layer 13 formed on the surface of the semiconductor wafer 12, particularly on the surface thereof, is formed so as to surround the outer periphery of a so-called effective area slightly inside the outermost periphery of the semiconductor wafer 12.
Is formed so as to separate the inside and the outside. This n
Although a PN junction is formed between the type semiconductor layer 13 and the P-type semiconductor wafer 12, if there is a defective joint portion or a portion where the junction is exposed, current leakage occurs at that portion. The outer peripheral portion of the semiconductor wafer 12 is different from the central portion in that normal epitaxial growth is likely to be impaired, and the PN junction portion is exposed. For reasons such as easy
There is a defective joint site or the like that induces current leakage.

The peripheral region 141 of the semiconductor layer 13 which is highly likely to induce such a current leakage is separated by the separation band 15 made of, for example, a dielectric material, into the chip arrangement region 14
Is electrically insulated and separated from each other, the leakage of current from the PN junction in the central chip array region 14 which is important in the manufacturing process of the semiconductor device is surely suppressed. Therefore, when the DC power supply 18 is connected between the P-type semiconductor wafer 12 and the n-type semiconductor layer 13 during the electrochemical etching, a uniform voltage is applied and set to the entire surface of the semiconductor wafer 12, Effective electrochemical etching can be performed, and a pressure sensor and an acceleration sensor can be easily and highly accurately manufactured by processing a semiconductor, for example.

When performing the electrochemical etching on the semiconductor substrate 11 thus constructed, a mask film 20 made of, for example, SiN is formed on the back surface of the P-type semiconductor wafer 12, and a voltage is applied by a power source 18. Then, a predetermined etching operation is performed. In this case, current leakage mainly occurs in the outer peripheral region 141 electrically separated from the chip arrangement region 14 by the separation band 15, so that the current leakage in the chip arrangement region 14 which is important in the manufacture of the semiconductor device is prevented. This is surely prevented, and a uniform voltage is applied and set over the entire area. Therefore, the mask film 20
Although the semiconductor wafer 12 is etched corresponding to the opening 21 of the above, the thin-wall processing is executed with high accuracy at this etching site, and it becomes easy to process various sensor mechanisms and the like with high accuracy.

In the above embodiment, the isolation band 15 has a trench structure made of, for example, a dielectric material, but as shown in FIG. 2, the entire outer peripheral portion of the n-type semiconductor layer 13 is covered with the dielectric isolation layer 151.
It may be configured by. According to this structure, the PN junction portion is covered with the dielectric isolation layer 151 at all the portions where the leakage of current is likely to occur, and this portion is electrically assured from the chip forming region in the central portion of the n-type semiconductor layer 13. Be divided. Therefore, the same effect as that of the above embodiment can be expected.

Such a structure can be formed by means such as filling the dielectric material after removing the outer peripheral area surrounding the chip arrangement area of the n-type semiconductor layer 13 by etching or the like. May be configured in the form of a film.

Further, as shown in FIG. 3, a concave groove 23 reaching the surface of the P-type semiconductor wafer 12 is formed along the boundary line between the chip array area 14 and the outer peripheral area 141 in FIG.
By forming a dielectric film 24 on the inner surface of
Can also be formed.

In the above-described embodiments, the separation band 15 that electrically separates the chip array region 14 and the outer peripheral region 141 of the n-type semiconductor layer 13 from each other is formed by a buried structure of a dielectric material such as SiN. Explained. However, this separator 15 is shown in FIG.
Alternatively, a P ⁺ diffusion layer may be used in the same structure as shown in FIG.

[0019]

As described above, according to the semiconductor substrate in which the electrochemical etching according to the present invention is performed, the n-type semiconductor layer is formed on the surface of the P-type semiconductor substrate by epitaxial growth and the PN junction is set on the entire surface. In this case, when the voltage is applied and set in this electrochemical etching, the outer peripheral region in which the leakage of current is likely to occur is electrically separated from the central chip array region which is important in manufacturing the semiconductor device. In particular, thin-wall processing and the like can be performed with high accuracy.

[Brief description of drawings]

1A and 1B show a semiconductor substrate according to an embodiment of the present invention, in which FIG. 1A is a plan view and FIG. 1B is a cross-sectional view corresponding to line bb in FIG.

FIG. 2 is a sectional view showing a second embodiment of the present invention.

FIG. 3 is a sectional view showing a third embodiment of the present invention.

[Explanation of symbols]

11 ... Semiconductor substrate, 12 ... P-type semiconductor wafer, 13 ... N-type semiconductor layer, 14 ... Chip array region, 141 ... Peripheral region, 15 ... Separation band, 151, Dielectric isolation layer, 16 ... N ⁺ diffusion layer, 17 …electrode,
18 ... DC power supply, 19 ... Leakage generating part, 20 ... Mask film, 21 ...
Aperture.

Claims (4)

[Claims] 1. A semiconductor wafer of a first conductivity type, and a semiconductor layer of a second conductivity type formed on a surface portion of the semiconductor wafer so that a PN junction is formed between the semiconductor wafer and the semiconductor wafer. A separation band that is formed so as to surround the outer periphery of the processed region of the semiconductor layer and reach the surface of the semiconductor wafer, and that forms an insulating separation region electrically separated from this region outside the processed region of the semiconductor layer. A semiconductor substrate for electrochemical etching, comprising a voltage applied between the semiconductor wafer and the semiconductor layer to perform electrochemical etching. 2. The electrochemical etching according to claim 1, wherein the separation band is formed of a dielectric separation layer in which a dielectric material is embedded in a groove formed to reach the surface of the semiconductor wafer. Semiconductor substrate. 3. The semiconductor substrate according to claim 1, wherein the insulating isolation region is entirely made of a dielectric material. 4. The first conductivity type is P and the second conductivity type is n, and the separation band is formed in the n-type semiconductor layer to reach the surface of the P-type semiconductor wafer. The P ⁺ diffusion layer embedded in the groove is formed.
A semiconductor substrate on which the described electrochemical etching is performed.