JPH07211730A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To enable the gate recess of a FET to be formed in excellent controllability as well as high functional electronic circuit to be made by a method wherein the first semiconductor layer is composed of a material in notably slower etching rate using a specific etchant than that of the second semiconductor layer. CONSTITUTION:Within the semiconductor device composed of the first semiconductor layer 9 laminated on a semiconductor substrate 1, the second semiconductor layer 10 in contact with the first semiconductor layer 9, the third semiconductor layer 11 laminated on the second semiconductor layer 10, an aperture part having a control electrode 23 in contact with the first semiconductor layer 9 formed on a part of the second semiconductor layer 10 and the third semiconductor layer 11, the first semiconductor layer 9 is to be composed of a material in notably slower etching rate using a specific etchant than that of the second semiconductor layer 10. For example, the first, second and third semiconductor layers 9, 10, 11 are respectively composed of an undoped GaAs stopper layer 9, an n-AlGaAs layer 10 and an n-GaAs cap layer 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor in which the amount of current is controlled by a voltage applied to a control electrode on the surface of a semiconductor, and more particularly to a semiconductor device which has excellent uniformity in device characteristics and is easy to manufacture. And its manufacturing method.

[0002]

2. Description of the Related Art There is a structure of FET (Field Effect Transistor), which is a recess gate structure, that is, a recess (groove) is provided in a part of a semiconductor surface and a gate electrode is formed in the recess. The structure and manufacturing method are disclosed in, for example, Japanese Patent Laid-Open No. 63-60570 as shown in FIG. Further, as a method of low damage etching, there is, for example, JP-A-5-82490.

[0003]

In an integrated circuit using semiconductor elements, it is important to use active elements having good element characteristics. However, variations in element characteristics only lead to difficulties in circuit design. Therefore, the yield is reduced and the cost is increased. The selective dry etching used in the conventional example is a suitable method as a gate processing method because it has excellent workability, low damage, and good uniformity. However, if the distance between the gate and the channel is further shortened in order to improve the device characteristics, damage to the channel becomes a problem even if dry etching, which has relatively low damage, is used. On the other hand, although the gate recess can be formed by using wet etching which has no damage at all, the reproducibility of the processing dimension was poor.

In the case of dry etching with extremely low damage as in the conventional example, the etching rate is usually several tens to 100 nm / hour, and it takes an extremely long time to perform etching of several hundred nm. And it was uneconomical.

A first object of the present invention is to provide a semiconductor device capable of forming a gate recess of an FET with good controllability and a manufacturing method thereof, and a second object thereof is to provide a high performance electronic circuit. .

[0006]

The first object is to provide a first semiconductor layer laminated on a semiconductor substrate, a second semiconductor layer in contact with the first semiconductor layer, and a second semiconductor layer. A control electrode having a third semiconductor layer laminated on the layer, having an opening in a part of the second semiconductor layer and the third semiconductor layer, and in contact with the first semiconductor layer in the opening. In the semiconductor device having, the etching rate of the first semiconductor layer with respect to a specific etching solution is achieved by using a material that is significantly slower than the second semiconductor layer. Further, in order to improve the processing accuracy, after the third semiconductor layer is removed by etching by selective dry etching,
This can be achieved by removing the second semiconductor layer by wet etching or dry etching with less damage than dry etching of the third semiconductor layer.
The second object can be achieved by constructing a circuit using the FET having such a structure.

[0007]

[Function] As a method of low damage selective dry etching,
There is RIE (Reactive Ion Etching). This RIE is
By exposing the semiconductor surface to an atmosphere in which a mixed gas of SiCl ₄ and SF ₆ is ionized in plasma in a depressurized container, Ga fluorides and chlorides are formed,
Etching is achieved by evaporation of this compound. For example, in the case of Al in AlGaAs, since the vapor pressures of fluorides and chlorides are different from Ga, these compounds cover the surface without evaporating, and thus etching stops, so that selectivity occurs. Al composition of 0.25 under normal conditions
The selection ratio of AlGaAs and GaAs is about 2000, which is a large value. The difference between the RIE mask size and the finished recess width can be controlled by the RIE etching time. This is realized because the side etching amount is about 0.2 μm / min under normal conditions.

On the other hand, in the case of the structure of the conventional example of FIG.
When the distance between the gate electrode and the channel is small, the transport property of the channel may be deteriorated even if the low damage RIE is used. FIG. 3 shows the distance dependence between the gate and the channel of the change in electron mobility before and after RIE.
As shown in the figure, the mobility change is not observed in the region of 25 nm or more, but it is significantly reduced below this. It has been experimentally found that such a change in mobility is not so dependent on etching conditions, although there is some variation. Therefore, in the conventional structure, the distance between the gate and the channel could not be 25 nm or less. From this, in RIE, the distance from the etching stop surface to the channel needs to be 25 nm or more.

In addition, δ-doping may be used in order to increase the concentration as the distance between the gate and the channel is shortened in order to improve the device characteristics. This has a structure in which ionized impurities are confined in the monoatomic layer, which is advantageous for improving the performance of the device. However, it is shown in FIG. 4 that this δ-doped is also unstable to RIE. This represents the activation rate of ionized impurities with respect to the distance from the surface to the δ-doped layer. As shown in the figure, a decrease in the activation rate is observed in the region of about 25 nm or less. From this, in RIE, the distance from the etching stop surface to the δ-doped layer needs to be 25 nm or more. Usually, in order to secure the breakdown voltage of the device, an undoped or low-concentration doped layer of 10 nm or more is interposed between the gate electrode surface and the carrier supply layer. Therefore, the distance from the etching stop surface to the gate electrode-semiconductor interface is It is understood that 15 nm or more, which is obtained by subtracting 10 nm, is required.

Further, the compound semiconductor in which the As atom of V group is replaced by P is a normal GaAs / AlGaAs / InGa
It is stable against etching solutions such as phosphoric acid and hydrofluoric acid, which are used for etching As, and these layers 1 to 3
By using a stopper of about nm, GaAs / AlG
Selective wet etching can be performed between aAs / InGaAs. With such a thickness, the Schottky characteristic of the gate is not significantly deteriorated. Since P can be easily formed by the gas source MBE or MOCVD, it does not significantly change the existing process. However, when a deep recess structure is used, it is difficult to secure controllability of side etching.
The variation in parasitic capacitance increases.

Further, dry etching as represented by the conventional photoexcited dry etching is one in which chloride or fluoride is formed on the surface by ionizing etching species by light or the like, and this evaporation is utilized. Since it does not use plasma unlike RIE, it is a method with relatively low damage. But,
Since such low damage dry etching has an extremely low etching rate, it takes an extremely long etching time to be applied to an element having a deep recess structure, and is not practical. Therefore, an element can be efficiently formed by performing dry etching to such an extent that damage by RIE does not cause a problem, and further by removing the remaining tens of nm by low damage dry etching.

As in the present invention, in order to prevent the etching damage from becoming a problem, the deep recess is formed by selective dry etching leaving about 15 nm, and the remaining 15 n is formed.
By performing wet etching for about m, such problems of damage and controllability can be solved at the same time. Further, the upper limit of the thickness is determined by the controllability of side etching. In order to avoid uneven etching, an etching time about twice the thickness up to the etching stop layer is required, and side etching by this is
If the thickness that does not significantly change the original side etching amount of about 200 nm is 50 nm or less, the variation of the side etching amount is about the same as the variation of RIE, which is not a serious problem. As a result, variations in element characteristics are extremely small, which facilitates circuit design. Such an element has a great effect when used in a low noise amplifier circuit, a mixer circuit, a logic circuit, a memory circuit, or the like.

[0013]

An embodiment of the present invention will be described below with reference to the drawings. After that, as a material description, AlGaAs is GaAs
In which some of the Ga atoms in the film are replaced with Al, In
GaAs means one in which some of the Ga atoms in GaAs are replaced with In.

(Embodiment 1) FIG. 5 shows a sectional view of an embodiment of the present invention. First, on a semi-insulating GaAs substrate 1, an undoped GaAs (thickness: 500 nm) 2, by an MBE (Molecular Beam Epitaxy) device that can use a gas source.
Undoped InGaAs channel layer (In composition 0.2
5, 8 nm) 3, undoped AlGaAs spacer layer (A
l composition 0.25, 2 nm) 4, n-AlGaAs carrier supply layer (Al composition 0.25, 5 nm, Si concentration: 2 ×
10 ¹⁸ / cm ³ ) 5, Si-δ doped layer (Si concentration: 5 x
10 ¹² / cm ² ) 6, n-AlGaAs carrier supply layer (Al composition 0.25, 5 nm, Si concentration: 2 × 10 ¹⁸ / c
m ³ ) 7, undoped AlGaAs layer (Al composition 0.2
5, 10 nm) 8, undoped GaAsP stopper layer 9, n-AlGaAs layer (Al composition 0.25, 15n)
m, Si concentration: 5 × 10 ¹⁸ / cm ³ ) 10 was grown, and finally the n-GaAs cap layer (Si concentration: 5 × 10 ¹⁸ / cm ³ ).
cm ³ , 160 nm) 11 is deposited.

After element isolation is performed by mesa etching, an insulating film is deposited and holes for the source electrode 21 and the drain electrode 22 are formed by a normal photolithography process. The insulating film on the surface of the hole is removed by dry etching, and the n-GaAs cap layer 11 is opened by wet etching to a thickness of about 40 nm. Furthermore, the insulating film is side-etched by wet etching to form a shape that facilitates lift-off. AuZn / Mo / Au is vapor-deposited on this, and heat treatment (400 ° C., 5 minutes) is performed in a nitrogen atmosphere. Further, a gate pattern is formed by using an EB (electron beam) drawing method.

Next, after dry etching the insulating film as shown in FIG. 6A, RIE is performed as shown in FIG.
Then, the n-GaAs layer 11 is opened. This RIE
Was performed using a mixed gas of SiCl ₄ and SF ₆ , each flow rate of 15 / 7.5 sccm, and RF power of 50 W.

Next, as shown in FIG. 7A, the n-AlGaAs layer 10 was removed by etching to the interface of the undoped GaAsP layer 9 with good controllability by phosphoric acid wet etching. Further, Al was vapor deposited and then lifted off to form the gate electrode 23 as shown in FIG. 7B.
In this way, the FET having the structure shown in FIG. 5 was realized.

In this HEMT, when the gate length is 0.35 μm, the threshold voltage = −1.0 V, the deviation σ = 28 mV of the variation of the threshold voltage in the plane of a 3-inch wafer,
The result was extremely good.

(Second Embodiment) Another embodiment of the present invention will be described with reference to FIGS. 5 to 7 as in the first embodiment. First, on the semi-insulating GaAs substrate 1, a gas source M can be used.
Undoped G by BE (Molecular Beam Epitaxy) equipment
aAs (thickness: 500 nm) 2, undoped InGaA
s channel layer (In composition 0.25, 8 nm) 3, undoped AlGaAs spacer layer (Al composition 0.25, 2 nm) 4,
n-AlGaAs carrier supply layer (Al composition 0.25,
5 nm, Si concentration: 2 × 10 ¹⁸ / cm ³ ) 5, Si-δ doped layer (Si concentration: 5 × 10 ¹² / cm ² ) 6, n-AlGa
As carrier supply layer (Al composition 0.25, 5 nm, Si
Concentration: 2 × 10 ¹⁸ / cm ³ ) 7, undoped AlGaAs layer (A
l composition 0.25, 10 nm) 8, undoped GaAsP
Stopper layer 9, n-AlGaAs layer (Al composition 0.2
5, 15 nm, Si concentration: 5 × 10 ¹⁸ / cm ³ ) 10 was grown, and finally the n-GaAs cap layer (Si concentration: 5)
X10 ¹⁸ / cm ³ , 160 nm) 11 is deposited.

After separating the elements by mesa etching, an insulating film is deposited and holes for the source electrode 21 and the drain electrode 22 are formed by a normal photolithography process. The insulating film on the surface of the hole is removed by dry etching, and the n-GaAs cap layer 11 is opened by wet etching to a thickness of about 40 nm. Furthermore, the insulating film is side-etched by wet etching to form a shape that facilitates lift-off. AuZn / Mo / Au is vapor-deposited on this, and heat treatment (400 ° C., 5 minutes) is performed in a nitrogen atmosphere. Further, a gate pattern is formed by using an EB (electron beam) drawing method. Next, after dry etching the insulating film as shown in FIG. 6A, RIE is performed as shown in FIG.
Then, the n-GaAs layer 11 is opened. This RIE
Is a mixed gas of SiCl ₄ and SF ₆ , and the flow rate is 15 / 7.5 sccm and the RF power is 50 W.
Next, as shown in FIG. 7A, the n-AlGaAs layer 10 is undoped G with good controllability by photoexcited dry etching.
The interface of the aAsP layer 9 was removed by etching. Furthermore A
(b) of FIG. 7 by performing lift-off after depositing l.
Thus, the gate electrode 23 was formed. In this way
An FET having the structure shown in FIG. 5 was realized.

This HEMT has a threshold voltage of 0.35 μm, a threshold voltage of −1.0 V, and a deviation σ of the threshold voltage variation in the plane of a 3-inch wafer σ = 31 mV.
The result was extremely good.

In the first and second embodiments, the conditions may be changed as follows.

In this embodiment, AlG is used as the etching layer.
Although aAs and GaAsP are used as the stopper layer, the combination is not limited to this, and any material having selectivity can be used. n-
The AlGaAs layer 10 and the n-GaAs layer 11 can be made of the same material or a material having low selectivity for RIE. This time is achieved by providing another layer having a lower RIE etching rate than that of the layer 11 between the layer 10 and the layer 11 so that the selectivity by the RIE can be obtained.

Further, in Example 2, photoexcitation etching was used as a low damage dry etching method.
Other low damage dry etching such as electron beam excitation etching may be used. Further, by making the low-damage dry etching anisotropic, that is, by making it difficult for side etching to occur, the semiconductor layer 2, here, n-Al is used.
An element having a small parasitic resistance and a low threshold voltage is formed by forming an opening in the GaAs layer 10 having almost the same size as an opening formed by a resist or an insulating film and forming a structure in which the gate electrode covers the opening. You can also do it.

In the epitaxial crystal growth in the manufacturing process, the same result can be obtained by using an apparatus that can control the growth in atomic layer units instead of MBE shown here, such as MOCVD. In addition, the n-AlGaAs layer 10 is not limited to this, and a material that easily forms ohmic contact, such as InGaAs, may be used. The undoped AlGaAs layer 8 immediately below the gate has an n-AlGaA density of 1 × 10 ¹⁸ / cm ² or less to the extent that the breakdown voltage is not reduced.
s may be used. The buffer layer 3 may be omitted, but the operation in a region where the drain current is small affects the transconductance and the short channel effect becomes remarkable. Also, if the Al composition is too small, the pinch-off characteristics deteriorate, and if it is too large, the crystallinity deteriorates.
Al composition 0.2 to 0.5, thickness 5 nm to 100 nm
In the range of, good results are shown.

In the embodiment, 0.25 was used as the Al composition of the AlGaAs layer, but similar results can be obtained even if a value of about 0.15 to 0.4 is used. The channel layer is I
Although InGaAs having an n composition of 0.25 is used, an In composition of about 0.2 to 0.6 may be used, and the thickness may be such that dislocations do not enter. The material is not limited to InGaAs, but a material having a large diffusion, such as I
It is also effective to stack a GaAs layer on InGaAs in the nGaAs / InAlAs system. Also, the substrate material is GaA
Not limited to s, InP or the like may be used.

In the embodiment, an example of an N-channel field effect transistor is shown, but good results can be obtained with a P-channel. In this case, this is achieved by making the N-doped layer of this embodiment a P-doped layer.

Although the present embodiment has been described with respect to the HEMT, good results can be obtained even when applied to another heterojunction element, that is, MESFET or the like.

(Embodiment 3) FIG. 8 shows a circuit diagram of a mixer according to an embodiment of the present invention. The HEMT described in the first embodiment is formed on a semiconductor substrate together with a matching circuit using a capacitor 210, an inductor 211, and a resistor 212. In the example of FIG. 8, the gate width 60 of the first HEMT 200 (mixer section)
0 μm, drain current 0.5 mA, next-stage HEMT2
When the drain current of 01 (IF amplifier part) was 3 mA, the conversion gain of the mixer at a frequency of 1.5 GHz was 17.5 dB at a local level of 0 dBm, which was a good value. In addition, the maximum input / output VSWR error was 5%, and the in-plane yield defined by a gain of 15 dB or more was 92%.

Although the example of the local drive type mixer is shown in the present embodiment, good results can be obtained even if a circuit type such as a double balance type or a single balance type is used. Although the lumped constant element was used for the matching circuit, good results were obtained even if a distributed constant element such as a microstrip line was used. In the present embodiment, an example of a so-called monolithic IC in which the matching circuit is on the same substrate as the active element is shown, but good results can be obtained even if the hybrid IC, that is, the matching circuit is not on the same substrate. Also, although the mixer having a frequency band of 1.5 GHz is described, good characteristics were obtained in other frequency bands by changing the matching circuit. Further, although the mixer has been described in the present embodiment, even when it is applied to another nonlinear circuit, for example, a high output amplifier or the like, a better result can be obtained as compared with the case where the conventional model is used.

[0031]

According to the present invention, an element having uniform characteristics can be manufactured by simply changing the crystal structure and the process. By using this element, the circuit design is facilitated and the yield is improved. To do.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device showing an embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor device showing a conventional example.

FIG. 3 is an explanatory diagram of a damage penetration depth by RIE.

FIG. 4 is an explanatory diagram of inactivation of δ-doped by RIE.

FIG. 5 is a sectional view of a semiconductor device showing an embodiment of the present invention.

FIG. 6 is an explanatory view showing a manufacturing process of an example of the present invention.

FIG. 7 is an explanatory diagram showing a manufacturing process of an example of the present invention.

FIG. 8 is a circuit diagram of a HEMT mixer showing an embodiment of the present invention.

[Explanation of symbols]

1 ... Semi-insulating GaAs substrate, 2 ... Undoped GaAs buffer layer, 3 ... Undoped InGaAs channel layer,
4 ... Undoped AlGaAs spacer layer, 5 ... n-Al
GaAs carrier supply layer, 6 ... Si-δ doped layer, 7 ...
n-AlGaAs carrier supply layer, 8 ... Undoped AlGaA
s barrier layer, 9 ... Undoped GaAsP etching stopper layer, 10 ... n-AlGaAs layer, 11 ... n-GaA
s cap layer, 21 ... Source electrode, 22 ... Drain electrode, 23 ... Gate electrode.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 29/778 H01L 21/306 S 9171-4M 29/80 H (72) Inventor Katsuhiko Higuchi Tokyo 1-280, Higashi Koigokubo, Kokubunji City, Central Research Laboratory, Hitachi, Ltd.

Claims (8)

[Claims] 1. A first semiconductor layer laminated on a semiconductor substrate, a second semiconductor layer in contact with the first semiconductor layer, and a third semiconductor layer laminated on the second semiconductor layer. A semiconductor device having an opening in a part of the second semiconductor layer and a part of the third semiconductor layer, and having a control electrode in contact with the first semiconductor layer in the opening. 2. A semiconductor device characterized in that the semiconductor layer is made of a material having an etching rate remarkably slower than that of the second semiconductor layer with respect to a specific etching solution. 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed by a heterojunction made of a plurality of single crystal semiconductor layers. 3. The semiconductor device according to claim 1, wherein the second semiconductor layer is GaAs, and the third semiconductor layer is GaAs.
aAs is a compound semiconductor in which a part of Ga atoms is substituted with In or Al atoms, and the first semiconductor layer is Ga.
A semiconductor device formed of a compound semiconductor in which a part of As atoms of As is substituted with P atoms. 4. The semiconductor device according to claim 1, wherein the second semiconductor layer has a thickness of 15 nm or more and 50 nm or less. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the opening of the third semiconductor layer is formed by selective dry etching. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the opening of the second semiconductor layer is formed by selective wet etching. 7. The method of manufacturing a semiconductor device according to claim 5, wherein the opening of the second semiconductor layer is formed by dry etching that has lower damage than dry etching for opening the first semiconductor layer. 8. An electronic circuit using the semiconductor device according to claim 1, 2, 3, or 4.