JPH0721061A - Program performance analyzing method - Google Patents

Abstract

PURPOSE:To provide a method to analyze the performance of a program by setting only an instruction pass executed actually as a target, and calculating execution time considering the pipeline interlock of a continuous instruction string without changing a source program. CONSTITUTION:A mechanical word instruction string 70 is inputted, and it is divided into plural fundamental blocks by fundamental block division processing 31, and the number of static execution cycles of the fundamental block is calculated by using interlock information 40 in cycle number calculation processing 32. At this time, the number of times of generation at every interlock specification is tabulated in generating number of times tabulation processing 33 simultaneously. The number of times of execution of each fundamental block is inputted from execution number of times information 80, and the execution time of the fundamental block is displayed by calculating from the number of cycles calculated by execution time calculation processing 34.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program performance analysis method, and more particularly, to a program performance analysis capable of analyzing program performance by calculating program execution time in consideration of pipeline interlock. Regarding the method.

[0002]

2. Description of the Related Art Conventionally, various program performance analysis methods for evaluating program performance have been known.

For example, as a program performance analysis method for analyzing which part of the program has a large execution ratio when the source program is compiled and the obtained load module is executed, a method for measuring execution time in the source program is used. There is a way to insert a process. This is a method in which the parser artificially inserts a statement for measuring the execution time into the source program, compiles it, executes the load module obtained, and thereby measures the execution time. is there.

Another analysis method is disclosed in Japanese Patent Laid-Open No. 4-320.
It is disclosed in Japanese Patent No. 536. This is to create a flow graph of a program from a machine language or assembler list obtained by compiling a source program, calculate the static execution time of each path existing in the flow graph, and calculate the program by the sum of them. This is a method for evaluating the performance related to the execution time of.

Furthermore, POHUA P. CHANG et al.'S paper "Using Profile Information"
on to Assist Code Optimize
ation ”: SOFTWARE-PRACTICE
AND EXPERIENCE, Vol. 21 (1
2), 1301-1321 (DECEMBER 199
1) discloses a method of acquiring the number of times of execution of a basic block (a series of assignment statements or sequences of expressions that are executed sequentially).

In the basic block execution count acquisition method disclosed in this paper, at the entrance of each basic block, a function for recording the execution count is called using the identifier assigned to each basic block as an argument. The identifier is a unique identifier in the program assigned to each basic block. The called function performs a process of adding 1 to the execution count of the basic block represented by the identifier given as an argument. This makes it possible to know how many times each basic block has been executed when the execution of the program is completed, and the program can be evaluated by the number of times each basic block has been executed.

[0007]

However, in the method of inserting the process for measuring the execution time in the source program,
In order to measure the execution time for all of the respective program parts, it is necessary to insert a certain number of processes for measuring the execution time into the program. Therefore, the processing overhead for measuring the execution time is included in the execution time of the measurement target portion, and there is a problem that the execution time of only the program portion cannot be accurately measured.

Further, when inserting a process for measuring time in a program, the analyst predicts to some extent whether the program can be evaluated by measuring the execution time from which position of the program to which position. The insertion location is determined based on such predictions. However, if the prediction is incorrect, it is necessary to insert the time measurement process into the source program again, compile and execute it again.

Further, in the method disclosed in the above-mentioned Japanese Patent Laid-Open No. 4-320536, the execution time of each path existing in the flow graph of the program is obtained, and the performance of the program is analyzed by the sum of those execution times. In some cases, the execution time of a path that may never be executed at the time of execution is also subject to analysis.

Further, in the method of evaluating the program by acquiring the number of executions of the basic block, the evaluation cannot be performed by the actual execution time of the program.

Therefore, a first object of the present invention is to provide a program performance analysis method targeting only the actually executed execution path.

A second object of the present invention is to analyze the performance of the program by calculating the execution time in consideration of the pipeline interlock of continuous instruction sequences without changing the source program. It is to provide a program performance analysis method.

[0013]

In order to achieve the above object, the present invention comprises a dividing step of dividing an inputted machine language instruction sequence into basic blocks which are continuous partial instruction sequences,
An execution count input step for inputting the execution count of the basic block; a cycle count calculating step for obtaining the execution cycle count of the basic block in consideration of pipeline interlock; and an execution cycle count and execution count for the basic block. And an execution time calculation step for calculating the execution time of the basic block using

In the dividing step, for example, the machine language instructions of the machine language instruction string are read one by one from the beginning, and when the read instruction is a branch instruction, it is divided between the branch instruction and the next instruction, Alternatively, when the read instruction is a label, it is divided before the label to divide the machine language instruction sequence into basic blocks.

The machine language instruction sequence may be prepared by any procedure. For example, a program created by compiling a high-level language source program that is the target of performance analysis may be used.

The number of times the basic block is executed may be measured by a conventionally known method. For example, when compiling a source program, a load module to which an object code for measuring the number of executions is added and output for each basic block, the load module is executed, and the number of executions of each basic block is calculated. A measuring method or the like is used.

In the cycle number calculation step, if there is a sequence of instruction sequences in which pipeline interlocks occur when the number of execution cycles of a basic block is calculated, a process of totalizing the number of occurrences for each type of interlock may be performed. Good. The number of occurrences of each type of interlock is also an index for evaluating program performance.

When the source program which is the object of performance analysis includes a loop, the execution time of the loop may be calculated from the number of execution cycles and the number of executions of the basic blocks forming the loop.

Further, the performance analysis result of the program obtained as described above (for example, the execution count and execution time for each basic block, and the interlock occurrence count for each interlock type) is displayed on the display device. Good to do.

[0020]

The machine language instruction sequence is divided into basic blocks, and the number of static execution cycles is calculated in consideration of the pipeline interlock of the basic blocks. Further, the execution time of the basic block can be calculated by inputting the execution count of the basic block and using the execution cycle count and the execution count.
The number of executions of the basic block is determined by generating and outputting a load module to which an object code for measuring the number of executions is added for each basic block when the source program is compiled, and executing the load module.
The number of executions of each basic block can be measured.

As a result, it is possible to analyze the program performance without changing the source program and targeting only the actually executed execution path.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

Before explaining each drawing, a pipeline interlock (hereinafter, abbreviated as interlock) will be described.

There is a certain two instructions (the one that is executed first is called the preceding instruction and the one that is executed subsequently is called the succeeding instruction), and there is a dependency between the preceding instruction and the succeeding instruction. The start of instruction execution may be delayed. For example, if there is a definition / citation relationship between the preceding instruction and the succeeding instruction in the same register or the same memory area, execution of the preceding instruction may delay the start of execution of the succeeding instruction, or
This is the case where the start of execution of the subsequent instruction is delayed because the preceding and subsequent instructions use the same arithmetic unit. In such a case, there is an interlock between the preceding instruction and the subsequent instruction.

The condition under which this interlock occurs is CP
Different for each U. The condition for interlock occurrence described in the present embodiment is an example thereof, and the present invention is not limited thereby.

FIG. 17 shows an instruction type handled in this embodiment and a method of writing the instruction in assembler. In the operand, Mem indicates access to memory, and Rx
Indicates access to a register.

The load instruction 201 is an instruction to read the data stored in the memory Mem into the register Ri. The store instruction 202 is an instruction to write the data stored in the register Ri into the memory Mem. The addition instruction is an instruction to add the data stored in the two registers Rj and Rk and store the result in the register Ri. The multiplication instruction is an instruction for multiplying the data stored in the two registers Rj and Rk and storing the result in the register Ri. The branch instruction is a branch instruction that transfers control to the position of label lab-xx.

FIG. 1 is a system configuration diagram of a program performance analysis system to which a program performance analysis method according to an embodiment of the present invention is applied.

This system comprises a CPU device 1, a memory device 2, an input device 3, and a display device 4. Specifically, it is a system in which a computer is combined with a predetermined program. The CPU device 1 includes a compiler 10, an execution unit 20, and a program performance analysis unit 30.

The compiler 10 uses the source program 50.
And compile the source program. In particular, the machine language instruction string output process 11 generates a machine language instruction string 70 according to the input source program. The execution count output code generation process 12 also generates a load module 60 to which an object code for measuring the execution count is added for each basic block.

The execution unit 20 has its load module 60.
Is executed and the execution count output processing 21 measures the execution count of each basic block. The measurement result is output as the execution count information 80.

The program performance analysis unit 30 is composed of a basic block division process 31, a cycle number calculation process 32, an interlock occurrence count total 33, and an execution time calculation process 34.

FIG. 2 shows a flow of processing by the compiler 10 and the execution unit 20 of FIG. 1, that is, processing for obtaining the machine language instruction string 70 and the execution count information 80.

The machine language instruction sequence output processing 11 in the compiler 10 inputs the source program 50 and outputs a machine language instruction sequence 70.

FIG. 4 shows an example of the source program 50 and the machine language instruction sequence 70. A high-level language source program 801 is compiled and a machine language instruction string represented by an assembler list is output. This machine language instruction sequence includes a label 802 and an instruction sequence 805.
-1 to 805-6. Instruction sequence 805-1 to 805
-6 is described by the notation described in FIG.

Referring again to FIG. 2, the execution count output code generation processing 12 in the compiler 10 outputs the load module 60 to which the object code for measuring the execution count of the basic block is added. This object code is added to each basic block.

Next, the execution module 20 executes the load module 60. As a result, the number of executions of each basic block is measured. The execution count output process 21 outputs the measurement result. As a result, the execution count information 80 recording the execution count for each basic block is created.

FIG. 3 shows the program performance analysis unit 30 of FIG.
The flow of processing in is shown.

The program performance analysis unit 30 stores the interlock information 40 in which the interlock information is registered, the machine language instruction sequence 70 output by the compiler, and the execution count information 80 obtained by executing the load module 60. Enter and.

The program performance analysis section 30 first performs basic block division processing 31. Basic block division processing 31
Then, the input machine language instruction sequence 70 is divided into basic blocks (a sequence of a series of assignment statements and expressions that are executed sequentially). Then, a basic block information table, an instruction sequence information table, and an interlock tabulation table are created for each basic block of all the basic blocks obtained by division.

FIG. 5 shows the structure of these tables.

FIG. 5A shows the structure of an instruction sequence information table 900 which stores information on all the instructions in the basic block. This instruction sequence information table 900 is secured in a basic block by the number of instructions in the basic block. 901 is a field for storing the instruction type, 90
Reference numeral 2 is a field for storing the number of start cycles indicating the cycle in which the instruction can be executed in the basic block, 903 is a field for storing the register name of the register defined by the instruction, 904 Is a field for storing the register name when there is a register referred to by the instruction.

FIG. 5B shows the structure of the interlock aggregation table 920 which stores the number of occurrences for each type of interlock. The interlock tabulation table 920 is created for each type of interlock generated in the basic block. Reference numeral 921 is a field for describing the type of interlock, and 922 is a field for storing the number of occurrences of the interlock of that type.

FIG. 5C shows a basic block information table 950 which stores information on all basic blocks. The basic block information table 950 is created for each basic block.

Reference numeral 951 is a field for storing the label name of the basic block, 952 is a field for storing the number of instructions in the basic block, and 953 is a field for storing the number of static execution cycles of the basic block at one time. Reference numeral 954 is an interlock aggregation table storing the number of interlock occurrences in the basic block (FIG. 5 (B)).
A field for storing a pointer to the instruction sequence information table 955 relating to the instructions in the basic block (see FIG. 5).
(A)) is a field for storing a pointer, and 956 is a field for storing a pointer to the next basic block information.

FIG. 5D shows a list structure composed of a basic block information table, an instruction string information table, and an interlock aggregation table. A basic block information table 950 is created for each basic block and is connected by a pointer 956. Basic block information 950
The pointer 954 stores the head address of the list of the interlock aggregation table 920 of the basic block. Also, the pointer 9 of the basic block information 950
55 is an instruction sequence information table 90 of the basic block.
The start address of the list of 0 is stored.

Referring again to FIG. 3, in the basic block division processing 31, the machine language instruction string 70 is input, and the basic block information table, the instruction string information table and the interlock having the list structure described in FIG. 5 are input. Create a summary table. At this point, the number of instruction cycles 902 in FIG. 5A, the number of occurrences 922 in FIG. 5B, and the number of cycles 953 in FIG. 5C are initialized to 0.

After the basic block division processing 31, a cycle number calculation processing 32 is performed. In the cycle number calculation process 32,
For all divided basic blocks, the number of execution cycles of the instruction sequence in each basic block is calculated based on the interlock information registered in the interlock information 40.

FIG. 6 shows an example of the contents of the interlock information 40 shown in FIGS. In the present embodiment, as the interlock information, a "instruction combination" and a "register use condition" that are conditions under which the interlock occurs, and "how many cycles are delayed when the interlock occurs" are shown. "Number of interlock cycles" is prepared in advance.

For example, when the register defined by the preceding instruction “load” and the register used (quoted) by the subsequent instruction “addition” are the same, the interlock information 301 is between the two instructions. If at least one instruction that is not affected by the preceding instruction "load" (interlock does not occur) is inserted, execution of the subsequent instruction "addition" starts one cycle later than usual. Is shown to be done.

For example, assume that execution of a load instruction is started in the nth cycle with the following instruction sequence.

N Ri = Mem n + 1 (1 cycle interlock) n + 2 Rk = Ri + Rj

In this case, since one cycle of interlock occurs between the loading of the preceding instruction and the addition of the succeeding instruction, the subsequent addition instruction is started in the (n + 2) th cycle. Other interlock information 302, 303, 30
4 also has the same meaning as the interlock information 301.

Referring again to FIG. 3, in the cycle number calculation process 32, while referring to the interlock information as shown in FIG. 6, the number of execution cycles of the instruction sequence in each basic block is considered in consideration of the interlock. To calculate. The result (that is, the number of execution cycles of the instruction sequence of the basic block) is shown in FIG.
It is set to the cycle number 953 of the basic block information 950 of (C). In addition, the number of start cycles of each instruction which becomes clear during calculation of the number of execution cycles is shown in FIG.
The number of start cycles of the instruction sequence information table 900 in (A) is 9
It is set to 02.

Next, the interlock counting process 33 is performed.
In the interlock aggregation processing 33, the interlock information 40
Based on the interlock information registered in, the type of interlock in each basic block and how many times it occurred are totaled. The counting result is set in the occurrence count 922 of the interlock counting table 920 of FIG.

Next, the execution time calculation process 33 is performed. In the execution time calculation process 33, the execution time is calculated for all the divided basic blocks based on the number of times of execution of the basic block and the number of cycles of the basic block. The execution count of the basic block is obtained by referring to the execution count information 80. The cycle number of the basic block is obtained by referring to the cycle number 953 of the basic block information table 950 of the basic block. The execution time is calculated by the following formula.

Execution time [seconds] = number of executions [times] × number of cycles [cycle] × (1 ÷ CPU operating frequency) [seconds / cy
cle]

For example, the execution count of a certain basic block is 1
When the number of cycles is 100,000,000, the number of cycles is 100, and the operating frequency of the CPU is 50 MHz, the execution time of the basic block is as follows.

Execution time [sec] = 10000000 × 10
0 × (1 ÷ 50000000) = 20 [seconds]

Next, the procedure of the program performance analysis processing 30 in this embodiment will be described in detail with reference to FIGS.

FIG. 7 shows the procedure of the program performance analysis processing 30 in this embodiment. First, in step 401a, a machine language instruction sequence is input from the machine language instruction sequence 70, basic block division processing (31 in FIG. 3) is performed,
A basic block information table, an instruction sequence information table, and an interlock aggregation table (FIG. 5) are created for each basic block, and the process proceeds to step 401b.

In step 401b, step 401a
For all the basic blocks created in step 1, the number of execution cycles and the number of interlock occurrences of the instruction sequence contained in the basic block are calculated (32, 33 in FIG. 3), and step 40
Go to 1c.

In step 401c, step 401a
Step 401 for all basic blocks created in
The execution time is calculated from the number of cycles calculated in step b and the number of executions of the execution count information 80 (34 in FIG. 3), and the calculation result and the number of interlocks generated in step 401b are displayed on the display device 4 ( Displayed in FIGS. 1 and 3).

8 and 9 are flowcharts showing the processing procedure of the basic block division processing 401a.

Before describing this processing procedure, the work data area used in this processing will be described first. A label stack, an instruction stack, and a variable inst_cnt are prepared as the work data area.

The label stack is an area for storing the label name output to the machine language instruction sequence 70. This label name is used to identify the basic block,
It is assumed that there is a one-to-one correspondence with the label information output in the execution count information 80. The instruction stack is an area for storing instructions in the basic block. Initially, the instruction stack is empty. An instruction is stored in the instruction stack each time one instruction is read. When the processing of one basic block is completed, the instruction stack becomes empty again. The variable inst_cnt is a variable used to count the number of instructions in the basic block.

Next, the basic block division processing 401a will be described with reference to FIGS. 8 and 9.

In step 501a, the label stack and the instruction stack are emptied, and the variable inst_cnt is set to 0.
Then, the process proceeds to step 505a. In step 505a, it is determined whether or not there is a machine language instruction that is not read in the machine language instruction sequence 70. If there is a machine language command that has not been read, the process proceeds to step 501b. Without machine instructions,
Proceed to step 515a.

At step 510b, the machine language instruction sequence 70
One machine language instruction is read from and the process proceeds to step 505b. In step 505b, it is determined whether the read instruction is a branch instruction. If the read instruction is a branch instruction, the process proceeds to step 501d. If it is not a branch instruction, the process proceeds to step 505c.

In step 505c, it is determined whether the read instruction is a label. If the read instruction is a label, the process proceeds to step 505d. If not a label
Proceed to step 501c.

In step 501c, the read instruction is stored in the instruction stack. Since one instruction is added to the basic block by storing the instruction in the instruction stack, 1 is added to the variable inst_cnt, and the process proceeds to step 505a.

In step 501d, the read branch instruction is stored in the instruction stack, and the variable inst_cnt is stored.
After adding 1 to step 501e, the process proceeds to step 501e.

In step 505d, the label name is not stored in the label stack, and the variable inst_cn is set.
It is determined whether t is 0. This determination is to prevent the creation of a basic block that does not have the label name of the basic block and has no instructions in the basic block. If this determination condition is satisfied, step 5
Go to 05a. If the determination condition is not satisfied, the process proceeds to step 501e.

In step 501e, one basic block information is created from the information stored in the label stack and the instruction stack.

The basic block information is created in the following procedure. First, one basic block information table 950 shown in FIG. 5C is created and added to the end of the basic block information table list. Next, the labels stored in the label stack are stored in the created basic block information table 9
The label name field 951 of 50 is registered. Next, in the block instruction count field 952, the variable inst_c
Stores the value of nt. Also, 0 is registered in the total cycle number field 953.

Further, the interlock occurrence count table 920 shown in FIG. 5B is created, and the occurrence count fields of all interlock types in the interlock occurrence count table 920 are initialized to zero. The interlock occurrence count totaling table 920 is created so as to have an area for totaling the number of interlock occurrences for all interlock types registered in the interlock information 40 of FIG.

Further, an instruction string information table 900 (FIG. 5A) having an area capable of storing variable inst_cnt instruction strings is created, and the instructions stored in the instruction stack are stored in the instruction field of the instruction string information table. Register in 901. At that time, the registers defined or quoted by the registered instruction are registered in the definition register field 903 or the reference register field 904, respectively. The number of start cycles field 902 is 0 for all instructions.
Initialize to.

With the above processing, the creation of the basic block information (table in FIG. 5) in step 501e is completed.

In step 501e, the label stack and the instruction stack are further emptied, and if the instruction read immediately before is the label, the label name is stored in the label stack. If the instruction read immediately before is a branch instruction, the label name is not stored in the label stack. Finally, the variable inst_cnt is set to 0,
Go to step 505a.

At step 515a, it is judged whether or not there is an instruction left on the instruction stack. If there are unloaded items, the process proceeds to step 511a. If not left, the basic block division processing is terminated. In step 511a, similar to the operation in step 501e, one basic block information is created from the information stored in the label stack and the instruction stack. After that, the basic block division processing ends.

FIG. 10 is a flow chart showing the processing procedure of the cycle number calculation / interlock occurrence frequency totaling processing 401b.

First, in step 605a, it is determined whether or not there is a basic block whose cycle number has not been calculated in the basic block information table list. This determination is made by checking whether or not there is a basic block whose cycle number field 953 of the basic block information table 950 of FIG. If there is a basic block for which the number of cycles has not been calculated, the process proceeds to step 601a. If there is no basic block for which the number of cycles has not been calculated, the calculation of the number of cycles has been completed for all the basic blocks, so the cycle number calculation / interlock occurrence count totaling process ends.

In step 601a, first, a variable crt_ holding the number of cycles to which an instruction can be assigned is held.
Set cycle to 1. Setting the number of cycles to 1 means that the first instruction in the basic block must be 1
It means that it is assigned to the cycle. Next, the variable i indicating which table in the instruction string information table 900 is pointed to is set to 1.

FIG. 12 shows an example of the instruction sequence information table 900. Explaining with reference to FIG.
Is first, table 900-2 is second, table 90
0-3 is the third.

Further, in step 601a, the value of the in-block instruction number field 952 of the basic block information table 950 is substituted into the variable max_inst for storing the number of instructions in the basic block. And step 605
Go to b.

At step 605b, the variable i is changed to the variable ma.
It is determined whether it is less than or equal to x_inst. If the variable i is less than or equal to the variable max_inst, step 601b
Proceed to. If the variable i is larger than the variable max_inst, the process proceeds to step 605e.

At step 605e, the variable max_in
It is determined whether st is 0. Variable max_in
If st is 0, it means that there is no instruction in the basic block, so the cycle number field 953 of the basic block information table 950 is left at the initial value 0,
Go to step 601g. If the variable max_inst is not 0, the process proceeds to step 601f and max_ins
The value stored in the start cycle number field 902 of the t-th instruction string information table 900 is set as the execution cycle number of the basic block, and the value is stored in the cycle number field 953 of the basic block information table 950.
Then, the process proceeds to step 601g.

At step 601g, the basic block next to the basic block for which the cycle number calculation process has been completed is selected, and the routine proceeds to step 605a.

In step 601b, first, the number of cycles at which the i-th instruction can be started (that is, the start cycle number of the i-th instruction) is determined by the following equation.

I_cycle = MAX (i_cycle
e, crt_cycle)

Here, the symbol i_cycle represents the start cycle number field 902 of the i-th instruction of the instruction sequence information table 900. In addition, MAX is a function that returns, as a result, one having a larger value out of the values of the two arguments.

If i_cycle is returned as a result of the evaluation of the above expression, it indicates that an interlock has occurred between the instruction assigned before the i-th instruction and the i-th instruction. If crt_cycle is returned, it indicates that the interlock has been canceled because there is no interlock with the preceding instruction, or because there is another instruction between the instruction in which the interlock occurs. Next, the start cycle number i_cycle of the i-th instruction is substituted into the variable crt_cycle.

Further, in step 601b, the inspection range is determined in order to inspect whether or not an interlock may occur between the i-th instruction and its subsequent instruction. The check is performed after step 605c. Specifically, it is checked whether there is an interlock between the i-th instruction and the j-th instruction while moving the variable j from i + 1 to loop_end. This loo
The value of p_end, that is, the range for checking whether an interlock occurs with the i-th instruction is determined by the following formula.

Loop_end = MIN (max_in
If the st, i-th instruction is of the interlock type, the maximum number of interlock cycles + i +
1)

However, MIN is a function that returns a result having a smaller value as a result opposite to MAX. In the above equation, the basic range of the check is the instruction after the maximum number of interlock cycles among the interlocks that may occur by the i-th instruction, but the number of instructions in the basic block is max_inst. From
This means that either smaller value is set to loop_end.

Finally, i + 1 is assigned as an initial value to a variable j indicating the jth instruction to be checked with the ith instruction. Then, the process proceeds to step 605c.

In step 605c, it is checked whether or not the variable j is less than or equal to loop_end in order to judge whether or not all the interlocks with the i-th instruction have been checked. If the variable j is less than or equal to loop_end, the process proceeds to step 605c. Variable j is loop_e
If it is larger than nd, the process proceeds to step 605d.

In step 605d, it is determined whether an interlock registered in the interlock information table 300 has occurred between the instruction i and the instruction j based on the instruction combination and the register use condition. If there is an interlock, the process proceeds to step 601c. If there is no interlock, the process proceeds to step 601d.

In step 601c, first, in step 6
Number of occurrences of interlock type determined in 05d (Fig. 5
Add 1 to 922) of (B). Next, the number of cycles from which the j-th instruction can be started due to the interlock generated by the i-th instruction is determined by the following formula.

J_cycle = MAX (j_cycle
e, i_cycle + 1 + i interlock cycle number)

Here, the symbol j_cycle is i_cy.
Similar to cle, it represents the start cycle number field 902 of the j-th instruction of the instruction sequence information table 900. Since the j-th instruction may already have an interlock between instructions different from the i-th instruction, if the delay due to the already set interlock is larger, the already determined j_cycle is started. Cycle and if the delay due to the i-th instruction is greater,
The “interlock cycle number by i_cycle + 1 + i” is the start cycle of j_cycle. And
Go to step 601d.

At step 601d, 1 is added to the variable j in order to perform a check between the i-th and j + 1-th instructions.
Then, the process proceeds to step 605c.

In step 601e, the interlock check between the i-th instruction and its succeeding instruction is completed, and i + 1
Add 1 to the variable i to perform the check by the th instruction. The cycle in which the i + 1th instruction can be started is crt_, which indicates the ith start cycle in the earliest case.
next cycle of cycle, ie crt_cycle
Since it becomes e + 1, 1 is added to crt_cycle.
Then, the process proceeds to step 605b.

FIG. 12 shows an instruction sequence information table 900 created by executing the basic block division processing 401a for the machine language instruction sequence of FIG. Data corresponding to each instruction is set in the instruction field 901, the definition register field 903, and the reference register field 904. Start cycle number field 9
02 are all initialized to 0.

FIG. 13 shows the instruction sequence information table 9 of FIG.
The result of executing the cycle number calculation / interlock occurrence frequency totaling process 401b for 00 is shown. The number of cycles at which each instruction is started is set in the start cycle number field 902.

Next, the execution time calculation process 401c will be described.

FIG. 14 shows an example of the contents of the execution count information table 120 which stores the execution count information 80 (FIG. 2). The execution count information table 120 includes a label name field 121 that stores a label name for identifying a basic block and an execution count field 122 that stores the number of times the basic block was actually executed.

FIG. 11 is a flow chart showing the processing procedure of the execution time calculation processing 401c.

First, in step 705a, it is determined whether or not there is the execution count information stored in the execution count information table 120. If there is execution count information, step 70
Go to 1a. If there is no execution count information, the execution time calculation process ends.

In step 701a, first, one execution count information is read. Next, basic block information 95 of the basic block corresponding to the label name of the read execution count information
The cycle number 953 is taken out from 0. Next, the execution time is calculated from the number of executions and the number of cycles. Finally, the calculation result is displayed on the display device 4. Then, step 705a
Proceed to.

FIG. 15 is a display example 130 of the calculated execution time and the number of interlock occurrences. The contents to be displayed are the label name of the basic block, the number of executions, the number of cycles and the execution time per basic block, and the number of occurrences for each interlock type.

By using the embodiment described above,
It becomes possible to calculate the execution time of the basic block, obtain the number of occurrences for each interlock type, and display the respective results. This makes it possible to detect in which part of the program the execution ratio is high,
Evaluate program performance.

In the above embodiment, when the source program of the performance analysis includes a loop process, the execution time of the loop is calculated from the number of execution cycles and the number of executions of the partial instruction sequence group forming the loop. However, it may be displayed.

FIG. 16 is an example of a source program including a loop. The loop execution time calculation procedure will be described using this example. The loop is divided into basic blocks,
It is divided into several basic blocks. In this example,
It is divided into three basic blocks 141, 142, 143. The execution time of one basic block can be calculated by the procedure described above, and the execution time can also be calculated for the three basic blocks in this example. Therefore, the execution time of the loop can be calculated by simply adding the execution times of the three basic blocks.

By displaying the execution time of the loop,
The performance of the loop part of the program can be evaluated.

[0116]

As described above, according to the present invention,
You can know the execution time considering the pipeline interlock, and you can analyze the performance of the program for the actual execution path. Furthermore, it is not necessary to change the source program.

[Brief description of drawings]

FIG. 1 is a system configuration diagram of a program performance analysis system to which a program performance analysis method according to an embodiment of the present invention is applied.

FIG. 2 is a flowchart of a process for obtaining a machine language instruction string and execution count information.

FIG. 3 is a flowchart of processing in a program performance analysis unit.

FIG. 4 is a diagram showing an example of a source program and a machine language instruction sequence.

FIG. 5 is a basic block information table, an instruction string information table, and an interlock aggregation table.

FIG. 6 is a diagram showing an example of contents of interlock information.

FIG. 7 is a flowchart showing the operation of program performance analysis processing.

FIG. 8 is a flowchart showing an operation of basic block division processing.

FIG. 9 is a flowchart showing an operation of basic block division processing.

FIG. 10 is a flowchart showing the operation of a cycle number calculation / interlock occurrence frequency totaling process of a basic block.

FIG. 11 is a flowchart showing the operation of execution time calculation processing.

FIG. 12 is a diagram showing an example of contents of an instruction sequence information table after execution of basic block division processing.

FIG. 13 is a diagram showing an example of the contents of an instruction sequence information table after the cycle number calculation / interlock occurrence number aggregation process.

FIG. 14 is a diagram showing execution count information.

FIG. 15 is a display example of execution time and interlock occurrence frequency.

FIG. 17 is a diagram showing the types of instructions handled in the example and the description method in the assembler.

[Explanation of symbols]

4 ... Display device, 30 ... Program performance analysis, 31 ... Basic block division, 32 ... Cycle number calculation, 33 ... Interlock aggregation, 34 ... Execution time calculation, 40 ... Interlock information, 70 ... Machine language instruction string, 80 ... Execution count information.

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[Procedure amendment]

[Submission date] July 8, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a system configuration diagram of a program performance analysis system to which a program performance analysis method according to an embodiment of the present invention is applied.

FIG. 2 is a flowchart of a process for obtaining a machine language instruction string and execution count information.

FIG. 3 is a flowchart of processing in a program performance analysis unit.

FIG. 4 is a diagram showing an example of a source program and a machine language instruction sequence.

FIG. 5 is a basic block information table, an instruction string information table, and an interlock aggregation table.

FIG. 6 is a diagram showing an example of contents of interlock information.

FIG. 7 is a flowchart showing the operation of program performance analysis processing.

FIG. 8 is a flowchart showing an operation of basic block division processing.

FIG. 9 is a flowchart showing an operation of basic block division processing.

FIG. 10 is a flowchart showing the operation of a cycle number calculation / interlock occurrence frequency totaling process of a basic block.

FIG. 11 is a flowchart showing the operation of execution time calculation processing.

FIG. 12 is a diagram showing an example of contents of an instruction sequence information table after execution of basic block division processing.

FIG. 13 is a diagram showing an example of the contents of an instruction sequence information table after the cycle number calculation / interlock occurrence number aggregation process.

FIG. 14 is a diagram showing execution count information.

FIG. 15 is a display example of execution time and interlock occurrence frequency.

FIG. 16 is an example of a source program including a loop.

FIG. 17 is a diagram showing the types of instructions handled in the example and the description method in the assembler.

[Explanation of Codes] 4 ... Display device, 30 ... Program performance analysis, 31 ... Basic block division, 32 ... Cycle number calculation, 33 ... Interlock aggregation, 34 ... Execution time calculation, 40 ... Interlock information, 70 ... Machine language Instruction string, 80 ... Execution count information.

Claims (7)

[Claims] 1. A division step of dividing an input machine language instruction sequence into basic blocks which are continuous partial instruction sequences, an execution number input step of inputting the number of times of execution of the basic block, and a pipeline interlock. Then, a cycle number calculation step for obtaining the number of execution cycles of the basic block, and an execution time calculation step for calculating the execution time of the basic block using the number of execution cycles and the number of executions of the basic block are provided. A program performance analysis method characterized by the above. 2. The program performance analysis method according to claim 1, wherein in the dividing step, the machine language instructions of the machine language instruction sequence are read one by one from the beginning, and when the read instruction is a branch instruction, the branch is executed. A program performance analysis characterized in that the machine language instruction sequence is divided into basic blocks by dividing between an instruction and the next instruction, or when the read instruction is a label, it is divided before the label. Method. 3. The program performance analysis method according to claim 1, wherein the machine language instruction sequence is created by compiling a source program. 4. The program performance analysis method according to claim 3, further comprising: when compiling the source program, generating a load module added with an object code for measuring an execution count for each basic block. An execution count output code generation processing step for outputting, and an execution count output processing step for executing the load module, measuring the execution count of each basic block, and outputting to the execution count input step. Program performance analysis method. 5. The program performance analysis method according to claim 1, wherein the step of calculating the number of cycles includes an interlock when an instruction string in which pipeline interlock occurs is generated when calculating the number of execution cycles of consecutive instruction strings. A program performance analysis method characterized by also performing a process of totaling the number of occurrences of each type. 6. The program performance according to claim 3, wherein when the source program includes a loop, the execution time of the loop is calculated from the number of execution cycles and the number of executions of basic blocks forming the loop. analysis method. 7. The program performance analysis method according to claim 1, further comprising a step of displaying a performance analysis result of the program.