JPH07219595A - Digital signal processing method and device therefor - Google Patents

Abstract

PURPOSE:To improve a dynamic range at the time of a small input while preventing an overflow. CONSTITUTION:A so-called block floating in which a gain is controlled by dividing an input signal into blocks every constant samples at the time of filtering operations of band dividing filters 106, 107 and by detecting the maximum value of a sample whose absolute value is the largest among blocks and by performing multiplying operations of multiplying samples in blocks by perscribed coefficients according to the size of the sample is executed in a block floating part and then the floating releasing is executed in the floating releasing circuits 115, 116, 117 by dividing respective samples by the respective multiplier.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing method for coding digital signals such as audio signals, audio signals and image signals, a digital signal processing method for decoding the digital signals, and a digital signal processing method for the digital signals. The present invention relates to a digital signal processing device that realizes a signal processing method.

[0002]

2. Description of the Related Art As one type of high-efficiency encoding in which a time-series sample data signal such as an audio signal is bit-compressed and encoded with high efficiency, band division encoding for performing encoding using a digital filter and spectrum conversion are performed. The transform coding used and the like are known, and a method combining both of them is also adopted.

An example of band division encoding is ISO11172-3 of ISO (International Organization for Standardization) standard. Further, as the digital filter, a so-called QMF (Quadratic Mirror Filter) filter is suitable because aliasing due to band division is canceled after combination.

Regarding the above QMF, for example, the document "Analysis / Syn" using "filter bank design based on time domain aliasing cancellation"("Analysis / Syn") is used.
tehsis Filter Bank Design Based on Time Domain Ali
asing Cancellation ", J. Princen and A. Bradley, IEEE
Transactions on Acoustics, Speech and Signal Proc
essing, Vol 34 pp.1153-1161, 1986).

[0005]

However, when the level of the input signal is high in the operation of the digital filter required in the band division coding as described above, it is not a problem, but the level of the input signal is If the value becomes smaller, there is a problem in that the calculation error becomes particularly large and the noise increases in the case of a fixed-point calculation.

Therefore, in view of the above, the present invention provides a digital signal processing method and a digital signal processing method in which, even when the level of the input signal becomes small, the calculation error does not increase and the noise does not increase in the calculation of the digital filter. The purpose is to provide a device.

[0007]

The present invention has been proposed in order to achieve the above object, and a digital signal processing method of the present invention provides a predetermined non-blocking frequency analysis for an input signal. After performing an encoding process for quantizing the analysis output by performing the recording or transmission, the input signal is divided into blocks for each of a plurality of samples,
When the level of the maximum absolute value of the input signal sample in each block is smaller than the predetermined threshold, all samples of the input signal of the block are multiplied by a predetermined coefficient and then a predetermined calculation is performed. After the predetermined calculation, each sample is divided by the predetermined coefficient.

In the digital signal processing method of the present invention, a predetermined non-blocking frequency analysis is performed on an input signal, the analysis output of the non-blocking frequency analysis is divided into blocks, and a predetermined blocking frequency analysis is performed.
It is also for recording or transmitting after performing an encoding process for quantizing the analysis output of the blocking frequency analysis, and the level of the maximum value of the absolute value of the sample of the input signal in each block is higher than a predetermined threshold. When it is small, all the samples of the input signal of the block are multiplied by a predetermined coefficient, a predetermined operation is performed, and each sample is divided by the predetermined coefficient after the predetermined operation. .

Furthermore, the digital signal processing method of the present invention is also a digital signal processing method for performing a predetermined non-blocking frequency analysis on an input signal. The input signal is divided into blocks, and in each block, absolute samples of the input signal are sampled. When the value is smaller than the predetermined threshold, all samples of the input signal of the block are multiplied by a predetermined coefficient, and then a predetermined calculation is performed. It is characterized by removing. In this case, in the digital signal processing method of the present invention, when the level of the maximum absolute value of the samples of the input signal in each of the blocks is smaller than a predetermined threshold, for all the samples of the input signal of the block, And multiply by a predetermined coefficient.

Here, in the digital signal processing method of the present invention, as the maximum value, a logical sum of absolute values of samples of input signals of the blocks, which is an approximation of the maximum value, is used. Further, the maximum absolute value in a predetermined word length is used as the threshold, and the threshold and the coefficient are set from the operation word length of the encoding process and the coefficient of the predetermined operation. The predetermined coefficient is variable for each block. As the predetermined coefficient, a number obtained by dividing the threshold by the maximum value or a power of 2 is used. Use shift. Further, the bit shift is performed so that the word length of the maximum value after the shift is shorter than the operation word length excluding the sign bit of the coding process by a constant n. For example, 1 is used for this constant n. Further, the above-mentioned predetermined calculation is performed with a fixed point, for example, a digital filter calculation is performed as the predetermined calculation, and a quadrature mirror filter is used for the digital filter calculation. The filter calculation at this time is performed by subordinately connecting filters that divide the band of the supplied signal into two. For example, the filter division is performed by dividing the output on the low band side, which is obtained by dividing the band by the first filter into two, into two by the second filter.

Further, in the digital signal processing method of the present invention, the orthogonal transform processing is performed for each band after the above-mentioned predetermined calculation is performed. Here, the block size of the orthogonal transform process is variable, and a transform discrete cosine transform process is used as the orthogonal transform process. Further, in the digital signal processing method of the present invention, the operation word length of the encoding process is substantially the same as the word length of the input / output sample.

Next, according to the digital signal processing method of the present invention, the input signal is subjected to a predetermined non-blocking frequency analysis and subjected to an encoding process for quantizing the analysis output, and then recorded or transmitted. It also performs a decoding process to decode the signal, and blocks the recorded or transmitted signal into multiple samples, and the level of the maximum absolute value of the signal sample in each block is smaller than the predetermined threshold. In some cases, all the samples of the signal of the block are multiplied by a predetermined coefficient, a predetermined calculation is performed, and each sample is divided by the predetermined coefficient after the predetermined calculation.

Further, according to the digital signal processing method of the present invention, a predetermined non-blocking frequency analysis is performed on an input signal, the analysis output of the non-blocking frequency analysis is divided into blocks, and a predetermined blocking frequency analysis is performed.
After performing the encoding process for quantizing the analysis output of the blocking frequency analysis, it also performs the decoding process for decoding the recorded or transmitted signal, and the inverse blocking frequency corresponding to the predetermined blocking frequency analysis. When the analysis is performed and the level of the maximum value of the absolute value of the output of the inverse blocking frequency analysis in each block is smaller than the predetermined threshold, for all the samples that are the output of the inverse blocking frequency analysis of the block. Is multiplied by a predetermined coefficient, a predetermined calculation is performed, and after the predetermined calculation, each sample is divided by the predetermined coefficient.

Here, in the digital signal processing method of the present invention, as the maximum value, a logical sum of absolute values of the inverse blocking frequency analysis outputs of the blocks, which is an approximation of the maximum value, is used, and the threshold is predetermined. Using the maximum absolute value of the word length, the threshold and the coefficient are set from the operation word length of the decoding process and the coefficient of the predetermined operation. The predetermined coefficient is variable for each block, and the predetermined coefficient may be a number obtained by dividing the threshold by the maximum value or a power of 2, and the multiplication may be performed in bits. Use shift. Further, the bit shift is performed so that the word length of the maximum value after the shift is shorter than the operation word length excluding the code part of the decoding process by a constant n, and 1 is used for the constant n, for example. Further, the above-mentioned predetermined calculation is performed with a fixed point, a digital filter calculation is performed as the above-mentioned predetermined calculation, and an inverse quadrature mirror filter is used for the digital filter calculation. At this time, the filter calculation is performed by subordinately connecting filters for synthesizing the two divided bands, and the filter division is performed by synthesizing the two low band side bands by the first filter and the second band. The filter is used to configure the output of the first filter and the band on the highest band side to obtain the entire band.

Further, in the digital signal processing method of the present invention, the inverse orthogonal transform processing is performed for each of the bands, the block size of the inverse orthogonal transform processing is variable, and the inverse orthogonal discrete cosine transform is used as the inverse orthogonal transform processing. Use processing.
Further, in the digital signal processing method of the present invention, the operation word length of the decoding process is substantially the same as the word length of the input / output sample.

Finally, the digital signal processing apparatus of the present invention has a computing means to which the above-mentioned digital signal processing methods of the present invention are applied.

[0017]

According to the digital signal processing method and apparatus of the present invention, in the filter operation as the predetermined operation, the input signal is divided into blocks, for example, every fixed number of samples, and the absolute value is the largest in this block. By detecting the maximum value that is a sample and applying a so-called block floating method that controls the gain by multiplying the sample in the block by a predetermined coefficient according to the size of this sample, it is possible to relatively Even in a coding process and a decoding process that require a small amount of processing, the calculation error at the time of a small input is reduced and the dynamic range is improved.

Further, according to the digital signal processing method and apparatus of the present invention, in the block floating, in order to multiply each sample by a common coefficient, as a simpler method, floating using bit shift is used. This further simplifies the encoding process and the decoding process, and in the case of the device, reduces the hardware scale and speeds up the process.

Then, instead of detecting the maximum value of the samples in each block, the logical sum of the samples in each block is taken and used as an approximate value of this maximum value, thereby further performing the encoding process and the decoding process. And the hardware scale is reduced in the case of a device.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

In the present embodiment, a technique for combining a band division coding and an adaptive transform coding and highly efficient coding a digital signal using each technique of adaptive bit allocation will be described.

FIG. 1 shows a high-efficiency coding apparatus as a concrete configuration of the digital signal processing apparatus of the present invention which realizes the coding processing of the digital signal processing method of the present invention. In the high-efficiency encoder shown in FIG. 1, the input digital signal is divided into a plurality of frequency bands by a filter and the like, the bandwidth is set wider for higher frequencies, and orthogonal transformation is performed for each frequency band to obtain The spectrum data of the specified frequency axis is coded by adaptively allocating bits for each so-called critical band (critical band) considering human auditory characteristics or for each high band in which the critical band is further divided into multiple bands. ing. Of course, the frequency division width by the filter or the like may be equally divided.
Further, in the embodiment of the present invention, the orthogonal transform block size is adaptively changed according to the input signal before the orthogonal transform, and the floating process is performed during the filter calculation.

That is, in FIG. 1, the input terminal 100
Is supplied with an audio PCM signal of 0 to 20 kHz, for example. These input signals are divided into blocks, for example, every 512 samples and subjected to the processing described later.

The time-series sample data of the block consisting of 512 samples supplied to the input terminal 100 is sent to the shortest shift amount calculation circuit 102. The shortest shift amount calculation circuit 102 first obtains the absolute values of these samples and calculates the maximum value or an approximate value of the maximum value. Also here, instead of finding the maximum value itself,
As an approximate value of this maximum value, a logical sum of absolute values of the input time-series sample data of a block consisting of 512 samples may be taken. A detailed description of the block floating unit when the logical sum of input samples is used as the approximate value of the maximum value will be given later in FIG.

In the shortest shift amount calculation circuit 102, the maximum value obtained as described above or its approximate value is used as the operation word length excluding the code of the encoding apparatus of this embodiment. The number of times mb that can be shifted to the left is calculated until, and the shortest shift amount Mb is set to (mb-n). When the shortest shift amount Mb has a negative value, it is forcibly set to 0. Note that, here, n is a constant set in consideration of the operation word length and the filter coefficient of the encoding device in order to prevent overflow, and is a positive value including 0. Good.

From the next shift amount determination circuit 103, the shortest shift amount Mb of the time-series sample data of the block calculated as described above and the work area of the block immediately preceding the block in time will be described later. The information that is not larger than the shift amount Mw of the sample that has already been left-shifted in the work area of the filter calculation calculated in the floating unit is used as the shift amount M of the block, that is, the sample data floating circuit 104 and the filter work. Area data / shift amount adjustment circuit 10
Sent to 5.

Next, in the sample data floating circuit 104, the time-series sample data of the 512 sample blocks of the above block is transferred to the shift amount determining circuit 103.
Floating processing is performed in which the shift amount M determined in 1 is shifted to the left. Here, in order to simplify the floating process, a power of 2 is selected as a multiplier,
This operation is supposed to be performed by left shift. Note that in practice, the multiplier is not limited to the power of 2, and may take any value.

In the work area data in the work area floating portion, which will be described later, for the block immediately preceding the block in time, the effective word length of the maximum absolute value of the data in the work area has already been encoded. Since it is left-shifted by n smaller than the operation word length of the device, in the filter work area data / shift amount adjusting circuit 105, the shift amount M selected by the shift amount determining circuit 103 is input from the terminal 101. If it is equal to the shift amount Mw of the filter work area, no processing is performed. However, the shift amount M selected by the shift amount determination circuit 103 is the shift amount Mw input from the terminal 101.
If it is smaller than the difference, the process shifts all the data in the work area to the right by the difference (Mw-M) bits to equalize the shift amount from the input signal with the data of the block.

The next band division filter 106 comprises a filter such as a so-called QMF. In the band division filter 106, the sample data floating circuit 1 is used.
The data up-shifted in 04 is divided into 0-10 kHz band and 10-20 kHz band in the filter work area shifted in the filter work area data shift amount adjusting circuit 105. 10k to 20
The 256 data in the kHz band are sent to the high frequency sample buffer 110.

The data in the band of 0 to 10 kHz divided by the band division filter 106 is then sent to the band division filter 107 which is also a filter such as QMF, and is further divided into two. The 128 pieces of data in the band of 0 to 5 kHz divided by the band division filter 107 are sent to the low-frequency sample buffer 108, and 5 kHz.
128 pieces of data in the band of 10 kHz are sent to the mid-range sample buffer 109.

Here, in this embodiment, as the band division filter, the filters such as the above QMF are subordinately connected in a cascade form and used. However, the above filter work area data / shift amount adjusting circuit 105 and a filter which will be described later. The shift operation in the work area data floating circuit 119 is performed on the data of all the filter work areas even when there are a plurality of filters in this way.

Next, the sample buffer 108 of each band,
The sample data of each band from 109 and 110 are sent to the corresponding block floating canceling circuits 112, 113 and 114 of the block floating canceling unit, respectively. Each block floating release circuit 112, 1
In steps 13 and 114, the supplied sample data is right-shifted by the shift amount selected by the shift amount determining circuit 103, that is, M bits, to restore the input level. Also, as mentioned above,
If a multiplier other than a power of 2 is used during floating, the block floating is not released by the right shift, but all the samples are divided by the multiplier. The output data of each block floating cancellation circuit 112, 113, 114 is sent to the corresponding orthogonal transformation circuit 115, 116, 117, respectively.

Further, the sample buffer 108 of each band,
The sample data of each band from 109 and 110 is also sent to the orthogonal transform block size determination circuit 111. The orthogonal transform block size determination circuit 111 uses the data of each band from the sample buffers 108, 109, and 110 of each band to determine the block size of the orthogonal transform in each band based on human hearing. The information indicating the block size of the orthogonal transformation is sent to the orthogonal transformation circuits 115, 116, 117 corresponding to each band and the output terminal 1
To 23.

Here, in the above orthogonal transform, generally, the larger the block size at the time of the orthogonal transform is, the higher the degree of concentration of the spectrum is, and therefore the effective coding can be performed. For example, in the case of an input signal or the like in which the level changes abruptly, such as in the attack part, a quantum called a pre-echo is generated in a small level part before and after (particularly in front of) the attack part if the block size of the orthogonal transformation remains large. Noise is easy to hear.

Therefore, in the present embodiment, the block size is adaptively changed according to the input signal, so that the encoding is effectively performed while preventing the deterioration of the sound quality. That is, the orthogonal transform block size determination circuit 1
11, the shortest shift amount similar to the above in each band is calculated every 2.5 ms, and when there is a place where the shortest shift amount sharply decreases by, for example, 4 bits or more, the amplitude of the signal rapidly increases. Assuming that there was
For example, the orthogonal transform block size is halved or ¼. Other than this, various concrete methods of determining the block size can be considered, but the method is not particularly limited here. Further, if there is a constraint on the hardware, the orthogonal transform block size may not be made variable in this way, and orthogonal transform may be performed with a fixed block size.

In this embodiment, the floating canceling section is carried out before entering the orthogonal transform section. However, when block floating processing is carried out also in the orthogonal transform section, for example, the floating canceling is carried out by the orthogonal transform section. It may be performed stepwise during the calculation, or in some cases, the floating may be released after the orthogonal transformation. Here, there is no particular limitation as to where the floating is released.

Next, according to the orthogonal transform block size in each band determined by the orthogonal transform block size determining circuit 111, the orthogonal transform circuits 115, 116 and 117 transform the discrete cosine which is an example of the orthogonal transform. Transform (Modefied Discrete Cosine Transform: MDC
T) is performed, where the time series data of each band is converted into spectrum data on the frequency axis.

Regarding the MDCT (Transform Discrete Cosine Transform), for example, the document “Time Domain Aliasing
Subband / Transform Coding Using Cancellation-Based Filter Bank Design "(^ Subband / Transform Coding
Using Filter Bank Designs Based on Time Domain Ali
asing Cancellation, "JPPrincen ABBradley, Uni
v. of Surrey Royal Melbourne Inst. of Tech. ICASSP
1987).

As described above, each orthogonal transformation circuit 115,
The spectrum data of each band subjected to the orthogonal transform calculation at 116 and 117 is sent to the adaptive bit allocation encoding circuit 120. In the adaptive bit allocation encoding circuit 120, for example, for each critical band,
The normalization coefficient, that is, the maximum value of the absolute value of the spectrum signal contained therein, normalizes each spectrum signal, and the normalized spectrum signal is masked by quantization noise of the quantization noise. Requantization is performed with the number of bits only, and the requantized spectrum signal is output to the output terminal 121 together with the normalization coefficient obtained for each critical band and the number of bits used for the requantization. To do.

On the other hand, in the shortest shift amount calculation circuit 118 of the work area floating portion, the shortest shift amount calculation is performed for all the data in the filter work area after the filter calculation in each of the band division filters 106 and 107 in the above block. As in the case of the circuit 102, the maximum value or its approximate value is detected, and the number of times mx at which the left shift is possible is calculated until the maximum value or the like becomes the operation word length excluding the code part of the encoding apparatus of this embodiment. . Further, in the shortest shift amount calculation circuit 118, the shortest shift amount Mx = (mx-n) is calculated with a margin of n bits, as in the shortest shift amount calculation circuit 102.

In the next filter work area data floating circuit 119, this shift amount Mx is used,
As in the case of the sample data floating circuit 104, each data is left-shifted by Mx bits to perform the floating process.

Further, in the next work area shift amount calculation circuit 124, the shift amount M of the shift amount determination circuit 103 and the shortest shift amount Mx obtained by the shortest shift amount calculation circuit 118 are added together to temporally 1
The shift amount Mw ′ from the input signal of the data in the filter work area is calculated for use in the processing in the subsequent block and is output to the terminal 122.

This is the end of the processing of the apparatus of this embodiment.

Next, the flowchart of FIG. 2 shows a procedure for implementing the processing of the block floating unit in the configuration of FIG. 1 by software.

In FIG. 2, the step corresponding to the shortest shift amount calculation circuit 102 of FIG.
At 11, the absolute value of each word is calculated. Further, in the next step S12, the maximum value, which is 0 as an initial value at the beginning of the process, is compared with the absolute value. If it is determined in step S12 that the absolute value is greater than or equal to the maximum value, the process proceeds to step S13, and in step S13, the absolute value is substituted as the maximum value. On the other hand, if it is determined in step S12 that the absolute value is not greater than or equal to the maximum value, the process proceeds to step S14
Determines whether all words have been completed. If it is determined in step S14 that the calculation of all words is not completed, the process returns to step S11, and if it is determined that the calculation is completed, the process proceeds to the next step S15.

The shortest shift amount calculation circuit 1 shown in FIG.
In each step corresponding to 02, as described above, instead of obtaining the maximum value in steps S12 and S13, the logical sum of absolute values of the words can be obtained. This eliminates the need to detect the maximum absolute value in the block, and the floating multiplier, that is, the shift amount can be obtained by a simple process of taking the logical sum of the absolute values in the block. In addition, this can reduce the number of steps when it is implemented by software by a microprogram, and accordingly high-speed processing can be achieved.

In the next step S15, the above step S
The maximum value obtained up to 14 is shifted to the left. In the next step S16, the most significant bit (MS
It is determined whether or not B) becomes "1", and if "1" is not detected in the MSB in this step S16 (NO), the process returns to step S15, and
When it is determined that "1" is detected, the number of shifts up to that time is set to mb, and the process proceeds to the next step S160.

In step S160, the extra bit number n for preventing overflow is subtracted from mb to obtain the maximum shiftable amount Mb, and the process proceeds to the next step S17. In step S17, it is determined whether or not the value is a positive value. When it is determined that the value is positive, the process proceeds to step S19, and when it is determined that the value is not positive, the process proceeds to step S18. In step S18, M is forced.
When b = 0, the process proceeds to step S19. The above steps correspond to the shortest shift amount calculation circuit 102 of FIG.

The following steps S19 to S21 correspond to the shift amount determining circuit 103 in FIG. Step S
In FIG. 19, the shortest shift amount Mb in this block is compared with the work area data shift amount Mw, and Mb
Is greater than or equal to Mw, the shift amount M in this block is determined to be Mw in step S20, and step S2
4 and conversely, if Mb is less than Mw, step S2
In step 1, the shift amount M is set to Mb, and the process proceeds to step S22.

Then, in step S22, the data in the work area, which has been left-shifted by Mw bits in the immediately preceding block in time, is right-shifted by (Mw-M) bits, and in the next step S23, in the work area. Processing of the filter work area data shift amount adjusting circuit 105 of FIG. 1 in which it is determined whether or not all the words have been completed, and if not completed, the processing returns to step S22, and if completed, the processing proceeds to step S24. I do.

In step S24, the time-series sample data is left-shifted by M bits, which is the shift amount determined in the block. In step S25, it is determined whether or not this process is completed for all words. If not completed, the process returns to step S24, and when completed, the process corresponding to the sample data floating circuit 104 in FIG. 1 is completed. The processing of the entire block floating unit is also ended at the same time.

Next, FIG. 3 shows a circuit configuration when the maximum value of absolute values in the process of the block floating unit in FIG. 1, that is, the process in FIG. 2 is approximated by the logical sum thereof.

In FIG. 3, digital time-series sample data is supplied to the input terminal 1. This sample data is sent to the absolute value calculation circuit 2, the absolute value of each word is calculated, and sent to the logical sum (OR) circuit 3 for obtaining the approximate value of the maximum value.

The data from the OR circuit 3 is sent to the memory 4 which stores one word as a latch or a register,
The output data from the memory 4 is returned to the OR circuit 3 and logically ORed with the absolute value of the current word from the absolute value calculation circuit 2. That is, the logical sum operation output from the OR circuit 3 is delayed by one word in the memory 4 and logically summed with the input current word, whereby the logical sum of the respective words is sequentially and sequentially taken.

The memory 4 is reset (zero-cleared) each time one block of 512-word (sample) data is input, and as a result, the logical sum of all absolute values of one-block, 512-word (sample) is taken. become.

The OR output data from the OR circuit 3 is sent to the shift amount detection circuit 5. In this shift amount detection circuit, the number of digits until "1" appears for the first time when each bit is viewed from the most significant bit or the OR output data is left-shifted to the most significant bit (MSB) for the first time.
The shift amount until just before 1 "appears is detected. That is, as the value of each digit of the logical sum output of the absolute value of each word in one block, the digit with" 1 "in any word is"
1 ", and only the digits that are" 0 "in any word are"
This means that the number of significant digits of the logical sum output (the number of digits ignoring "0" from the most significant digit) becomes equal to the number of significant digits of the maximum absolute value in the block. It is equal to the shift amount based on the maximum absolute value of the above, and the value obtained by subtracting n as a margin of the number of digits to prevent overflow from the shift amount detected as described above is output as the maximum shift amount possible for this block. .

The shift amount determining circuit 7 is supplied with the shift amount of the filter work area data from the input terminal 6. The shift amount determining circuit 7 compares the shift amount of the work area data with the maximum shift amount of the output of the shift amount detecting circuit 5 and selects the one that is not larger, and shift circuit 9 and work area data shift circuit 11 are selected. Output to.

Further, each data sent to the shift circuit 9 through the delay circuit 8 is shifted or floating-processed according to the shift amount information from the shift amount determining circuit 7 and sent to the output terminal 10. If the shift amount sent from the shift amount determining circuit 7 is equal to the shift amount of the work area supplied from the input terminal 6, nothing is done. On the contrary, if different, the shift amount sent from the shift amount determining circuit 7 is subtracted from the shift amount supplied from the input terminal 6, and the data in the work area is right-shifted by the number of bits of the difference.

Next, the flow chart of FIG. 4 shows a procedure for realizing the work area floating unit in FIG. 1 by software.

In FIG. 4, from step S41 to step S46, for each data in the filter work area, step S11 to step S1 in FIG.
By performing the same processing as up to 6, the shortest shift amount m
Find x.

Next, in step S47, the maximum possible shift amount Mx = mx-n in this work area is obtained. Here, as in the case of FIG. 2, n is the number of spare bits taken to prevent overflow.

Then, in the next step S48, this Mx
It is determined whether the value of is 0, and if it is 0, the floating process is not performed, and the process proceeds to step S51. M
If x is not 0, the process proceeds to step S49.

In step S49, the data in the work area, which has been left-shifted by M bits, is left-shifted by Mx bits, as compared with the time-series sample at the time of input. In the next step S50, it is determined whether or not all the data in the work area has been completed. If not completed, the process returns to step S49, and if completed, the process proceeds to step S51.

Finally, in step S51, the shift amount (M + Mx) from the original time-series sample is calculated and output, and the process ends.

Next, a decoding device corresponding to the coding device of this embodiment will be described with reference to FIG.

In FIG. 5, the input terminal 500 is
Encoded data on the frequency axis obtained from the output terminal 121 of FIG. 1 is supplied, and this encoded data is first sent to a decoding circuit 501 for adaptive bit allocation and subjected to decoding processing, and low band and middle band respectively. , And are sent to spectrum buffers 502, 503, and 504 provided corresponding to high frequencies. The data of each buffer 502, 503, 504 is
Inverse transform processing (inverse orthogonal transform processing) of the MDCT, respectively.
Each inverse orthogonal transform circuit (IMDCT circuit) 505, 5
06, 507, and these inverse orthogonal transform circuits 505,
At 506 and 507, the orthogonal transform is canceled according to the orthogonal transform block size data supplied from the input terminal 525.

In the next shortest shift amount calculation circuit 508, the absolute value of the low-frequency sample from the inverse orthogonal transform circuit 505 is taken, and the maximum value or an approximate value of the maximum value is calculated. Here, instead of obtaining the maximum value itself, the absolute value of this low-frequency sample may be ORed as an approximate value of the maximum value. Further, the shortest shift amount calculation circuit 508 uses the maximum value obtained as described above or its approximate value, and the number of times the maximum value can be shifted to the left until it becomes the post-computation length excluding the code of the decoding device. pL
And the shortest shift amount NL is set to (pL-q). When the shortest shift amount NL has a negative value, it is forcibly set to 0 and sent to the shift amount determination circuit 512. Note that q is a constant set in consideration of the operation word length of the decoding device and the filter coefficient in order to prevent overflow during the filter operation, and may be set to 0 or a positive value.

Also in the shortest shift amount calculation circuits 509 and 510, the same processing as that of the shortest shift amount calculation circuit 508 is performed on the samples in the middle and high ranges, and the shortest shift amount calculation circuit 509 performs the shortest shift in the middle range. The amount NM is obtained, and the shortest shift amount calculation circuit 510 obtains the shortest shift amount NH in the high frequency range. These shortest shift amount calculation circuits 509 and 510
Each shortest shift amount from 1 to 3 is also sent to the shift amount determining circuit 512.

In the shift amount determining circuit 512, the shortest shift amount N sent from the shortest shift amount calculating circuits 508, 509, 510 is set as the shift amount N of the block.
L, NM, NH, and the smallest shift amount Nw of the filter work area supplied from the input terminal 511 are selected and sent to the floating circuits 513, 514, 515 provided for each band, The data is sent to the filter work area data / shift amount adjusting circuit 516 and the filter work area data / floating circuit 521.

Next, the floating circuits 513 and 51
In 4 and 515, a floating process is performed in which the data of each band is left-shifted by the shift amount N determined by the shift amount determining circuit 512. Here, in order to simplify the processing, a power of 2 is selected as the multiplier and this operation is performed by left shift, but in practice, not only the power of 2 but any value may be taken.

Further, in the work area floating unit for the block immediately preceding the block in time, the data in the work area is already the effective word length of the maximum absolute value of the data in the work area. Since it is left-shifted by q smaller than the operation word length of, the filter work area data floating circuit 516 performs processing when the shift amount N determined by the shift amount determining circuit 512 is equal to Nw. Absent. However, when the shift amount N determined by the shift amount determining circuit 512 is smaller than Nw, the difference (Nw
By performing a process of right-shifting all the data in the work area by -N) bits, the shift amount from the input signal is made equal to the data of the block.

The data which has been subjected to the floating process as described above is the band division filters 106 and 107.
The signals are combined by the band combining filters 517 and 518 composed of filters such as IQMF that perform the inverse processing of the above, and sent to the floating canceling circuit 519. The floating canceling circuit 519 shifts the shift amount determined by the shift amount determining circuit 512, that is, N bits to the right, to be returned to the level at the time of input and output to the terminal 523 as a reproduction signal. Further, as described above, when the multiplier is set to a value other than the power of 2 in the floating, the block floating is not released by the right shift but by dividing all the samples by the multiplier. .

Next, in the shortest shift amount calculation circuit 520 of the work area data floating unit, the shortest shift amount is further calculated for all the data in the filter work area after the filter calculation in the band synthesis filters 517 and 518 in the above block. Calculation circuit 50
8, 509, and 510, the maximum value or its approximate value is detected, and the maximum number of times m that can be left-shifted until the maximum value becomes the operation word length excluding the code part of the decoding device.
Calculate y.

Then, in the shortest shift amount calculation circuit 520, the above-mentioned shortest shift amount calculation circuits 508, 509, 510.
The shortest shift amount Ny = (m
Calculate y−q). In the next filter work area data / floating circuit 521, by using this shift amount Ny, the floating circuits 513, 514, 5
As in the case of 15, the data is left-shifted by Ny bits to be subjected to floating processing and sent to the work area shift amount calculation circuit 522.

This work area shift amount calculation circuit 522
In (1), the shift amount N determined by the filter work area data floating circuit 512 and the shortest shift amount Ny determined by the shortest shift amount calculation circuit 520 are added together to be used in a block one block later in time. Therefore, the shift amount Ny ′ from the input signal of the data of the filter work area is obtained, and the shift amount Ny ′ is output to the terminal 524, whereby the processing ends.

Although a so-called QMF filter is subordinately connected in cascade as the band synthesizing filter in this embodiment, the filter work area data shift amount adjusting circuit 516 and the filter work area data floating circuit are used. The shift operation in the circuit 521 is performed on the data in all the filter work areas even when there are a plurality of filters in this way.

Further, the present invention is not limited to the above-mentioned embodiment, but can be applied to a signal processing device for not only audio PCM signals but also digital voice (speech) signals.

[0078]

According to the digital signal processing method and apparatus of the present invention, the input signal is divided into blocks, for example, every fixed number of samples in the filter calculation as the predetermined calculation, and the absolute value in this block is the maximum. Comparison of fixed-point arithmetic, etc. by detecting the maximum value that is a large sample and applying a method called block floating, which controls the gain by multiplying the sample in the block by a predetermined coefficient according to the size of this sample It is possible to reduce the calculation error at the time of a small input and improve the dynamic range even in the encoding process and the decoding process with less dynamic processing.

Further, according to the digital signal processing method and device of the present invention, in the block floating, as a simpler method for multiplying each sample by a common coefficient, bit shift is used in units of 6 dB, for example. By using the floating, it is possible to further simplify the encoding process and the decoding process, and in the case of a device, reduce the hardware scale and speed up the process.

Then, instead of detecting the maximum value of the samples in each block, the logical sum of the samples in each block is taken and used as an approximate value of this maximum value, thereby further performing the encoding process and the decoding process. And the hardware scale can be reduced in the case of a device.

That is, according to the digital signal processing method and apparatus of the present invention, when performing a non-blocking operation such as a filter operation, the input signal is divided into blocks for every fixed sample, and each block is most suitable before the operation. It is possible to improve the dynamic range at the time of small input while preventing overflow by multiplying each sample by such a coefficient to perform the calculation and then dividing each sample by the multiplier after the calculation.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a high-efficiency encoding apparatus as an embodiment for performing encoding processing of a digital signal processing method of the present invention.

FIG. 2 is a flow chart for explaining the operation of the block floating process of the embodiment of the present invention.

FIG. 3 is a block circuit diagram for realizing the operation of the block floating process according to the embodiment of the present invention.

FIG. 4 is a flowchart for explaining the operation of a filter work area floating process according to the embodiment of the present invention.

FIG. 5 is a block circuit diagram showing a high-efficiency code decoding device as an embodiment for performing a decoding process of the digital signal processing method of the present invention.

[Explanation of symbols]

102, 118, 508, 509, 510, 520 Shortest shift amount calculation circuit 103, 512 Shift amount determination circuit 104 Sample data floating circuit 105, 516 Filter work area Data shift amount adjustment circuit 106, 107 Band division filter 108 Low band Sample buffer 109 Middle range sample buffer 110 High range sample buffer 111 Orthogonal transform block size determination circuit 112, 113, 114, 519 Floating cancellation circuit 115, 116, 117 Orthogonal transform circuit (MDCT circuit) 119, 521 Filter work area data floating Circuits 124 and 522 Work area shift amount calculation circuit 120 Adaptive bit allocation encoding circuit 501 Adaptive bit allocation decoding circuit 502 Low band spectrum buffer 503 Mid band spectrum Torr buffer 504 high band spectrum buffer 505, 506, 507 inverse orthogonal transform circuit (IMDCT
Circuit) 513, 514, 515 Floating circuit 517, 518 Band synthesis filter

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H04N 5/60 Z 7/24

Claims (43)

[Claims] 1. A digital signal processing method for recording or transmitting an input signal, which is subjected to a predetermined non-blocking frequency analysis and an encoding process for quantizing the analysis output, and then recorded or transmitted. When the maximum level of the absolute value of the sample of the input signal in each block is smaller than a predetermined threshold in each block, all samples of the input signal of the block are multiplied by a predetermined coefficient. After that, a predetermined calculation is performed, and after the predetermined calculation, each sample is divided by the predetermined coefficient. 2. A predetermined non-blocking frequency analysis is performed on an input signal, the analysis output of the non-blocking frequency analysis is blocked to perform a predetermined blocking frequency analysis, and the analysis output of the blocking frequency analysis is quantized. In the digital signal processing method of recording or transmitting after performing the encoding process, when the maximum absolute value of the sample of the input signal in each block is smaller than the predetermined threshold, the input signal of the block is input. A digital signal processing method, characterized in that all the samples are multiplied by a predetermined coefficient, a predetermined operation is performed, and each sample is divided by the predetermined coefficient after the predetermined operation. 3. The digital signal processing method according to claim 1, wherein a logical sum of absolute values of samples of input signals of the block, which is an approximation of the maximum value, is used as the maximum value. 4. A digital signal processing method for performing coding by performing predetermined non-blocking frequency analysis on an input signal, wherein the input signal is divided into blocks, and the absolute value of the sample of the input signal in each block. Is smaller than a predetermined threshold, all samples of the input signal of the block are multiplied by a predetermined coefficient, then a predetermined calculation is performed, and each sample is divided by the coefficient after the predetermined calculation. A digital signal processing method comprising: 5. In each of the blocks, when the level of the maximum absolute value of the samples of the input signal is smaller than a predetermined threshold, all samples of the input signal of the block are multiplied by a predetermined coefficient, 5. The digital signal processing method according to claim 4, wherein, as the maximum value, a logical sum of absolute values of samples of input signals of the block, which is an approximation of the maximum value, is used. 6. The digital signal processing method according to claim 1, wherein a maximum absolute value in a predetermined word length is used as the threshold. 7. The threshold and the coefficient are set from an operation word length of the encoding process and a coefficient of the predetermined operation, according to any one of claims 1 to 5. The digital signal processing method described in. 8. The digital signal processing method according to claim 1, wherein the predetermined coefficient is variable for each block. 9. The digital signal processing method according to claim 8, wherein a number obtained by dividing the threshold by the maximum value is used as the predetermined coefficient. 10. The digital signal processing method according to claim 8, wherein a power of 2 is used as the predetermined coefficient, and a bit shift is used as the multiplication. 11. The bit shift is performed such that the word length of the maximum value after the shift is shorter than the operation word length excluding the sign bit of the encoding process by a constant n. Digital signal processing method. 12. The digital signal processing method according to claim 11, wherein the constant n is 1. 13. The digital signal processing method according to claim 1, wherein the predetermined arithmetic operation is performed in fixed point. 14. The digital filter calculation is performed as the predetermined calculation, and a quadrature mirror filter is used for the digital filter calculation, according to any one of claims 1 to 5. Digital signal processing method. 15. The digital signal processing method according to claim 14, wherein the filter operation is performed by subordinately connecting filters for dividing the band of the supplied signal into two. 16. The digital signal processing method according to claim 15, wherein the filter calculation is performed by further dividing the output on the low band side obtained by dividing the band by the first filter into two parts by the second filter. Signal processing method. 17. The digital signal processing method according to claim 1, wherein the orthogonal transform process is performed for each band after the predetermined calculation is performed. . 18. The digital signal processing method according to claim 17, wherein the block size of the orthogonal transform processing is variable. 19. The digital signal processing method according to claim 18, wherein a transform discrete cosine transform process is used as the orthogonal transform process. 20. A digital signal according to claim 1, wherein the operation word length of the encoding process is substantially the same as the word length of the input / output sample. Signal processing method. 21. A decoding process of decoding a recorded or transmitted signal after performing a predetermined non-blocking frequency analysis on an input signal and performing a coding process of quantizing the analysis output. In the digital signal processing method, the recorded or transmitted signal is divided into blocks for every plural samples, and when the level of the maximum absolute value of the sample of the signal in each block is smaller than a predetermined threshold, all the signals in the block are Is multiplied by a predetermined coefficient, a predetermined calculation is performed, and each sample is divided by the predetermined coefficient after the predetermined calculation. 22. A predetermined non-blocking frequency analysis is performed on an input signal, the analysis output of the non-blocking frequency analysis is blocked to perform a predetermined blocking frequency analysis, and the analysis output of the blocking frequency analysis is quantized. In a digital signal processing method for performing a decoding process for decoding a signal recorded or transmitted after performing an encoding process, an inverse blocking frequency analysis corresponding to the above predetermined blocking frequency analysis is performed, and When the level of the maximum absolute value of the samples of the output of the inverse blocking frequency analysis is smaller than the predetermined threshold, after multiplying all the samples of the output of the inverse blocking frequency analysis of the block by the predetermined coefficient. , Perform a predetermined calculation, and perform each sample after the above predetermined calculation Digital signal processing method characterized by dividing the serial predetermined coefficient. 23. The digital signal processing method according to claim 21, wherein as the maximum value, a logical sum of absolute values of inverse blocking frequency analysis outputs of the blocks, which is an approximation of the maximum value, is used. 24. The digital signal processing method according to claim 21, 22, or 23, wherein a maximum absolute value in a predetermined word length is used as the threshold. 25. The threshold and the coefficient are set from an operation word length of the decoding process and a coefficient of the predetermined operation.
The described digital signal processing method. 26. The digital signal processing method according to claim 21, 22 or 23, wherein the predetermined coefficient is made variable for each block. 27. The digital signal processing method according to claim 26, wherein a number obtained by dividing the threshold by the maximum value is used as the predetermined coefficient. 28. The digital signal processing method according to claim 26, wherein a power of 2 is used as the predetermined coefficient, and a bit shift is used as the multiplication. 29. The bit shift is performed so that the word length of the maximum value after the shift is shorter than the operation word length excluding the code part of the decoding process by a constant n. Digital signal processing method. 30. The digital signal processing method according to claim 29, wherein the constant n is 1. 31. The digital signal processing method according to claim 21, 22, or 23, wherein the predetermined arithmetic operation is performed with a fixed point. 32. The digital signal processing method according to claim 21, 22, or 23, wherein a digital filter operation is performed as the predetermined operation, and an inverse quadrature mirror filter is used for the digital filter operation. 33. The digital signal processing method according to claim 32, wherein the filter operation is performed by subordinately connecting filters for synthesizing the divided bands. 34. In the filter calculation, the first filter combines two low-frequency bands, and the second filter combines the first band.
34. The digital signal processing method according to claim 33, wherein the output of the filter and the band on the highest band side are configured to obtain the entire band. 35. The digital signal processing method according to claim 21, 22, or 23, wherein inverse orthogonal transform processing is performed for each of the bands. 36. The digital signal processing method according to claim 35, wherein the block size of the inverse orthogonal transform process is variable. 37. The inverse transform discrete cosine transform process is used as the inverse orthogonal transform process.
The described digital signal processing method. 38. The digital signal processing method according to claim 21, 22, or 23, wherein the operation word length of the decoding process is substantially the same as the word length of the input / output sample. 39. A digital signal processing device for recording or transmitting after performing a predetermined non-blocking frequency analysis on an input signal and performing an encoding process for quantizing the analysis output, Each sample is divided into blocks, and when the level of the maximum absolute value of the sample of the input signal in each block is smaller than a predetermined threshold, all samples of the input signal of the block are multiplied by a predetermined coefficient. Thereafter, a digital signal processing device is provided, which has a calculation means for performing a predetermined calculation and dividing each sample by the predetermined coefficient after the predetermined calculation. 40. A predetermined non-blocking frequency analysis is performed on an input signal, the analysis output of the non-blocking frequency analysis is blocked to perform a predetermined blocking frequency analysis, and the analysis output of the blocking frequency analysis is quantized. In a digital signal processing device that performs recording or transmission after performing encoding processing, when the level of the maximum absolute value of the sample of the input signal in each block is smaller than a predetermined threshold, the input signal of the block is input. A digital signal processing apparatus having a calculating means for multiplying all the samples by a predetermined coefficient, performing a predetermined calculation, and dividing each sample by the predetermined coefficient after the predetermined calculation. . 41. A decoding process for performing a predetermined non-blocking frequency analysis on an input signal, quantizing the analysis output, performing an encoding process, and then decoding a recorded or transmitted signal. In a digital signal processing device for performing, the recorded or transmitted signal is divided into blocks for each of a plurality of samples, and when the level of the maximum absolute value of the sample of the signal in each block is smaller than a predetermined threshold, A digital signal processing apparatus comprising: a calculating unit that multiplies all samples by a predetermined coefficient, performs a predetermined calculation, and divides each sample by the predetermined coefficient after the predetermined calculation. 42. A predetermined non-blocking frequency analysis is performed on an input signal, the analysis output of the non-blocking frequency analysis is blocked to perform a predetermined blocking frequency analysis, and the analysis output of the blocking frequency analysis is quantized. In a digital signal processing device that performs a decoding process of decoding a recorded or transmitted signal after performing a coding process, an inverse blocking frequency analysis corresponding to the above predetermined blocking frequency analysis is performed, and in each block. When the maximum absolute value of the sample of the output of the inverse blocking frequency analysis is smaller than a predetermined threshold, all samples which are the output of the inverse blocking frequency analysis of the block are multiplied by a predetermined coefficient. rear,
A digital signal processing apparatus comprising: a calculation unit that performs a predetermined calculation and divides each sample by the predetermined coefficient after the predetermined calculation. 43. A digital signal processing device for performing a predetermined non-blocking frequency analysis on an input signal, wherein the input signal is divided into blocks, and the absolute value of the sample of the input signal in each block is a predetermined threshold. When it is smaller than the hold, it has a calculating means for multiplying all the samples of the input signal of the block by a predetermined coefficient and then performing a predetermined calculation and dividing each sample by the coefficient after the predetermined calculation. A digital signal processing device characterized by the above.