JPH07202126A - Semiconductor device - Google Patents

Abstract

PURPOSE:To protect an output transistor and an internal circuit from electrostatic breakdown by a method wherein the parasitic resistance, from the metal terminal in a protective transistor to the first reference potential or the second reference potential, is made smaller than the parasitic resistance from the metal terminal in the output transistor to the first reference potential. CONSTITUTION:An output transistor 22, which controls the potential of an input-output signal, is provided between an output terminal 21, which is the metal terminal used to connect an outer circuit, and the resistor 23 of an inner circuit 201, and a protective transistor 24, with which a discharge path is formed, and a protective diode 25 are provided to protect the inner circuit and the output transistor 22 from a surge current. As the resistance value of the parasitic resistor 202 of the protective transistor is smaller than the resistance value of the parasitic resistor 203 of the output transistor, only the protective transistor, having large current resistivity, is put in operation even when a high voltage pulse is applied to the metal terminal. Accordingly, the most of the surge current is allowed to flow to the protective transistor 24.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a protection transistor for protecting an internal circuit from electrostatic breakdown.

[0002]

2. Description of the Related Art Conventionally, as a technique for protecting a semiconductor integrated circuit from an electrostatic breakdown phenomenon, for example, Japanese Patent Laid-Open No. 4-1220 is known.
The technique disclosed in Japanese Patent Publication No. 59 is known. Hereinafter, this known technique will be described with reference to the drawings. FIG. 5 shows a circuit configuration of this conventional semiconductor device, FIG. 6 shows a pattern layout of the device, and FIG. 7 shows a sectional view taken along line bb of FIG.

In FIG. 5, when a high voltage pulse due to invasion of electrostatic charges is applied to the input / output terminal 1 which is a metal terminal,
Surge current flows through the output transistor 2 and the wiring 100 to the gate drive circuit, or the input resistor 3 and the wiring 10
The semiconductor device is destroyed by flowing through 1 to the internal circuit. Therefore, the protection transistor 4 forming a discharge path is provided near the input / output terminal 1 of the internal circuit. The protection transistor 4 is composed of a bipolar transistor having a large withstand current, and becomes conductive when a high voltage pulse is applied to clamp the applied voltage.

In FIG. 7, the output transistor 2 is P
-Type LDD (Lightly Doped Dr) having N-type diffusion layers 6 and 7 and a gate electrode 8 formed on the surface of a semiconductor substrate 5
ain) structured MOSFET. Note that P
A gate oxide film 15 is interposed between the type semiconductor substrate 5 and the gate electrode 8. The N-type diffusion layer 6 serving as the source of the output transistor 2 is connected to the ground line by the aluminum wiring 9, and the N-type diffusion layer 7 serving as the drain is connected to the input / output terminal 1 by the aluminum wiring 10. The gate electrode 8 and the aluminum wirings 9 and 10 are insulated by the sidewall insulating film 16 and the interlayer insulating film 17.

The protection transistor 4 is a P-type semiconductor substrate 5
Is a base, the N-type diffusion layer 7 is a collector, and the N-type diffusion layer 11 is an emitter. The N-type diffusion layer 7 and the N-type diffusion layer 11 are insulated by the field oxide film 18. The N-type diffusion layer 7 which is the collector of the protection transistor 4 is connected to the input / output terminal 1 by the aluminum wiring 10, and the N-type diffusion layer 11 which is the emitter of the protection transistor 4 is connected to the ground line by the aluminum wiring 12. It In such a semiconductor device, the drain of the output transistor 2 and the collector of the protection transistor 4 are commonly formed as the N-type diffusion layer 7,
The structure is such that the pattern area is reduced and no extra capacitance is added to the input / output terminal 1.

Further, as shown in FIGS. 5 and 6, in the conventional semiconductor device, the resistance value of the parasitic resistance 103, which is determined by the distances S1 and S2 between the gate electrode 8 of the output transistor 2 and the contacts 13 and 14, is , The resistance value of the parasitic resistance 102 determined by the distances S3 and S4 between the contacts 14 and 19 and the field oxide film 18, and the effective channel length L1 of the output transistor 2 is equal to the effective base width of the protection transistor 4. It is about the same as L2.

[0007]

In the conventional semiconductor device described above, the output transistor operates as a parasitic bipolar transistor when a high voltage pulse resulting from the intrusion of electrostatic charges is applied to the input / output terminal. That is, the surge current input to the input / output terminal does not always flow through the protection transistor, but also through the output transistor or internal circuit to be protected, which causes a problem that the semiconductor device is destroyed.

When an output transistor having an LDD structure is used to form the integrated circuit of the semiconductor device, the electrostatic breakdown resistance of the output transistor is reduced due to the structure, so that the semiconductor device is not statically damaged. There is a problem that the electric breakdown phenomenon is likely to occur.

The present invention has been made to solve the above problems, and provides a semiconductor device capable of protecting an output transistor and an internal circuit from an electrostatic breakdown phenomenon with a circuit configuration having a minimum pattern area. The purpose is to

[0010]

To achieve the above object, a semiconductor device of the present invention is provided with a metal terminal provided on a semiconductor substrate and a metal terminal formed in one conductivity type region of the semiconductor substrate. An output transistor having a reverse conductivity type first diffusion layer connected to a terminal as a drain and a reverse conductivity type second diffusion layer connected to a first reference potential as a source; and the first diffusion layer. An element isolation insulating film provided in the vicinity of the first diffusion layer and a third diffusion layer of the opposite conductivity type, which is connected to the first reference potential or the second reference potential, and is separated from the first diffusion layer. The first diffusion layer is the collector,
A protection transistor based on the one conductivity type region, wherein a parasitic resistance from the metal terminal in the protection transistor to the first reference potential or the second reference potential is from the metal terminal in the output transistor It is characterized in that it is smaller than the parasitic resistance up to the first reference potential. It is desirable that the metal terminal be an input / output terminal for connecting an external circuit and an internal circuit of the semiconductor substrate.

In order to make the parasitic resistance of the protection transistor smaller than that of the output transistor, the distance from the connection between the metal terminal and the first diffusion layer to the element isolation insulating film, and the first From the connection between the metal terminal and the first diffusion layer, the length obtained by combining the distance from the connection between the reference potential or the second reference potential and the third diffusion layer to the element isolation insulating film is calculated as follows. It is possible to employ means for forming the distance to the gate electrode of the output transistor and the distance from the connecting portion between the first reference potential and the second diffusion layer to the gate electrode of the output transistor to be shorter than the total length. desirable.

In the semiconductor device of the present invention, by making the effective base length of the protection transistor shorter than the effective channel length of the output transistor, the function of the protection transistor can be more effectively exerted, and the metal terminal and The connection portion with the first diffusion layer and the first reference potential and the second
It is also possible to effectively utilize the function of the protection transistor by adopting a configuration in which a refractory metal silicide pad is interposed in the connection portion with the diffusion layer of. The present invention can be applied to the one conductivity type region as a well formed in the semiconductor substrate.

[0013]

In the semiconductor device of the present invention, the resistance value of the parasitic resistance of the protection transistor between the metal terminal and the first reference potential or the second reference potential is the output transistor between the metal terminal and the first reference potential. Since the resistance value is smaller than the resistance value of the parasitic resistance, the output transistor does not operate as a parasitic bipolar transistor even when a high voltage pulse due to the intrusion of electrostatic charges is applied to the metal terminal, and the protection transistor having a large current withstanding function mainly operates. Therefore, most of the surge current flows through the protection transistor, and the electrostatic breakdown withstand capability of the output transistor and the internal circuit is greatly improved.

If a structure is adopted in which the effective base length of the protection transistor is shorter than the effective channel length of the output transistor, surge current easily flows through the protection transistor, and the protection transistor can effectively function.
Further, when a configuration in which the refractory metal silicide pad is interposed at the connection portion between the metal terminal and the first diffusion layer and the connection portion between the first reference potential and the second diffusion layer, the refractory metal silicide pad is Since the resistance value of the parasitic resistance of the output transistor is increased, the electrostatic breakdown resistance of the output transistor can be increased without expanding the area of the diffusion layer.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of a semiconductor device according to the present invention will be described below with reference to the drawings. FIG. 1 shows a circuit diagram of an input / output circuit of a semiconductor device of this embodiment, FIG. 2 shows its pattern layout, and FIG. 3 shows a cross section taken along the line aa of FIG.

As shown in FIG. 1, in the semiconductor device of this embodiment, the potential of the input / output signal is placed between the input / output terminal 21 which is a metal terminal for connecting to an external circuit and the resistor 23 of the internal circuit 201. An output transistor 22 for controlling
A protection transistor 24 forming a discharge path for protecting the internal circuit and the output transistor 22 from a surge current,
And a protection diode 25 are provided.

As shown in FIG. 3, the output transistor 22 has 2 of the N type diffusion layers 27 on the surface of the P type semiconductor substrate 26.
7a, 27b, 27c and gate electrodes 28a, 28b
It is composed of an N-type LDD structure MOSFET. In addition, N which is the source region of the output transistor 22
The type diffusion layer 27b is connected to the first reference potential (ground potential) by the aluminum wiring 29, and the N-type diffusion layers 27a and 27c which are the drain regions are connected to the input / output terminal 21 by the aluminum wiring 30. P-type semiconductor substrate 26 and gate electrode 2
A gate oxide film 38 is interposed between 8a and 28b. Although the source of the output transistor 22 is connected to the ground line in this embodiment, the present invention is not limited to this, and the source may be connected to the reference potential of the high potential power supply line. Can be applied.

The gate electrode 28 of the output transistor 22
As shown in FIG. 2, a and 28b are connected to the wiring 200 to the gate drive circuit, and switch the conduction / non-conduction of the output transistor 22 by the drive signal from the gate drive circuit to control the potential of the input / output terminal 21. is doing. The gate electrodes 28a and 28b and the aluminum wirings 29 and 30 are insulated by the sidewall insulating film 36 and the interlayer insulating film 37.

The protection diode 25 is a PN diode composed of a P-type diffusion layer 31 and an N-type diffusion layer 27a. The P-type diffusion layer 31 is connected to the ground line by the aluminum wiring 29, and the N-type diffusion layer 27a is connected to the input / output terminal 21 by the aluminum wiring 30.

The protection transistor 24 has a P-type semiconductor substrate 26 as a base and an N-type diffusion layer 27c as a collector.
It is configured as an NPN bipolar transistor having the N-type diffusion layer 27d as an emitter. The N-type diffusion layer 27c and the N-type diffusion layer 27d are insulated by the field oxide film 32. The collector N-type diffusion layer 27c is connected to the input / output terminal 21 by an aluminum wiring 30, and the emitter N-type diffusion layer 27d is connected by an aluminum wiring 29 to a ground line.

In this embodiment, as shown in FIG. 2, from the gate electrode 28b of the output transistor 22 to the aluminum wiring 30.
To the contact 33 of the output transistor 22, the distance S11 from the gate electrode 28b to the contact 34 of the aluminum wiring 29 is 5 μm, and the distance S12 from the contact 33 of the output transistor 22 to the field oxide film 32 and the emitter of the protection transistor 24. The distance S13 from the contact 35 between the aluminum wiring 29 and the field oxide film 32 is 2.5 μm. As a result, assuming that the electric resistance of the diffusion layer is, for example, 50Ω per unit length and unit width, and the width of the output transistor 22 is 10 μm, the resistance value of the parasitic resistance 203 shown in FIG.
It becomes 0Ω, which is twice the resistance value of the parasitic resistance 202 of 25Ω. Further, in this embodiment, the effective channel length L10 of the output transistor 22 is formed to be 1.2 μm,
Set the effective base width L11 of the protection transistor 24 to 0.9 μ
and the effective channel of the output transistor 22 is made longer.

In the semiconductor device of this embodiment, the parasitic resistance 20
The resistance value of 3 is increased to form the output transistor 22 in a structure that does not easily operate as a parasitic bipolar transistor. Therefore, when a positive high-voltage pulse is applied to the input / output terminal 21, the protection transistor 24 having a large withstand current operates and becomes conductive. As a result, most of the surge current flows to the protection transistor 24, so that the electrostatic breakdown resistance of the output transistor 22 can be greatly improved. When a negative high voltage pulse is applied to the input / output terminal 21, a forward surge current flows through the protection diode 25, so that the output transistor 22 is protected.

Next, a semiconductor device according to the second embodiment of the present invention will be described. FIG. 4 is a diagram showing a pattern layout of this embodiment. The basic circuit configuration of the input / output unit of the semiconductor device of this embodiment is the same as that of the semiconductor device of the first embodiment.

The difference between this embodiment and the first embodiment is that the refractory metal silicide pad 40 is provided between the N-type diffusion layer 27 and the aluminum wiring 30 from the input / output terminal 21 or the aluminum wiring 29 from the ground line. Is interposed to increase the resistance value of the parasitic resistance 203 of the output transistor 22 without increasing the area of the diffusion layer. With such a configuration, the protection transistor 24 functions more effectively. Further, when the present embodiment is applied to the ultra-high speed LSI, the output transistor can obtain a very high electrostatic withstand capability.

In each of the above embodiments, the output transistor 22 is directly formed in the P-type semiconductor substrate 26, but the present invention is not limited to this.
The output transistor 22 may be formed in the well of No. 6. Further, although both the output transistor 22 and the protection transistor 24 are connected to the ground line of the reference potential, the invention is not limited to this, and one element may be connected to the reference potential of the high potential power supply line.

[0026]

As described above, according to the semiconductor device of the present invention, since the resistance value of the parasitic resistance of the protection transistor is smaller than the resistance value of the parasitic resistance of the output transistor,
Even if a high voltage pulse is applied to the metal terminal, only the protection transistor having a large withstand current operates and becomes conductive.
Therefore, most of the surge current flows to the protection transistor, and thus the electrostatic breakdown resistance of the output transistor is greatly improved. Moreover, since it is not necessary to add an extra capacitance or resistance element to the input / output circuit of the semiconductor device,
With the circuit configuration having the minimum pattern area, the output transistor and the internal circuit can be protected from the electrostatic breakdown phenomenon.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a circuit configuration of a first embodiment of a semiconductor device of the present invention.

FIG. 2 is a diagram showing a pattern layout of the circuit of the embodiment.

FIG. 3 is a sectional view taken along line aa of FIG.

FIG. 4 is a diagram showing a pattern layout of a circuit of a second embodiment of the semiconductor device of the present invention.

FIG. 5 is a circuit diagram showing a circuit configuration of an input / output unit of a conventional semiconductor device.

FIG. 6 is a diagram showing a pattern layout of a circuit of the semiconductor device.

7 is a sectional view taken along line bb of FIG.

[Explanation of reference numerals] 21 input / output terminal 22 output transistor 23 resistance 24 protection transistor 25 protection diode 26 P-type semiconductor substrate 27 (27a, 27b, 27c, 27d) N-type diffusion layers 28a, 28b Gate electrodes 29, 30 Aluminum wiring 31 P-type diffusion layer 32 Field oxide film 33, 34, 35 Contact 36 Side wall insulating film 37 Interlayer insulating film 38 Gate oxide film 40 Refractory metal silicide pad 200 Wiring to gate drive circuit 201 Wiring to internal circuit 202 Parasitic of protection transistor Resistor 203 Parasitic resistance of output transistor

Claims (6)

[Claims] 1. A metal terminal provided on a semiconductor substrate,
A second conductivity type second diffusion layer, which is formed in one conductivity type region of the semiconductor substrate and is connected to the metal terminal, is used as a drain, and is connected to a first reference potential. An output transistor having a diffusion layer as a source and an element isolation insulating film provided in the vicinity of the first diffusion layer separates the first diffusion layer from the first diffusion layer and sets the first reference potential or the second reference potential. A protection transistor having the connected third conductivity type diffusion layer as an emitter, the first diffusion layer as a collector, and the one conductivity type region as a base; A parasitic resistance up to a first reference potential or a second reference potential is applied from the metal terminal of the output transistor to the first reference potential.
The semiconductor device is characterized by being smaller than the parasitic resistance up to the reference potential. 2. The metal terminal is an input / output terminal for connecting an external circuit and an internal circuit of the semiconductor substrate.
The semiconductor device according to. 3. The distance from the connection between the metal terminal and the first diffusion layer to the element isolation insulating film and the connection between the first reference potential or the second reference potential and the third diffusion layer. The distance from the connecting portion between the metal terminal and the first diffusion layer to the gate electrode of the output transistor, the first reference potential, and the second reference potential. 3. The semiconductor device according to claim 1, wherein the length is shorter than the combined length of the distance from the connection portion with the diffusion layer to the gate electrode of the output transistor. 4. The semiconductor device according to claim 1, wherein an effective base length of the protection transistor is shorter than an effective channel length of the output transistor. 5. A refractory metal silicide pad is interposed between a connection portion between the metal terminal and the first diffusion layer and a connection portion between the first reference potential and the second diffusion layer. The semiconductor device according to any one of claims 1 to 4. 6. The semiconductor device according to claim 1, wherein the one conductivity type region is a well formed in the semiconductor substrate.