JPH07183864A - Time slot assignment controlling method and device therefor - Google Patents

Abstract

PURPOSE:To provide a time slot assignment controlling method which is capable of flexibly coping with the change of the assignment of time slots by a simple constitution and processing the change of the setting of the assignment in short time. CONSTITUTION:As for a register (SSR) storing the head of an assignment time slot and a register (LER) setting the number of time slot to be used, two pairs of SSR 1 and LER 1, and SSR 2 and LER 2 exist in this method. The number of slot set to the LER 1 from the head time slot set to the SSR 1 and the number of slot set to the LER 2 from other head time slot set to the SSR 2 are extracted by each of pairs of comparison circuits 2760 and 2780, and 2761 and 2781. By a time slot access control circuit 2790, the assignment of continuous time slots at maximum two sections is performed for one interface circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time slot allocation control method and device applied to an exchange, a multiplexer or an ATM communication device.

[0002]

2. Description of the Related Art When constructing a communication device such as an exchange, a multiplexer or an ATM communication device, a simple structure is used as a method for connecting a function of accommodating a terminal device and a function of performing a switching operation or a multiplexing operation. In addition, a configuration method in which these are connected by a time division bus is known because of the advantage that simple control is sufficient.

FIG. 3 shows an AT having the bus type connection structure.
It is a principal part block diagram of an M exchange. In the figure, reference numeral 20
TEI1 to TEIn denoted by -1 to 20-n are interface circuits that accommodate a function of connecting to a terminal device, a public network, or a dedicated line. SW indicated by reference numeral 10
Is a switching circuit having an exchange function for exchanging data between arbitrary TEIk and TEIm.

Detailed configurations of the SW 10 and each TEI are shown in FIGS. First, FIG. 4 shows the detailed configuration of the SW 10, and the data receiving unit 110 and the header rewriting unit 1 are shown.
20, a data transmission unit 130, and a conversion table.

Further, FIGS. 5 and 6 respectively show the above TEs.
2 shows a detailed configuration in the vicinity of the I data reception control unit and the data transmission control unit. As shown in FIG. 5, the data reception control unit includes a reception control unit 210, a destination extraction unit 220, a buffer control unit 230, and a data buffer 240. The data transmission control unit, as shown in FIG. It is composed of a buffer control unit 260 and a time slot allocation control unit 270. Note that, in this example, the data reception control unit and the data buffer of the data transmission control unit and the buffer control unit are provided independently, but they may be shared.

The above TEI1 to TEIn and SW10 are S
They are mutually connected by a bus used for data transmission from W10 to each TEI and a bus used for data transfer from each TEI in the SW10 direction (see FIG. 3).

With respect to this bus, the former is called a down bus, and the latter is called an up bus. Of these, the downstream bus has a downstream bit synchronization clock (BCKDW), downstream cell start instruction clock (CCKDW1), and downstream data (DATADW) transfer function, while the upstream bus has an upstream frame start instruction timing supply clock (FCK). , Upstream cell start instruction timing supply clock (CCKDW2), Upstream bit clock (BCKUP), Upstream cell start instruction clock (CCKUP), Upstream data (DATAUP)
Has a transfer function.

FIG. 7 shows an example of the timing of each of these data on the down or up bus. For both down and up buses (CCKDW1 / CCKDW2 / CCKUP)
Data can be transferred to any destination (TEI) every cycle.

For upstream buses, CCKDW2 or CCKUP
The DATA UP section of one cycle is called a time slot,
The section of a certain level (low level in this example) of FCK is counted as the first slot or SLOTO, and k + 1 up to SLOTk.
It has a structure with individual time slots.

Next, the mechanism of data exchange in the bus type exchange as shown in FIG. 3 will be described. Here, the case of transferring data from TEI1 to TEI3 is taken as an example.

In TEI1 (see FIG. 6), data (INFO.) Input from a terminal or the like is stored in the data buffer 250 in the format shown in FIG. As shown in FIG. 8, information such as a connection identifier (PVCI) connecting TEI1 and TEI3 is added to the header of the data. The data stored in the data buffer 250 is then sent to the upstream bus, and its control is performed as follows.

The upstream bus is a time division bus composed of a plurality of time slots as described above. The time slot used by the TEI 1 is controlled by a processor (not shown) in charge of control of the exchange, and the start time slot number and the number of time slots occupied from the start time slot are determined by the time slot allocation control unit (of the data transmission control unit). SLOT
ACC.CONTL.) 270 is set.

The number of timeslots allocated is determined by the communication speed of the terminal accommodated in the TEI 1 and the communication speed per time slot is V [bp.
s], if the communication speed of the terminal or the like is nV [bps], n tie slots are allocated.

Now, the time slot allocation control unit (SLOT A
CC.CONTL.) 270 starts counting the number of CCKDW2 when FCK goes to L level, and when the set time slot comes around, the buffer control unit (BUFF.CONTL.
) Output the data transmission enable signal (TXEN) to 260 until the number of designated time slots is reached. This control allows TEI1 to send data to the upstream bus using the designated time slot.

The data sent to this bus is SW10.
To reach. In SW10 (see FIG. 4), the header rewriting unit 120 refers to the conversion table 140 using the PVCI in the header of the arrival data, and indicates the TAG-Y indicating the mounting position of the TEI3.
Pull out.

As described above, in this example, the destination is T
Since it is EI3, the value of TAG-Y becomes "3", and this value is written in the header of the transmission data, and the TE of the transmission source
It is output from I1 to the upstream bus.

On the other hand, the downlink bus is a bus for the SW 10 to broadcast data to all TEIs, and therefore, there is no need for time slot allocation like the upstream bus. For this broadcast to the down bus by SW10,
The TEI3 (see FIG. 5) monitors the TAG-Y field of all the broadcasted data with the TAG-Y filter (destination extraction unit) 220, and finds data marked with "3" in TAG-Y. Then, the buffer control unit 230 is driven by the reception instruction signal, and the internal data buffer 240
Store the data in.

Through the above series of operations, TEI1 to TE
Data exchange to I3 takes place. The above is a description of the outline of data transmission between TEIs. Next, the time slot allocation control in this data transmission will be described in detail.

Although the above description refers only to allocating time slots on the bus to one TEI, a method for allocating time slots to a plurality of TEIs will be described below. For ease of explanation, consider a case where the total number of time slots is 12 and the maximum number of TEIs that can be accommodated is 4.

FIG. 9 shows 1 to TEI1 to TEI4.
It is an example of allocation of ten time slots. In the figure, TS1 to 12 indicate time slot numbers, and the lower numbers 1, 2, 3, and 4 are TEs, respectively.
It shows that the time slot is assigned to I1, the time slot assigned to TEI2, the time slot assigned to TEI3, and the time slot assigned to TEI4.

That is, in FIG. 3A, three are provided in TEI1,
It can be seen that this is an example in which three time slots are allocated to TEI2, one to TEI1 and three to TEI4. In addition, "E" is attached to the time slots of 11 and 12,
It is shown that these two time slots are unallocated, that is, empty.

In the exchange, a processor (not shown) allocates a time slot to one TEI as described above, but as shown in FIG. 4A, a time slot is allocated doubly between TEIs. It is managed by the processor so that it will not happen.

FIG. 10 is a conventional block diagram of a time slot allocation control unit for performing the above time slot allocation control in TEI. In this conventional time slot allocation control unit 270, a register (SSR) 2710 for storing the head of the allocated time slot and a register (LER) 2730 for setting the number of time slots to be used are CPUs from a processor (not shown). It is connected to BUS.

The time slot counter (SC) 27
50 is CCKDW 2 from when FCKDW goes to L level
Is a circuit that counts the number of the output signals, and its output is input to two comparison circuits (COMP1, COMP2) 2760 and 2780. The value set in SSR 2710 and the output of the counter (SC) 2750 are given to COMP1, and the remaining value set in SSR 2710 and the value set in LER 2730 are added to adder (ADD) 2740 to COMP2. The value added by is given.

The outputs of both comparison circuits (COMP1, COMP2) are input to the time slot access control unit (SAC) 2790, and the value indicated by the counter (SC) 2750 is SSR 27.
When the time slot set to 10 is reached, CO
The output of MP1 turns on, and the SAC 2790 sends the transmission enable signal (TXE
When (N) is turned on and the set number of LER 2730 is reached,
The output of COMP2 turns on, resulting in TXEN turning off.

While performing the above-mentioned operation in each TEI,
Each of these TEIs sends data only to designated time slots as shown in FIG. 9 (a).

Next, consider a case where the number of time slots assigned to the TEI is changed from the upper stage to the lower stage of FIG. 9A, for example. The example of the figure shows that the allocation number of TEI1 is changed from 3 to 2 and the allocation number of TEI3 is changed from 1 to 2.

As described above, the time slot allocation is SSR
2710 and LER 2730 are set to arbitrary values. At that time, SSR 2710 is the nth, LER 273
The assigned time slots must be consecutive from the nth to the kth such that 0 is k.

When reassigning time slots according to this rule, the register (SS
Rewriting the contents of (R, LER) is not allowed because the communication performed by TEI that does not need to be changed is interrupted. Therefore, the TE already assigned
For I (in this example, TEI2 and TEI4), it is necessary to reallocate the time slot without changing the setting value.

The result of changing the allocation according to such a rule is shown in the lower part of FIG. 10A, and the TEI 1 has changed from the time slots 1 to 3 to the time slots 1 to 2.
In the TEI 3, the allocation from the time slot 7 to 1 has been changed from the time slot 11 to 2.

Next, as another case different from the above, FIG.
From the time slot allocation state shown in the upper part of (a), TE
Consider a case where it is necessary to change the allocation number of I3 from 1 to 3, instead of 1.

In this case, regarding the number of time slots that can be re-allocated to TEI3, since there are only two unused places continuously (upper part of FIG. 9 (a)), the larger one is inevitably assigned. However, since the maximum value is 2, it can be seen that the demand of such a case cannot be realized by the changing method as described above (the number of slots is continuously assigned from a certain slot).

In this case, TEI2 that does not need to be reallocated
If all the allocations including the TEI 4 are reexamined, the allocations are possible, but if the interruption of communication is not allowed as described above, such a request cannot be met.

Therefore, even in such a case, there is a method of designating the time slots to be used one by one in order to change the time slot allocation only for the portion that needs to be changed.

FIG. 11 shows an example of implementation of a time slot allocation control unit based on this method. As many registers as the number of time slots are prepared to designate the time slots to be used (SR
1, SR2, ..., SRn) and compare circuit (COMP1, COMP2,
~, COMPn) are also provided for the number of timeslots.

With such a configuration, for example, in the above example, the maximum number of changeable TEI3 allocations from the state in the upper part of FIG. 9A is 2.
It is also possible to set the maximum changeable number to 4 as in the relationship from the upper stage to the lower stage in FIG. 9B. Such allocation is possible because the time slot allocation rule does not have to be continuous as in the above-described example, and discontinuities such as 3, 7, 11 to 12 can be made.

However, according to the time slot allocation control based on this method, as can be seen from FIG. 11, it is necessary to prepare the registers for the time slot setting for the time slot, which increases the hardware scale. Not only that, but it took a lot of time to set from the processor.

[0038]

As described above, in the above-mentioned conventional time slot allocation control system, in order to flexibly change the allocation, it is necessary to prepare registers for time slot setting for the time slots. However, the hardware scale is increased, and the processor needs to set all the registers. Therefore, there is a problem that the setting time is long and inefficient.

The present invention eliminates the above problems, and allocates time slots while suppressing an increase in hardware scale due to an increase in the number of registers for designating allocation time slots and an increase in processor register setting time. An object of the present invention is to provide a time slot allocation control method and device capable of flexibly coping with changes.

[0040]

The first invention of the present application is such that a plurality of interface means capable of accommodating a terminal device are exchanged with each other through a time division bus having a plurality of time slots. In the communication device connected to the switching means for performing the multiplexing operation, the interface means is set to set at least two time slot sections that can be continuously used from a certain time slot position according to an instruction from the processor controlling exchange control. Means for allocating at least two consecutive time slots among all time slots when transmitting data to another interface means.

The second invention of this application is such that a plurality of interface means capable of accommodating a terminal device, a time division bus connecting the interface means and having a plurality of time slots, and connected to the time division bus. A time slot access control of the source interface means based on an instruction from a processor that controls exchange when transmitting data between the interface means, the switching means performing a switching operation or a multiplexing operation of the time slots. In a communication device in which the means continuously allocates and allocates a required number of time slots from a certain time slot position, the time slot access control means is a head for setting the position of the time slot at which data transmission is started. The slot setting means and data can be sent following the time slot. The number of slots used setting means for setting the number of time slots comprises at least two sets,
It is characterized in that at the time of data transmission to another interface means, at least two consecutive time slots among all time slots are assigned.

The third invention of this application is provided in the interface means of a communication device, which is formed by connecting a plurality of interface means capable of accommodating a terminal device to a switching means via a time division bus having a plurality of time slots. In a time slot allocation control device for allocating necessary time slots for data transmission, at least two first register means for setting different time slot positions for starting data transmission, and the first Second register means provided corresponding to the register means, each of which sets the number of time slots capable of transmitting data subsequent to the time slot set in the corresponding first register means, and the number of time slots is counted. A counter, and a count value of the counter, the first register means and the second register Comparing means for comparing with each set value of the stage, and when the count value reaches the set value of the first register means, a transmission permission signal is output, and further the set value of the corresponding second register means is reached. And a time slot access control means for controlling to stop the output of the transmission permission signal and allocate at least two consecutive time slots in all the time slots.

[0043]

In the present invention, the leading slot setting means for setting the leading time slot to be allocated on the time division bus, and the number of used slots for setting the number of consecutive time slots to be used. At least two sets of means are provided so that at least two consecutive time slots can be designated from all the time slots.

As a result, the flexibility of changing the allocation of the time slots is increased as compared with the case where only one set of this kind of setting means is provided, and it is significantly larger than the case where the setting means is provided by the number of time slots. The hardware scale can be reduced, and at the same time, the time required for the processor to make settings can be shortened.

[0045]

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing an embodiment of a time slot allocation control unit of a bus type ATM switch according to the present invention. The schematic structure of the ATM switch, the timing of the bus, the format of the data, and the outline of the switching operation are the same as those described in the conventional example, and therefore the description thereof is omitted here. The time slot allocation control unit 270A shown in FIG.
It may be considered as an improved example of the circuit of reference numeral 270 shown in FIG.

In the ATM switch of the present invention, the rule of time slot allocation is different from that of the conventional system and one TE is used.
It is possible to reallocate at least two consecutive time slots for I.

In order to realize this method, the time slot allocation control circuit 270A of the present invention sets a register for setting a head time slot to be allocated and how many time slots are continuously used from that register. It is realized by preparing two sets of registers for.

That is, in FIG. 1, first, a register (SSR1) 271 for storing the head of the assigned time slot
0 and one set of registers (LER1) 2730 for setting the number of timeslots that can be used from that time slot exist.
Another pair is provided by the R2) 2711 and the register (LER2) 2731. These registers (SSR1, LE
R1) and (SSR2, LER2) are connected to a CPU BUS from a processor (not shown).

The time slot counter (SC) 2
750 is a circuit that counts the number of CCKDW2 from the point where FCKDW goes to L level as in the conventional case, and its output is two sets of comparison circuits (COMPA1, COMPB1),
Input to (COMPA2, COMPB2).

Here, the (COMPA1) 2760 has the (SSR1)
The value set in 2710 and the output of the counter (SC) 2750 are given to (COMPB1) 2780, and (SSR1) 2
The value set in 710 is added to the value set in (LER1) 2730 by the adder (ADD1) 2740.

A similar functional circuit is used for (SSR2) 2711 and (LER2) 2731, and another set (COMPA2) and (COPA2)
MPB2) exists, and (COMPA2) 2761 has the value set in (SSR2) 2711 and the counter (SC) 2
The output of 750 is given to (COMPB2) 2781,
(LER2) 2731 to the value set in (SSR2) 2711
The value added by the adder (ADD2) 2741 is given.

The outputs of COMPA1, COMPB1, COMPA2, COMPB2 are input to the time slot access control section (SAC) 2790, and the value indicated by the counter (SC) 2750 is (SSR
1) When the time slot set in 2710 is reached, the output of (COMPA1) 2760 is turned on, the transmission enable signal (TXEN) is turned on, and when the number of settings of (LER1) 2730 is reached, (COMPB1) 2780 is reached. Output turns on, TX
EN is turned off.

Then, when the value indicated by the counter (SC) 2750 reaches the time slot set in (SSR2) 2711, the output of (COMPA2) turns on,
When the transmission permission signal (TXEN) is turned on and the set number of (LER2) 2731 is reached, the output of (COMPB2) 2781 is turned on and TXEN is turned off.

In this way, the time slot access control unit (SAC) 2790 sends registers (SSR1, LER).
1) and (SSR2, LER2) can be reassigned to two consecutive time slots determined by the set values.

Next, a specific example of time slot allocation by the time slot access control unit 270A having the above configuration will be described in detail with reference to FIG. For ease of explanation, FIG.
, The total number of time slots is 12, and the maximum number of TEIs that can be accommodated is 4.

The upper part of FIG. 2A shows TEI1 to TEI4.
It is an example of allocating 1 to 10 time slots to the. The 11th and 12th time slots indicate unused or empty.

In FIG. 2A, TS1 to 12 indicate time slot numbers, and the numbers 1, 2, 3, and 4 in the frame of the numbers are the time slots TEI2 assigned to TEI1, respectively. Assigned to TEI3,
This indicates that the time slot is assigned to TEI4.

From this, the upper part of FIG.
In this example, three time slots are allocated to TEI2, three to TEI2, one to TEI1 and three to TEI4, and two time slots, E, are unallocated.

When a processor (not shown) allocates time slots to one TEI as described above, management is performed so that time slots are not allocated twice between TEIs, as shown in the upper part of FIG. 2 (a). Is also done by this processor.

When the apparatus according to this embodiment is started up, each TE
In I, the first set of time slot setting registers in the time slot allocation control unit 270A, that is, SSR1,
Time slot allocation is performed only by LER1. This is because the processor initially manages one continuous time slot allocation for one TEI, and when the time slot allocation is completed, for example, as shown in FIG.
The allocation is as shown in the upper part of (a).

Next, the change control of time slot allocation to TEI according to the present invention will be described in detail. Figure 2 now
It is assumed that the number of timeslots allocated to TEI1 is changed from 3 to 2 and the number of timeslots allocated to TEI3 is changed from 1 to 3 as in the case of (b) from the upper stage to the lower stage.

As described in the section of the prior art, SS
When there is only one set of R and LER, and when the empty area of continuous time slots for only two time slots remains as shown in the upper part of FIG.
As for the change of 3, the maximum can be allotted to 2 as shown in the lower part.

According to the present invention, since two sets of SSR and LER are provided, up to two consecutive time slots can be reallocated to the TEI3. As a result, when the above request is received from the state shown in the upper part of FIG. 2A, as shown in the lower part of FIG. 2B, the TEI 3 has the time slot 7 alone and the time slot 7 as requested. A total of 3 timeslots 11 to 12 can be assigned.

As described in the section of the prior art, there has been a method of providing time slot setting registers corresponding to the number of time slots in order to make the time slot allocation most flexible (see FIG. 11).

According to this method, the empty time slot (time slot 3) of FIG. 2 (b) can be assigned to TEI3, which seems to be an excellent method at first glance. However, as described above, since the number of registers is required for the number of time slots, the hardware scale and the time required for the processor to set the registers are unavoidable.

On the other hand, in the method of the present invention, since the total number of registers is 4 regardless of the number of time slots, when the number of time slots exceeds 4, the hardware scale and the set time are extremely large. Take an advantage.

Although there is a demerit that only two consecutive time slots can be set, when the processor allocates a time slot in the initial stage, if the time slot number is allocated from the younger one, the latter half of the time slot can be set. Since empty time slots will be concentrated in the part, when changing the time slot allocation, the time slots to be reallocated can be allocated by assigning the time slot group that has been used until now and the empty area group in the latter half. Therefore, it can be said that there is practically no problem even if only two locations can be specified.

[0068]

As described above, according to the present invention, the head slot setting means for setting the head time slot and the use for setting the number of time slots to be continuously used from the head slot setting means. When at least two sets of slot number setting means are provided so that at least two consecutive time slots can be designated from all the time slots, the present control method is applied to a switch having a bus structure and a multiplexer. , Flexible control of time slot allocation is possible by adding minimum hardware, and it is possible to efficiently change only the part that needs to be changed in a short time while minimizing the setting time to the setting means. It has an excellent advantage.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a time slot allocation control unit in a bus type ATM switch according to the present invention.

FIG. 2 is a diagram showing an example of time slot allocation change based on the time slot allocation control method of the present invention.

FIG. 3 is a diagram showing a schematic configuration of a main part of a bus type ATM switch.

FIG. 4 is a detailed configuration diagram of a switching circuit in FIG.

5 is a detailed configuration diagram of a data reception control unit of the interface circuit in FIG.

6 is a detailed configuration diagram of a data transmission control unit of the interface circuit in FIG.

7 is a timing chart of each data on the bus between the switching circuit and the interface circuit in FIG.

8 is a diagram showing an example of a format of data transmitted between the interface circuits in FIG.

FIG. 9 is a diagram showing an example of time slot allocation change based on a conventional time slot allocation control method.

FIG. 10 is a configuration diagram of a time slot allocation control unit in a conventional bus type ATM switch.

FIG. 11 is a diagram showing another configuration example of the time slot allocation control unit in the conventional bus type ATM switch.

[Explanation of symbols]

10 switching circuit (SW) 110 data receiving unit 120 header rewriting unit 130 data sending unit 140 conversion table 20-1 to 20-n interface circuit (TEI1 to TE)
In) 210 reception control unit 220 destination extraction unit 240,250 data buffer 230,260 buffer control unit 270 time slot allocation control unit 2710,2711 allocation start time slot storage register (SSR1,2) 2730,2731 used time slot storage register ( LER1, 2) 2740, 2741 Adder (ADD1, ADD2) 2750 Time slot counter 2760, 2761 Comparison circuit (COMP.A1, COMP.A2) 2780, 2781 Comparison circuit (COMP.B1, COMP.B2) 2790 Time slot access Control unit (SAC)

Claims (15)

[Claims] 1. Communication in which a plurality of interface means capable of accommodating a terminal device are connected to a switching means for performing a replacing operation or a multiplexing operation of the time slots via a time division bus having a plurality of time slots. In the device, the interface means includes setting means for setting at least two time slot sections that can be continuously used from a certain time slot position according to an instruction from a processor in charge of exchange control, and transmits data to another interface means. At this time, the time slot allocation control method is characterized in that at least two consecutive time slots are allocated among all the time slots. 2. When changing the allocation of time slots, the time slot setting for the interface means that does not need to be changed is maintained as it is, and the setting section of the setting means is changed for other interface means that need to be changed in allocation. The time slot allocation control method according to claim 1, wherein time slot reallocation is performed according to the time slot allocation. 3. The time slot allocation control method according to claim 1, wherein the time slot allocation is performed using only one time slot section of the setting means when the apparatus is started up. 4. The time slot allocation control according to claim 3, wherein allocation is performed in order from the smallest time slot number, and empty time slots are concentrated in a section near the maximum value of the time slot number. Method. 5. The time slot allocation control method according to claim 1, wherein the interface means further has a function of connecting to a public network or a private line. 6. A plurality of interface means capable of accommodating a terminal device, a time division bus connecting the interface means and having a plurality of time slots, and a time division exchange operation connected to the time division bus. Alternatively, when transmitting data between the interface means, the time slot access control means of the interface means of the transmission source is provided with a switching means for performing a multiplexing operation, and based on an instruction from the processor that controls exchange, In a communication device for continuously allocating and allocating slots from a certain time slot position, the time slot access control means includes a leading slot setting means for setting a position of a time slot to start data transmission, and the time slot access control means. Set the number of time slots that can send data following a slot. At least two sets of used slot number setting means for performing the data transfer are provided, and at the time of data transmission to another interface means, at least two consecutive time slots among all time slots are assigned. Time slot allocation control method. 7. When changing the allocation of time slots, the setting of the time slot for the interface means that does not need to be changed is maintained as it is, and the setting values of the two sets of setting means for the other interface means that need to be changed. 7. The time slot allocation control method according to claim 6, wherein time slot reallocation is performed according to the change. 8. The time slot allocation control method according to claim 6 or 7, wherein when starting up the device, only one of the two sets of setting means is used for time slot allocation. 9. The time slot allocation control according to claim 8, wherein allocation is performed in order from the smallest time slot number, and empty time slots are concentrated in a section near the maximum value of the time slot number. Method. 10. The time slot allocation control method according to claim 6, wherein the interface means further has a function of connecting to a public network or a private line. 11. An interface means of a communication device, wherein a plurality of interface means capable of accommodating a terminal device are connected to a switching means via a time division bus having a plurality of time slots, and is provided in a necessary amount for data transmission. In a time slot allocation control device for allocating time slots, at least two first register means for setting different time slot positions for starting data transmission, and corresponding to the first register means are provided. Second register means for respectively setting the number of time slots capable of transmitting data following the time slot set in the corresponding first register means, a counter for counting the number of time slots, and a count of the counter A value is compared with each set value of the first register means and the second register means. And a transmission permission signal when the count value reaches the set value of the first register means, and a transmission permission signal is output when the corresponding count value reaches the set value of the second register means. And a time slot access control means for controlling to allocate at least two consecutive time slots in all time slots. 12. When changing the allocation of time slots, the setting values of the first and second register means for the interface means that do not need to be changed are maintained as they are and the interface means that need to be changed for the other interface means are maintained. First
12. The time slot allocation control device according to claim 11, wherein time slot reallocation is performed according to a change in the setting value of the second register means. 13. The time slot allocation according to claim 12 or 13, wherein only one set of the first register means and the second register means is used when the apparatus is started up. Control device. 14. The time slot allocation control according to claim 13, wherein allocation is performed in order from the smallest time slot number, and empty time slots are concentrated in a section near the maximum value of the time slot number. apparatus. 15. The time slot allocation control device according to claim 11, wherein the interface means further has a function of connecting to a public network or a private line.