JPH07161971A - Field effect transistor and its manufacture - Google Patents

Abstract

PURPOSE:To eliminate a low carrier concentration layer between an ohmic electrode and two-dimensional electron gas while preventing the introduction of other causes that deteriorate element characteristics. CONSTITUTION:At least a channel layer 3, an electrode supplying layer 4 and a cap layer 5 are laminated on a semiconductor substrate 1, a recessed gate electrode 8 is provided in the opening 6 on the cap layer 5 and a source drain electrode 8 is provided on the cap layer 5 so as to provide a field effect transistor. At least on the exposed part on the side wall of the cap layer 5 in the vicinity of the gate electrode 8, an intrinsic compound semiconductor layer 7 is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is directed to reducing the gate breakdown voltage,
The present invention relates to a field effect transistor in which parasitic resistance is reduced without deteriorating device characteristics due to an increase in source-gate capacitance, and a manufacturing method thereof.

[0002]

2. Description of the Related Art FIGS. 7 to 8 are explanatory views of a conventional example. In the figure, 15 to 18 are semiconductor substrates, 25 to 28 are buffer layers,
35-38 channel layer, 45 is an electron supply layer, 46a is n ⁺ electron supply layer, 46b the n ^- electron supply layer, 47a the n ^- - InAlAs electron supply layer, 47b is i-InAlAs layer, is 55 to 58 Cap layer,
55a to 56a and 58a are n ^-- GaAs cap layers, 55b to 56b
, 58b are n ⁺ -GaAs cap layers, 55c to 56c, 57b, 58.
c is an n ⁺ -InGaAs cap layer, 85 to 88 are gate electrodes, 95
a to 98a are source electrodes and 95b to 98b are drain electrodes.

For high integration and high performance of HEMTs and MESFETs, it is desired to use a non-alloy ohmic electrode having high reliability, high heat resistance, low resistance and miniaturization. In order to take full advantage of the non-alloy ohmic electrode, it is necessary to make the resistance between the electrode and the two-dimensional electron gas as low as possible. However, the conventional structure cannot sufficiently reduce the resistance.

The reason will be described with reference to FIG. In a field effect transistor having a recess gate structure, the lower layer portion of the cap layer 55 and the gate electrode 85 may come into contact with each other. Therefore, unless the carrier concentration in this portion is lowered, the gate breakdown voltage is lowered and the gate-source capacitance is also increased. As a result, the element characteristics are deteriorated such that the response becomes slow. Although the contact can be prevented by increasing the distance between the source and the gate, the parasitic resistance increases by the increased distance.

Therefore, the carrier concentration of the lower layer portion of the cap layer 55 which may come into contact with the gate electrode 85 is set to 1 to 2 × 10 ^18.
It is controlled to about cm ^-3 , and the resistance of this part is not low enough. In the HEMT of the n ⁻ -InAlAs / InGaAs layer, since the Schottky barrier of the InAlAs layer is low, the i-InAlAs layer 47b is inserted on the electron supply layer as shown in FIG. 8C. Further, as shown in FIG. 7B, the electron supply layer formed on the semiconductor substrate 16 is a HEMT having an InGaP layer or an AlGaAs layer.
Among them, in the structure in which the carrier concentration of the electron supply layer 46 is increased for the purpose of high performance, the carrier concentration of the upper layer portion of the electron supply layer 46 is lowered in order to secure the gate breakdown voltage.
Since these layers are also present in the source and drain portions, they cause an increase in parasitic resistance.

Further, FIG. 8D shows an example of a conventional MESFET, which has the same problem as HEMT in terms of structure.

[0007]

As described above, in order to reduce the parasitic resistance, the resistance between the ohmic electrode forming the source / drain electrodes and the two-dimensional electron gas of the electron supply layer is as low as possible, that is, as high as possible. Carrier concentration (5 x 10
¹⁸ cm ^-3 or more), a low carrier concentration layer was present in order to prevent the introduction of other factors that deteriorate the device characteristics.

The present invention provides a field effect transistor that does not include a low carrier concentration layer between the ohmic electrode and the two-dimensional electron gas, and a method for manufacturing the same, while preventing the introduction of other factors that deteriorate the device characteristics. With the goal.

[0009]

FIG. 1 is a diagram for explaining the principle of the present invention, showing a schematic cross-sectional view of formation of an intrinsic compound semiconductor layer on the side wall of a cap layer. In the figure, 1 is a semiconductor substrate, 3
Is a channel layer, 4 is an electron supply layer, 5 is a cap layer, 6 is an opening, 7 is an intrinsic compound semiconductor layer, 8 is a gate electrode, and 9 is
Are source / drain electrodes.

In the present invention, as shown in the schematic sectional view of FIG. 1, in order to prevent the contact between the gate electrode 8 and the high-concentration cap layer 5, a semiconductor layer having a low carrier concentration, for example, only between the two layers, for example, is provided. The intrinsic compound semiconductor layer 7 is formed. Also,
When the electron supply layer 4 having a low Schottky breakdown voltage is used, the semiconductor layer having a low concentration, for example, the intrinsic compound semiconductor layer 7 is formed only directly under the gate electrode 8.

FIG. 2 is an explanatory view of two kinds of manufacturing methods of a semiconductor layer having a low carrier concentration, which is peculiar to the present invention, for example, an intrinsic compound semiconductor layer 7. 2A to 2C are explanatory views of a method of forming the intrinsic compound semiconductor layer 7 having a low carrier concentration only on the side wall of the cap layer 5.

First, as shown in FIG. 2A, the cap layer 5 is removed only in the recess region by dry etching using an insulating film mask such as an SiO ₂ film (not shown) to form an opening for forming the recess gate electrode. Form part 6.

Next, as shown in FIG. 2B, after removing the mask made of the SiO ₂ film with hydrofluoric acid, for example, an i-GaAs layer is grown as the intrinsic compound semiconductor layer 7 on the entire surface. Since this growth is isotropic, the intrinsic compound semiconductor layer 7 also grows on the sidewall of the opening 6.

Finally, as shown in FIG. 2C, the intrinsic compound semiconductor layer 7 having the same thickness as the grown intrinsic compound semiconductor layer 7 is dry-etched. Since this dry etching is anisotropic, only the intrinsic compound semiconductor layer 7 grown on the side wall is left in the opening 6.

FIGS. 2D to 2F are explanatory views of a method of forming a semiconductor layer having a low carrier concentration, for example, an intrinsic compound semiconductor layer 7 on the side wall of the cap layer 5 and immediately below the gate. First, as shown in FIG. 2D, the cap layer 5 is removed only in the recess region by dry etching using a mask made of an insulating film 10 such as a SiO ₂ film.

Next, as shown in FIG. 2E, an intrinsic compound semiconductor layer 7 having a low carrier concentration is selectively grown only on the exposed inside of the opening 6 using the mask of the insulating film 10. Finally, as shown in FIG. 2F, the insulating film 10 used as the mask is removed with hydrofluoric acid to form a coating layer of the intrinsic compound semiconductor layer 7 only on the sidewalls and bottom of the opening 6.

That is, as shown in FIG. 1, at least the channel layer 3, the electron supply layer 4 and the cap layer 5 are laminated on the semiconductor substrate 1, and the recess structure is formed in the opening 6 of the cap layer 5. In the field effect transistor in which the source / drain electrodes 9 are provided on the gate electrode 8 and the cap layer 5, the intrinsic compound semiconductor layer 7 is formed at least on the exposed portion of the side wall of the cap layer 5 close to the gate electrode 8. As a result, as shown in FIGS. 2A to 2C, in the semiconductor substrate 1 in which at least the channel layer 3, the electron supply layer 4, and the cap layer 5 are stacked, the recess structure gate electrode of the cap layer 5 is formed. The step of forming the opening 6 in the formation region, the step of forming the intrinsic compound semiconductor layer 7 on the semiconductor substrate 1 including the opening 6, and the anisotropic compound semiconductor layer 7 Etching is performed to leave the intrinsic compound semiconductor layer 7 only on the side wall of the cap layer 5, or as shown in FIGS. 2D to 2F, patterning is performed on the recess structure gate electrode formation region of the cap layer 5. The step of providing the opening 6 with the insulating film 10 as a mask, the step of selectively forming the intrinsic compound semiconductor layer 7 only in the opening 6, and the step of removing the insulating film 10 on the semiconductor substrate 1. Achieved by

[0018]

There is a technique for preventing the contact between the gate electrode and the cap layer by forming an insulating film on the side wall of the cap layer, but it differs from the present invention in the following points.

First of all, if an insulating film is used to cover the side wall, the damage applied during etching is large, but since the semiconductor etching technique can be used in the present invention, the damage can be suppressed to a small level. It is possible.

Second, when an insulating film is used, a large difference in thermal expansion coefficient between the insulating film and the semiconductor layer causes a local strain, but in the present invention, a semiconductor layer having a similar thermal expansion coefficient is used. It is possible to suppress the distortion to a small level.

Further, in the present invention, since the low carrier concentration layer is not sandwiched between the ohmic electrode and the two-dimensional electron gas, the gate breakdown voltage and the parasitic capacitance are not increased.

[0022]

3 to 6 are schematic structural sectional views of several embodiments of the field effect transistor of the present invention.

In the figure, 11 to 14 are GaAs substrates, and 21a to 22.
a and 24a are i-GaAs buffer layers, 21b to 22b and 24b are i-AlG
aAs buffer layer, 23a is i-InP buffer layer, 23b is InAlA
s buffer layer, 31a to 32a are i-GaAs or AlGaAs channel layers, 33 is an i-InGaAs channel layer, 34 is an n ^-- GaAs channel layer, 41 to 42 are n ^-- GaInP or n ^-- AlGaAs electron supply layers, 43 is an n ⁻ -InAlAs electron supply layer, 51a to 52a, 54a
Is n ⁺ -GaAs cap layer, 51b to 52b, 54b is n ⁺ -InG
aAs cap layer, 53 is n ⁺ -InGaAs cap layer, 71, 74
Is i-GaAs layer, 72 is i-InGaP or i-AlGaAs layer, and 73 is i-In
AlAs layers, 81 to 84 are gate electrodes, 91a to 94a are source electrodes, and 91b to 94b are drain electrodes.

First, a first embodiment of the present invention will be described with reference to FIG. On the semi-insulating GaAs substrate 11, MO
2,000 Å thick i-GaAs buffer layer 21 by VPE method
a, 3,000 Å thick i-AlGaAs buffer layer 21b, 2,000
0 Å thick i-GaAs channel layer 31a, 100 Å thick i-
N of the thickness of the InGaAs channel layer 31b, 400 Å ^{- -} GaInP or n ^- - AlGaAs electron supply layer, the thickness of 500 Å n ⁺ GaAs
Cap layer 51a, n ⁺ InGaAs cap layer with a thickness of 500 Å
51b are sequentially laminated.

Next, a 1,000 Å-thick SiO ₂ film mask having an opening in the recess formation planned area formed by using the plasma CVD technique and the photolithography technique is used, and n ⁺ GaAs having a high carrier concentration in the opening is used. Cap layer 51a, n ⁺ In
Only the GaAs cap layer 51b was removed by dry etching with CCl ₂ F ₂ to form a recess structure.

After removing the SiO ₂ film used as the mask with hydrofluoric acid, the i-GaAs layer 71 was grown again on the entire surface of the GaAs substrate 11 to a thickness of 100 Å by MOVPE method. next,
By dry etching with CCl ₂ F ₂ , high carrier concentration in the recess structure n ⁺ GaAs cap layer 51a, n ⁺ InGaAs cap layer 51b Only the i-GaAs layer 7 on the side wall portion is left and i-Ga
The As layer 7 was etched.

Finally, a source electrode 91a and a drain electrode 91b made of Ti / Al having a thickness of 3,000Å and a gate electrode 81 made of an Al film having a thickness of 3,000Å were formed. Next, a second embodiment of the present invention will be described with reference to FIG.

On the semi-insulating GaAs substrate 12, the i-GaAs buffer layers 22a, 3,000 having a thickness of 2,000 Å are formed by MOVPE.
0 Å of the thickness of the i-AlGaAs buffer layer 22b, 2,000 Å of the thickness of the i-GaAs channel layer 32a, 100 Å of the thickness of the i-InGaAs channel layer 32b, the thickness of 2,000 Å n ^{- -} InGaP or n
^- - the thickness of the AlGaAs electron supply layer 42,500 Å thick of n ⁺ GaAs cap layer 52a, 500 Å n ⁺ InGaAs cap layer 52b
Are sequentially laminated.

Next, using a 1,000 Å-thick SiO ₂ film mask having an opening in the recess formation planned region formed by the plasma CVD technique and the photolithography technique, n ⁺ GaAs having a high carrier concentration in the opening is used. Cap layer 52a, n ⁺ In
Only the GaAs cap layer 52b was removed by dry etching with CH ₃ Br to form a recess structure.

Using this mask, the i-InGaP or i-AlGaAs layer 72 was grown only in the opening by MOVPE method.
Then, the mask is removed with hydrofluoric acid. Then 3,000 Å
Source electrode 92a and drain electrode made of Ti / Au with different thickness
A gate electrode 82 made of TI / Pt having a thickness of 92b and a thickness of 3,000 Å was prepared.

Next, a third embodiment of the present invention will be described with reference to FIG. On the semi-insulating GaAs substrate 13, MO
I-InP buffer layer 23a with a thickness of 500 Å by VPE method
, 3,000 Å thick InAlAs buffer layer 23b, 2,500
I-InGaAs channel layer 33 with a thickness of Å, n with a thickness of 4,000 Å
^- sequentially stacked n ⁺ InGaAs cap layer 53 having a thickness of -InGaAs electron supply layer 43,500 Å.

Next, using a 1,000 Å thick SiO ₂ film mask having an opening in a recess formation planned region formed by plasma CVD technology and photolithography technology, n ⁺ InGaAs having a high carrier concentration in the opening is used. Only cap layer 53 is C
A recess structure was created by removing it by dry etching with H ₃ Br.

Using this mask, by the MOVPE method,
An i-InAlAs layer 73 was grown to a thickness of 1,000Å only in the opening. Then, the mask is removed with hydrofluoric acid. Finally, a source electrode 93a and a drain electrode 93b made of Ti / Al having a thickness of 3,000 Å and a gate electrode 83 having a thickness of 3,000 Å made of an Al film were formed.

Next, the present invention will be described with reference to FIG.
A fourth embodiment applied to T will be described. On the semi-insulating GaAs substrate 14, the i-GaAs buffer layer 24a having a thickness of 2,000 Å and the i-AlGa having a thickness of 3,000 Å are formed by the MOVPE method.
As buffer layer 24b, 1,000 Å thick n ⁻ -GaAs channel layer 34, 500 Å thick n ⁺ -GaAs cap layer 54a, 500
An n ⁺ -InGaAs cap layer 54b having a thickness of Å is sequentially laminated.

Then, using a SiO ₂ film mask having a thickness of 1,000 Å and having an opening in the recess formation planned region, which is formed by using the plasma CVD technique and the photolithography technique, n ⁺ -having a high carrier concentration in the opening is used. GaAs cap layer 54a, n ⁺ -
Only the InGaAs cap layer 54b was removed by dry etching with CCl ₂ F ₂ to form a recess structure.

After removing the SiO ₂ film used as the mask with hydrofluoric acid, the i-GaAs layer 74 was grown again on the entire surface of the GaAs substrate 11 to a thickness of 100 Å by MOVPE method. next,
By dry etching with CCl ₂ F ₂ , high carrier concentration in the recess structure n ⁺ -GaAs cap layer 54a, n ⁺ -InGa
The i-GaAs layer 74 was etched leaving only the As cap layer 54b and the i-GaAs layer 74 on the side wall.

Finally, a source electrode 94a and a drain electrode 94b made of Ti / Al having a thickness of 3,000Å and a gate electrode 84 made of an Al film and having a thickness of 3,000Å were prepared.

[0038]

As described above, according to the structure and the manufacturing method of the present invention, a semiconductor layer having a low resistance is formed on the side wall of the cap layer to make the contact between the gate electrode and the cap layer as compared with the conventional example. In order to prevent this, the parasitic resistance is reduced to 3/4, and the effect of reducing the parasitic resistance of the present invention is confirmed without deteriorating the device characteristics, and HEMT and MESFE are confirmed.
It greatly contributes to the improvement of the characteristics of the field effect transistor such as T.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of the principle of the present invention (No. 1)

FIG. 2 is an explanatory diagram of the principle of the present invention (No. 2)

FIG. 3 is a device configuration diagram of a first embodiment of the present invention.

FIG. 4 is a device configuration diagram of a second embodiment of the present invention.

FIG. 5 is a device configuration diagram of a third embodiment of the present invention.

FIG. 6 is a device configuration diagram of a fourth embodiment of the present invention.

FIG. 7 is an explanatory diagram of a conventional example (No. 1)

FIG. 8 is an explanatory diagram of a conventional example (No. 2)

[Explanation of symbols]

1 semiconductor substrate 3 channel layer 4 electron supply layer 5 cap layer 6 opening 7 intrinsic compound semiconductor layer 8 gate electrode 9 source / drain electrode 10 insulating film 11 to 14 GaAs substrate 21a to 22a, 24a i-GaAs buffer layer, 21b to 22b, 24b i-AlGaAs buffer layer 23a i-InP buffer layer 23b InAlAs buffer layer 31a to 32a i-GaAs or AlGaAs channel layer 33 i-InGaAs channel layer 34 n ^-- GaAs channel layer 41 to 42 n ^-- GaInP or n ^- -AlGaAs electron supply layer 43 n ^- type InAlAs electron supply layer 51a ~52a, 54a n ⁺ -GaAs cap layer 51b ~52b, 54b n ⁺ -InGaAs cap layer 53 n ⁺ -InGaAs cap layer 71 and 74 i-GaAs layer 72 i-InGaP or i-AlGaAs layer 73 i-InAlAs layer 81 to 84 Gate electrode 91a to 94a Source electrode 91b to 94b Drain electrode

Claims (3)

[Claims] 1. A semiconductor substrate (1) on which at least a channel layer (3), an electron supply layer (4) and a cap layer (5) are laminated,
Recess structure gate electrode (8) in the opening (6) of the cap layer (5), and source / drain electrodes on the cap layer (5)
In the field effect transistor provided with (9), at least the cap layer close to the gate electrode (8)
A field effect transistor characterized in that an intrinsic compound semiconductor layer (7) is formed on an exposed portion of a side wall of (5). 2. At least a channel layer (3) and an electron supply layer
(4) In the semiconductor substrate (1) in which the cap layer (5) is laminated, a step of forming an opening (6) in the recess structure gate electrode formation region of the cap layer (5), and the opening (6 ) Including the step of forming the intrinsic compound semiconductor layer (7) on the semiconductor substrate (1) and anisotropic dry etching of the intrinsic compound semiconductor layer (7) to form a sidewall of the cap layer (5). A method for manufacturing a field effect transistor, characterized in that the intrinsic compound semiconductor layer (7) is left only in the region. 3. A semiconductor substrate (1) in which at least a channel layer (3), an electron supply layer (4) and a cap layer (5) are laminated.
In the opening (6), the insulating film (10) patterned in the recess structure gate electrode formation region of the cap layer (5) is used as a mask.
And a step of selectively forming the intrinsic compound semiconductor layer (7) only in the opening (6), and a step of removing the insulating film (10) on the semiconductor substrate (1). A method for manufacturing a field effect transistor, comprising: