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JPH0714942A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0714942A
JPH0714942A JP14333093A JP14333093A JPH0714942A JP H0714942 A JPH0714942 A JP H0714942A JP 14333093 A JP14333093 A JP 14333093A JP 14333093 A JP14333093 A JP 14333093A JP H0714942 A JPH0714942 A JP H0714942A
Authority
JP
Japan
Prior art keywords
conductor
hole
package body
pin
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14333093A
Other languages
Japanese (ja)
Inventor
Masatoshi Akagawa
雅俊 赤川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP14333093A priority Critical patent/JPH0714942A/en
Publication of JPH0714942A publication Critical patent/JPH0714942A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To provide a semiconductor device in which a semispherical bump can be formed easily on the opening of a conductor through-hole which is to be connected with a conductor pattern prepared in a package body. CONSTITUTION:The semiconductor device is provided with a semiconductor chip which is mounted on a plastic package body 10 having a conductor pattern thereon. In a conductor through-hole 22 which is formed by connecting a conductor layer 24 that has an opening on one end face of the body 10 and is formed along the inside wall face thereof with the conductor pattern, the stem part 30 of a T-shaped metallic pin erected on a collar part 26 whose area is larger than the opening is inserted as being contact with the layer 24, and a semispherical bump 18 is formed on the flat face side of the part 26 covering the opening of the through-hole 22.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置に関し、更に
詳細には導体パターンが形成されたパッケージに半導体
チップが搭載された半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a semiconductor chip mounted on a package having a conductor pattern formed thereon.

【0002】[0002]

【従来の技術】従来から図3に示す半導体装置が使用さ
れている。図3に示す半導体装置は、導体パターン(図
示せず)が形成されたパッケージ本体100のキャビテ
ィ凹部102に搭載された半導体チップ104と導体パ
ターンとがワイヤ106によって接続されていると共
に、パッケージ本体100に形成された導体パターン
は、パッケージ本体100の底面に装着されたピン11
0とビア等によって接続されている。尚、半導体チップ
104等はキャップ108によってキャビティ凹部10
2内に封止されている。従来、かかるパッケージ本体1
00は、セラミックによって形成されていたが、半導体
装置の軽量化や製造コストの低減のため、本発明者は先
に特願平5ー16934号明細書において、プラスチッ
クパッケージを提案した。
2. Description of the Related Art Conventionally, the semiconductor device shown in FIG. 3 has been used. In the semiconductor device shown in FIG. 3, the semiconductor chip 104 mounted in the cavity recess 102 of the package body 100 in which a conductor pattern (not shown) is formed is connected to the conductor pattern by a wire 106, and the package body 100 is also connected. The conductor pattern formed on the pin 11 is attached to the pin 11 mounted on the bottom surface of the package body 100.
0 and vias and the like are connected. It should be noted that the semiconductor chip 104 and the like are covered by the cap 108 with the cavity recess 10
It is sealed within 2. Conventionally, such a package body 1
00 was made of ceramics, but the present inventor previously proposed a plastic package in Japanese Patent Application No. 5-16934 in order to reduce the weight of the semiconductor device and reduce the manufacturing cost.

【0003】このプラスチックパッケージにおいては、
セラミックパッケージの如く、グリーンシートに穿設し
たスルーホール内に金属粉が混合されたペーストを充填
して焼成したビアによって、導体パターンとピンとを接
続することができず、図4に示す様に、導体スルーホー
ル202によって導体パターンとピン110とを接続す
る。かかる導体スルーホール202は、プラスチックパ
ッケージ本体200にドリル等によって穿設したスルー
ホール204の内壁面に、めっきによって導体パターン
と接続される導体層206を形成したものである。尚、
導体スルーホール202の開口部周縁には、導体層20
6に連結された端子ランド207が導体層206と一連
に形成されている。この導体スルーホール202には、
その開口面積よりも大なる面積の鍔部210の両面の各
々に、長ピン部211及び短ピン部212が突出したピ
ン110が装着される。ピン110の装着は、通常、短
ピン部212が導体スルーホール202内に挿入される
ことによる嵌着、或いは前記嵌着と樹脂付けとの併用に
よってなされる。
In this plastic package,
As in a ceramic package, the conductor pattern and the pin cannot be connected by the via that is formed by filling the paste in which the metal powder is mixed into the through hole formed in the green sheet and firing it. As shown in FIG. The conductor pattern is connected to the pin 110 by the conductor through hole 202. The conductor through hole 202 is formed by forming a conductor layer 206, which is connected to a conductor pattern by plating, on the inner wall surface of the through hole 204 formed in the plastic package body 200 by a drill or the like. still,
The conductor layer 20 is formed around the opening of the conductor through hole 202.
A terminal land 207 connected to the conductor 6 is formed in series with the conductor layer 206. In this conductor through hole 202,
The pins 110 with the long pin portions 211 and the short pin portions 212 protruding are attached to each of both surfaces of the flange portion 210 having an area larger than the opening area. The pin 110 is usually attached by fitting by inserting the short pin portion 212 into the conductor through hole 202, or by using both the fitting and resin attachment.

【0004】この様に導体スルーホール202に装着さ
れたピン110は、導体スルーホール202内に挿入さ
れた短ピン部212と導体層206との接触、及び端子
ランド207と鍔部210との接触によって、プラスチ
ックパッケージ本体200に形成された導体パターンと
接続される。しかし、最近、パッケージ本体200に搭
載される半導体チップ104の操作速度が高速化される
に伴い、パッケージ本体200の底面から外方に向けて
突出するピン110の長ピン部211のインダクタンス
や抵抗等の影響が問題となってきた。このため、本発明
者は、前述した特許出願の明細書において、ピン110
に代えて半球状のバンプを採用することも併せて提案し
た。
In the pin 110 thus mounted in the conductor through hole 202, the short pin portion 212 inserted in the conductor through hole 202 contacts the conductor layer 206, and the terminal land 207 contacts the flange portion 210. Is connected to the conductor pattern formed on the plastic package body 200. However, recently, as the operation speed of the semiconductor chip 104 mounted on the package body 200 has been increased, the inductance and resistance of the long pin portion 211 of the pin 110 protruding outward from the bottom surface of the package body 200. Has become a problem. For this reason, the inventor has proposed that the pin 110
We also proposed to use hemispherical bumps instead of.

【0005】[0005]

【発明が解決しようとする課題】ピン110に代えてバ
ンプを採用することによって、ピン110の長ピン部2
11のインダクタンスや抵抗等の影響を解消することが
できる。しかしながら、ピン110に代えてバンプを採
用する際に、はんだ等の低融点金属を溶融し、導体スル
ーホール202の開口部上又はその近傍に溶融低融点金
属の表面張力を利用して半球状のバンプを形成する必要
がある。このため、図5に示す種々の問題が発生する。
By using a bump instead of the pin 110, the long pin portion 2 of the pin 110 can be obtained.
It is possible to eliminate the influence of the inductance, resistance, etc. of 11. However, when a bump is used instead of the pin 110, a low melting point metal such as solder is melted and a hemispherical shape is formed on the opening of the conductor through hole 202 or in the vicinity thereof by utilizing the surface tension of the molten low melting point metal. It is necessary to form bumps. Therefore, various problems shown in FIG. 5 occur.

【0006】つまり、図5(a)に示す如く、導体スル
ーホール202の開口部を避けて端子ランド207上に
バンプ300を形成せんとする場合、半球状のバンプ3
00を容易に形成することができるものの、端子ランド
207の面積を拡大しなければならず、バンプ300の
形成密度が従来のピン110の装着密度よりも低下す
る。一方、導体スルーホール202の開口部上に直接バ
ンプ300を形成せんとすると、図5(b)に示す如
く、導体スルーホール202内に低融点金属の一部が進
入し形状の崩れたバンプ300が形成される。或いは、
図5(c)に示す如く、導体スルーホール202の開口
部周縁に沿って低融点金属が流れ、ドーナツ状のバンプ
300が形成される。この様に、導体スルーホール20
2の開口部上に半球状のバンプを形成することは、極め
て困難であった。そこで、本発明の目的は、パッケージ
本体に形成された導体パターンに接続される導体スルー
ホールの開口部上に、半球状のバンプを容易に形成する
ことができる半導体装置を提供することにある。
That is, as shown in FIG. 5A, when the bump 300 is not formed on the terminal land 207 while avoiding the opening of the conductor through hole 202, the hemispherical bump 3 is formed.
00 can be easily formed, but the area of the terminal land 207 must be increased, and the formation density of the bumps 300 becomes lower than the mounting density of the conventional pins 110. On the other hand, if the bumps 300 are not formed directly on the openings of the conductor through-holes 202, as shown in FIG. 5B, the bumps 300 whose shape has collapsed due to a portion of the low melting point metal entering the conductor through-holes 202. Is formed. Alternatively,
As shown in FIG. 5C, the low melting point metal flows along the periphery of the opening of the conductor through hole 202 to form a donut-shaped bump 300. In this way, the conductor through hole 20
It was extremely difficult to form a hemispherical bump on the second opening. Therefore, an object of the present invention is to provide a semiconductor device capable of easily forming a hemispherical bump on an opening of a conductor through hole connected to a conductor pattern formed on a package body.

【0007】[0007]

【課題を解決するための手段】本発明者は、前記目的を
達成すべく検討を重ねた結果、鍔部にピン部が立設され
たT字ピンを用い、T字ピンのピン部を導体スルーホー
ル内に挿入し、導体スルーホールの開口部を覆うT字ピ
ンの鍔部の平坦面側にバンプを形成することによって、
導体スルーホールの開口部上に半球状のバンプを容易に
形成できることを見出し、本発明に到達した。すなわ
ち、本発明は、導体パターンが形成されたパッケージ本
体に半導体チップが搭載された半導体装置において、該
パッケージ本体の一端面に開口され且つ内壁面に沿って
形成された導体層が前記導体パターンに接続されて成る
導体スルーホール内に、導体スルーホールの開口面積よ
りも大なる面積の鍔部に立設された金属製のT字ピンの
ピン部が、前記導体層に接触するように挿入されている
と共に、前記導体スルーホールの開口部を覆うT字ピン
の鍔部の平坦面側に、はんだ等の低融点金属から成る半
球状のバンプが形成されていることを特徴とする半導体
装置にある。かかる構成を有する本発明は、パッケージ
本体がプラスチックからなる半導体装置に好適に適用で
きる。
As a result of repeated studies to achieve the above object, the present inventor has used a T-shaped pin in which a pin portion is erected on a collar portion, and uses the T-shaped pin's pin portion as a conductor. By inserting into the through hole and forming a bump on the flat surface side of the collar portion of the T-shaped pin that covers the opening of the conductor through hole,
The inventors have found that hemispherical bumps can be easily formed on the openings of conductor through holes, and have reached the present invention. That is, according to the present invention, in a semiconductor device in which a semiconductor chip is mounted on a package body having a conductor pattern formed thereon, a conductor layer formed along one inner wall surface of the package body and formed along an inner wall surface is formed on the conductor pattern. Into the conductor through-hole formed by connection, a pin portion of a metal T-shaped pin erected on a collar portion having an area larger than the opening area of the conductor through hole is inserted so as to come into contact with the conductor layer. In addition, a hemispherical bump made of a low melting point metal such as solder is formed on the flat surface side of the collar portion of the T-shaped pin that covers the opening of the conductor through hole. is there. The present invention having such a configuration can be suitably applied to a semiconductor device whose package body is made of plastic.

【0008】[0008]

【作用】本発明によれば、パッケージ本体の導体パター
ンに接続する導体スルーホールの開口部がT字ピンの鍔
部によって覆われるため、平坦面である鍔部のバンプ形
成面において、はんだ等の低融点金属を溶融して半球状
のバンプを形成する際に、導体スルーホール内に低融点
金属が進入すること、或いは導体スルーホールの開口縁
に沿ってドーナツ状に低融点金属が流れることを防止
し、半球状のバンプを容易に形成できる。また、導体ス
ルーホールの開口部上にバンプを形成できるため、バン
プの高密度化を図ることもできる。
According to the present invention, since the opening of the conductor through hole connected to the conductor pattern of the package body is covered with the flange of the T-shaped pin, solder or the like is not formed on the bump forming surface of the flange which is a flat surface. When the low melting point metal is melted to form a hemispherical bump, the low melting point metal may enter into the conductor through hole, or the low melting point metal may flow in a donut shape along the opening edge of the conductor through hole. It is possible to prevent and easily form a hemispherical bump. Further, since the bump can be formed on the opening of the conductor through hole, the density of the bump can be increased.

【0009】[0009]

【実施例】本発明を図面によって更に詳細に説明する。
図1は、本発明の一実施例を示す断面図であり、プラス
チックパッケージ本体10(以下、パッケージ本体10
と称することがある)のキャビティ凹部11に搭載され
た半導体チップ12は、パッケージ本体10に形成され
た導体パターン(図示せず)とワイヤ14によってボン
ディングされている。これら半導体チップ12等が装着
されたキャビティ凹部11は、キャップ16によってキ
ャビティ凹部11内に封止される。この図1に示すパッ
ケージ本体10の導体パターンと、パッケージ本体10
の底面に形成された半球状のはんだバンプ18、18・
・・とは、図2に示す導体スルーホール22によって接
続されている。
The present invention will be described in more detail with reference to the drawings.
FIG. 1 is a sectional view showing an embodiment of the present invention.
The semiconductor chip 12 mounted in the cavity concave portion 11 (which may be referred to as “”) is bonded by a wire 14 to a conductor pattern (not shown) formed on the package body 10. The cavity recess 11 in which these semiconductor chips 12 and the like are mounted is sealed in the cavity recess 11 by the cap 16. The conductor pattern of the package body 10 shown in FIG.
Hemispherical solder bumps 18, 18 formed on the bottom surface of the
.. are connected by the conductor through holes 22 shown in FIG.

【0010】図2に示す導体スルーホール22は、パッ
ケージ本体10に形成されている導体パターンと当接す
るスルーホール20をドリル等によって穿設した後、銅
めっき等によってスルーホール22の内壁面に沿って導
体層24を形成する。この導体層24は、導体パターン
とスルーホール22の開口部周縁に形成された端子ラン
ド26との間を接続する。かかる導体スルーホール22
には、金属製のT字ピンのピン部30が挿入されること
によって、その鍔部26が導体スルーホール22の開口
部を覆いつつ、T字ピンがパッケージ本体10の底面に
装着される。このT字ピンは、ピン部30と導体層24
との接触、及び鍔部28と端子ランド26との接触によ
って、パッケージ本体10に形成された導体パターンと
接続される。本実施例において使用するT字ピンは、
銅、ニッケル、鉄ーニッケルーコバルト合金、又は鉄ー
ニッケル合金等によって形成することができ、導体スル
ーホール22とピン部30との嵌合によりパッケージ本
体10に装着される。尚、導体スルーホール22とピン
部30との嵌合が不充分の場合には、樹脂付けを行って
もよい。
The conductor through-hole 22 shown in FIG. 2 is formed along the inner wall surface of the through-hole 22 by copper plating or the like after the through-hole 20 that comes into contact with the conductor pattern formed on the package body 10 is drilled. To form the conductor layer 24. The conductor layer 24 connects the conductor pattern and the terminal land 26 formed on the periphery of the opening of the through hole 22. Such conductor through hole 22
By inserting the pin portion 30 of the T-shaped pin made of metal, the collar portion 26 covers the opening of the conductor through hole 22 and the T-shaped pin is mounted on the bottom surface of the package body 10. This T-shaped pin has a pin portion 30 and a conductor layer 24.
The conductor pattern formed on the package body 10 is connected to the conductor pattern by the contact with the flange 28 and the terminal land 26. The T-shaped pin used in this embodiment is
It can be formed of copper, nickel, iron-nickel-cobalt alloy, iron-nickel alloy, or the like, and is mounted on the package body 10 by fitting the conductor through hole 22 and the pin portion 30. If the conductor through hole 22 and the pin portion 30 are not sufficiently fitted to each other, resin may be applied.

【0011】本実施例においては、パッケージ本体10
の底面に装着されたT字ピンの鍔部26の平坦面側に、
半球状のはんだバンプ18を形成する。このバンプ18
の成形は、先ず、鍔部26の平坦面であるバンプ形成面
にフラックスを塗布した後、はんだボールをバンプ形成
面に載置しつつ加熱溶融し、溶融はんだの表面張力を利
用して半球状とする。次いで、半球状の溶融はんだを冷
却することによって半球状のバンプ18が形成される。
他の成形方法としては、鍔部26のバンプ形成面に、は
んだペーストをスクリーン印刷によって所定厚さに塗布
してはんだペースト層を形成した後、はんだペースト層
を加熱溶融することによっても半球状のバンプ18を形
成できる。
In this embodiment, the package body 10
On the flat side of the collar 26 of the T-pin attached to the bottom of the
A hemispherical solder bump 18 is formed. This bump 18
First, the flux is applied to the bump forming surface, which is a flat surface of the collar portion 26, and then the solder balls are placed on the bump forming surface to be melted by heating, and the surface tension of the molten solder is used to make a hemispherical shape. And Next, the hemispherical bumps 18 are formed by cooling the hemispherical molten solder.
As another forming method, a solder paste may be applied to the bump forming surface of the collar portion 26 by screen printing to a predetermined thickness to form a solder paste layer, and then the solder paste layer may be heated and melted to form a hemispherical shape. The bump 18 can be formed.

【0012】この様に、本実施例のはんだバンプ18
は、導体スルーホール22の開口部を覆うT字ピンの鍔
部26の平坦面側に形成されるため、バンプ18の成形
の際に、導体スルーホール22の開口部の影響を排除で
き、半球状のバンプ18を容易に形成できる。更に、バ
ンプ18を導体スルーホール22の開口部上に形成で
き、バンプ18をパッケージ本体10の底面に高密度に
設けることができる。このため、半導体チップ12の高
集積化等に伴う半導体装置の多ピン化にも対応可能であ
る。また、パッケージ本体10の導体パターンと外部接
続端子とが導体スルーホール22を介して接続されたパ
ッケージにおいて、外部接続端子として使用されていた
従来のピンに比較して、インダクタンスや抵抗等の影響
が少ないバンプ18を容易に形成でき、操作速度が高速
化された半導体チップを搭載可能とすることができる。
Thus, the solder bumps 18 of this embodiment are
Is formed on the flat surface side of the collar portion 26 of the T-shaped pin that covers the opening of the conductor through hole 22, so that the influence of the opening of the conductor through hole 22 can be eliminated when the bump 18 is formed, and the hemisphere Shaped bumps 18 can be easily formed. Further, the bumps 18 can be formed on the openings of the conductor through holes 22, and the bumps 18 can be provided on the bottom surface of the package body 10 with high density. Therefore, it is possible to cope with the increase in the number of pins of the semiconductor device accompanying the high integration of the semiconductor chip 12. Further, in a package in which the conductor pattern of the package body 10 and the external connection terminals are connected via the conductor through holes 22, the influence of inductance, resistance, etc. is greater than that of a conventional pin used as an external connection terminal. It is possible to easily form a small number of bumps 18 and mount a semiconductor chip having an increased operation speed.

【0013】以上、述べてきた本実施例において使用す
るT字ピンは、図4に示すピン110の短ピン部212
を導体スルーホール22内に挿入した後、パッケージ本
体10の底面から外方に向けて突出する長ピン部211
を切削してもよい。また、本実施例では、プラスチック
パッケージ10について述べてきたが、セラミックパッ
ケージにおいても、導体スルーホールを設ける場合に
は、本実施例で用いたT字ピンを利用して導体スルーホ
ールの開口部上に、半球状のバンプを容易に形成でき
る。
The T-shaped pin used in this embodiment described above is the short pin portion 212 of the pin 110 shown in FIG.
Of the long pin portion 211 protruding outward from the bottom surface of the package body 10 after inserting into the conductor through hole 22.
May be cut. Although the plastic package 10 has been described in the present embodiment, when the conductor through hole is provided in the ceramic package as well, the T-shaped pin used in the present embodiment is used to form the conductor through hole on the opening. Moreover, hemispherical bumps can be easily formed.

【0014】[0014]

【発明の効果】本発明によれば、インダクタンスや抵抗
等の影響が従来のピンに比較して少ない半球状のバンプ
をパッケージ本体の一端面に容易に形成でき、操作速度
が高速化された半導体チップを搭載した半導体装置を提
供できる。
According to the present invention, hemispherical bumps, which are less affected by inductance and resistance as compared with the conventional pins, can be easily formed on one end surface of the package body, and the operation speed is increased. A semiconductor device equipped with a chip can be provided.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る半導体装置の一実施例を示す断面
図である。
FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention.

【図2】図1に示す半導体装置のバンプ18の近傍の構
造を示す部分断面図である。
2 is a partial cross-sectional view showing a structure near a bump 18 of the semiconductor device shown in FIG.

【図3】従来の半導体装置を説明するための断面図であ
る。
FIG. 3 is a cross-sectional view for explaining a conventional semiconductor device.

【図4】図3に示す半導体装置のピン110の近傍の構
造を示す部分断面図である。
4 is a partial cross-sectional view showing a structure near a pin 110 of the semiconductor device shown in FIG.

【図5】導体スルーホール202にバンプ300を形成
する際に発生する問題を説明するための説明図である。
FIG. 5 is an explanatory diagram for explaining a problem that occurs when forming the bumps 300 in the conductor through holes 202.

【符号の説明】[Explanation of symbols]

10 パッケージ本体 12 半導体チップ 18 バンプ 22 導体スルーホール 24 導体層 28 鍔部 30 ピン部 10 Package Body 12 Semiconductor Chip 18 Bump 22 Conductor Through Hole 24 Conductor Layer 28 Collar Section 30 Pin Section

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 導体パターンが形成されたパッケージ本
体に半導体チップが搭載された半導体装置において、 該パッケージ本体の一端面に開口され且つ内壁面に沿っ
て形成された導体層が前記導体パターンに接続されて成
る導体スルーホール内に、導体スルーホールの開口面積
よりも大なる面積の鍔部に立設された金属製のT字ピン
のピン部が、前記導体層に接触するように挿入されてい
ると共に、 前記導体スルーホールの開口部を覆うT字ピンの鍔部の
平坦面側に、はんだ等の低融点金属から成る半球状のバ
ンプが形成されていることを特徴とする半導体装置。
1. In a semiconductor device in which a semiconductor chip is mounted on a package body having a conductor pattern formed thereon, a conductor layer formed along an inner wall surface of the package body and connected to the conductor pattern. Into the conductor through-hole formed as described above, the pin portion of the metal T-shaped pin erected on the flange portion having an area larger than the opening area of the conductor through hole is inserted so as to contact the conductor layer. In addition, a hemispherical bump made of a low melting point metal such as solder is formed on the flat surface side of the collar portion of the T-shaped pin that covers the opening of the conductor through hole.
【請求項2】 パッケージ本体がプラスチックからなる
請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the package body is made of plastic.
JP14333093A 1993-06-15 1993-06-15 Semiconductor device Pending JPH0714942A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14333093A JPH0714942A (en) 1993-06-15 1993-06-15 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14333093A JPH0714942A (en) 1993-06-15 1993-06-15 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0714942A true JPH0714942A (en) 1995-01-17

Family

ID=15336279

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14333093A Pending JPH0714942A (en) 1993-06-15 1993-06-15 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0714942A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08236911A (en) * 1995-02-27 1996-09-13 Nec Corp Structure of ball-shaped external connection terminal
WO1998034443A1 (en) * 1997-01-30 1998-08-06 Ibiden Co., Ltd. Printed wiring board and manufacturing method therefor
KR100239406B1 (en) * 1996-12-27 2000-01-15 김영환 Surface mounted semiconductor package and method of manufacturing the same
US6199273B1 (en) 1995-12-19 2001-03-13 Sumitomo Metal Industries, Ltd. Method of forming connector structure for a ball-grid array
US6518513B1 (en) 1997-06-06 2003-02-11 Ibiden Co. Ltd. Single-sided circuit board and method for manufacturing the same
JP2018006463A (en) * 2016-06-29 2018-01-11 京セラ株式会社 Substrate for mounting semiconductor device and semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08236911A (en) * 1995-02-27 1996-09-13 Nec Corp Structure of ball-shaped external connection terminal
US6199273B1 (en) 1995-12-19 2001-03-13 Sumitomo Metal Industries, Ltd. Method of forming connector structure for a ball-grid array
KR100239406B1 (en) * 1996-12-27 2000-01-15 김영환 Surface mounted semiconductor package and method of manufacturing the same
WO1998034443A1 (en) * 1997-01-30 1998-08-06 Ibiden Co., Ltd. Printed wiring board and manufacturing method therefor
US6444924B1 (en) * 1997-01-30 2002-09-03 Naoto Ishida Printed wiring board with joining pin and manufacturing method therefor
US6518513B1 (en) 1997-06-06 2003-02-11 Ibiden Co. Ltd. Single-sided circuit board and method for manufacturing the same
US7721427B2 (en) 1997-06-06 2010-05-25 Ibiden Co., Ltd. Method for manufacturing single sided substrate
JP2018006463A (en) * 2016-06-29 2018-01-11 京セラ株式会社 Substrate for mounting semiconductor device and semiconductor device

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