JPH07109599B2 - Information transfer device for processing system - Google Patents

Description

TECHNICAL FIELD The present invention relates to a processing system, and more particularly to an information transfer device used therein.

Background Art A bus system used in a processing system such as a computer has a common signal bus or bus that interconnects each component or module that configures the system, and a master module that activates data transfer on the bus. Data transfer is performed with the slave module that accepts the activation of this data transfer.

As is well known, the bus system includes a synchronous system and an asynchronous system. The synchronous type has a merit that it can use a low-speed circuit element as compared with the asynchronous type, and thus consumes less power. However, since the circuit operation proceeds in synchronization with the clock common to each module, the data transfer rate depends on the clock rate (frequency). Therefore, in order to transfer a large amount of data in a short time, a high speed clock must be used.

For example, in a processing system that handles image data, the higher the image resolution, the larger the total amount of information. Moreover, in order to handle a large number of images, the processing capacity of the entire system must be large. For example, in a large-scale system, there is a demand to simultaneously operate multiple modules on the bus at a transfer rate of several megabytes per second. In order to increase the processing capacity of the system, the high speed of data transfer in the system is also one factor.

In the conventional bus transfer method, there is a method in which the master module addresses the slave module and waits until data is actually transferred. For example, when receiving data from a slave module, address the slave module's address space. At that time, if the slave module is engaged in other operations,
The master module will wait until the operation is completed. Therefore, during the waiting period, the bus is occupied by the module, and another module cannot use it.

Further, generally, an interrupt request is generated asynchronously from each module of the processing system. The interrupt control requires an interrupt control line independent of the control line for normal data transfer control. For example, an interrupt request line and a response line are arranged in module units or module group units,
An independent signal line or an address line or a data line is used for setting the interrupt priority and transferring the interrupt vector.

Aim of the Invention In view of such a demand, it is an object of the present invention to provide an information transfer device having a simple configuration in which the time required for data transfer is short.

DISCLOSURE OF THE INVENTION According to the present invention, a common transfer path that commonly connects a plurality of constituent units that configure a processing system and transfers information, and a transfer path that is provided in each of the constituent units and that synchronizes with a clock of a predetermined frequency. An information transfer device in a processing system having a control means for controlling information transfer in
The common transfer path transfers a first signal line that defines the priority of each of the plurality of constituent units and a second signal line that transfers at least a second signal that includes designation information that designates one of the plurality of constituent units. A signal line and a third signal line that transfers a third signal indicating that the structural unit is responsive to information transfer,
A fourth signal line for transferring information, and the control means synchronizes with the clock, and when the constituent unit requests another constituent unit to use the common transfer path, the first signal To the first signal line to monitor the state of the first signal line from the constituent unit having a higher priority than the constituent unit of its own, and the first signal to any one of the first signal lines. Is not present, the second signal is output to the second signal line after the first signal output, while the second signal designating its own constituent unit is received from the second signal line. When its own structural unit can respond to this, the third signal is output to the third signal line, and after the second signal output, when the third signal is received, the following information is output. When the transfer is advanced and the third signal is not received, the common transfer path is opened.

According to one aspect of the present invention, the plurality of constituent units includes a central processing system, and the second signal includes a request signal for requesting an interrupt to the central processing system.

Description of Embodiments Next, an embodiment of the information transfer device according to the present invention will be described in detail with reference to the accompanying drawings.

In the processing system shown in FIG. 1, each structural unit (element), that is, module 12, 14 and
16 common signal transfer path (bus), that is, bus 10 is commonly connected. For example, the module 12 is a memory module having a system memory 18 and a bus interface (BIF) 20 in this embodiment. The module 14 is an I / O module having an input / output device (I / O) 22 and a BIF 20 in this embodiment. The I / O 22 includes not only normal input / output devices but also external storage devices and communication line interfaces.

The module 16 is a central processing system module having a central processing system and a BIF 21 in this embodiment. In the central processing system, central processing unit 24, local memory 26 and I / O 28 are internal buses.
Connected to BIF 21 by each other by 30. BIF 21 is
The BIF 20 of another module may have almost the same configuration, but is different from the other BIF 20 in that it has an interrupt processing circuit 800 described later.

These modules 12, 14 and 16 are understood in the context of the present invention as logical building blocks, i.e. logical modules, which may physically consist of a single unit or be physically separated. It may be composed of a plurality of units. Further, a plurality of each module may be prepared, or a single module may be provided. Therefore, a plurality of central processing system modules 16 may be connected,
Further, there may be a plurality of CPUs 24 in the central processing system module 16. Of course, the I / O 22 of the I / O module 14 may include a CPU.

Bus 10 and BIF 20 included in each module 12, 14 and 16
A bus system is configured by the above. In this embodiment, the connection lines between the modules are, as shown in FIG. 2, a bus clock BCLK, an address bus AB, a command response CR,
It consists of data bus DB, data response DR and arbitration bus ARB. It should be noted that each of these connecting lines does not necessarily consist of a single connecting line, but may include a plurality of connecting lines.

Of the modules 12, 14 and 16, the module that activates data transfer on the bus 10 is called the master module and is designated by the reference numeral 30 in FIG. A module that accepts activation of data transfer by the master module 30 is referred to as a slave module and is denoted by reference numeral 32.

In this embodiment, when the master module 30 addresses the slave module 32, the command response is sent to the slave modules as indicated by dotted lines 34 and 36 in the figure.
Return from 32 to master module 30. When data is transferred between the master module 30 and the slave module 32, the data response is returned from the slave module 32 to the master module 30.

The bus clock BCLK is supplied from any module included in this system. Alternatively, it may be supplied from a clock source independent of these modules.

The address bus AB is, in this embodiment, as shown in FIG.
It consists of a bus identification line ID, a command line CMD, an address line ADR, and a mask line MSK, and its data format is shown in FIG. 4A. As can be seen, the bus identification ID consists of 3 bits and indicates the type of information content. For example, "000" indicates an idle (IDLE), and "111" indicates an interrupt. The command CMD also displays the type of information content 3
It consists of bits, for example, "000" indicates read (READ), data is transferred from the slave module to the master module and "001" indicates write (WRITE), and data is transferred from the master module to the slave module.

The address ADR consists of 24 bits and can specify a logical address space of FFFFFF (H) including all modules in the system. In this embodiment, the data bus DB is 16 bits,
That is, it consists of 2 bytes, and the mask line of address bus AD
MSK is the data that is transferred based on its addressing 1
It has 2 bits to selectively mask the 6-bit upper and lower bytes. This simplifies the circuit configuration of the receiving register of the module.

The arbitration bus ARB, as shown in FIG.
In this embodiment, one hold line HOLD and 16 bus request lines BR0 to BR15 are included. The priority is higher in the order of BR0 to BR15 and HOLD. That is, if the HOLD line has the highest priority, for example, the module A has the third priority, and the module B has the second higher priority than the module A, as shown in FIG. Module B is
Assigned to BR14. The hold line HOLD is commonly connected to each module.

In addition, each module is connected so as to monitor the BR line of a module higher in rank than its own module.
That is, module A monitors the states of BR14, BR15 and HOLD. Module B also monitors the status of BR15 and HOLD.

For example, the arbitration control circuit 100 in the BIF 20 of the module A is constructed as shown in FIG. 6, for example. The control circuit 100 is provided in each of the modules 12, 14 and 16 and includes a NOR gate 102 and a NAND gate 1
04, and three flip-flops (FF) 106, 108, 110. To the input of the NOR gate, the HOLD line and the BR line of the module having a higher priority than itself, that is, BR14 and BR15 in this case, are input, and the output 112 thereof is the NAND gate 104.
Connected to the other input of the latter, and the other input of the latter has its own bus request
BR13 is input.

The system clock BCLK is supplied to the three flip-flops 106, 108 and 110, and these constitute a shift register that shifts in response to the clock BCLK. The output of each stage is used as a signal that defines each timing in the arbitration process. For example, the output 114 of the first stage 106 is the address ADR, command CMD from that module.
It specifies the timing of sending the message such as. This will be described in detail later.

Referring to FIG. 7, bus acquisition and arbitration processing between modules by this system are performed according to the flow shown in the figure. For example, as shown in FIGS. 15 (E) and 15 (F), at time t1, module A makes a request for data transfer using bus 10 to another module at time t2. Then (200),
In response to the bus clock BCLK coming next to each of these requests (202, FIG. 8), these modules make the signal BR significant (206).

In this example, module A first makes the signal BR13 significant. At that time, module A monitors the BR lines of all the modules having higher priority than its own module (224),
If a bus request BR is issued from another high-priority module at that time, it waits (242, FIG. 10). Thus, in this example, module B makes signal BR14 significant on the next clock following it, while module A takes the bus master (226). The module A that has performed the bus cycle acquisition processing 244 turns off the signal BR (248) and shifts to the data transfer processing. Therefore, the module B becomes the bus master in the next clock cycle.

For example, when a transfer request occurs at times t3 and t4, both modules simultaneously make the signal BR significant at the next clock.
In this example, module B has a higher priority than A, so
That is, the module B does not monitor the signal BR of the module A having a lower rank, so that the module B becomes the bus master in the next clock cycle. Therefore, the module A can be the bus master in the next clock cycle.

If the same module wants to continuously transfer data every 2 bytes (248), the signal line HOLD is made significant at the next cycle after the previous transfer cycle (hold request 25
0). As shown in FIG. 16, when the module A acts as a bus master and transfers data over two clock cycles, the signal line HO is transmitted from the module A at the next clock cycle.
Make LD significant. Thus, at that time, even if there is a bus request BR from another module B having a higher priority, it is waited until the signal HOLD is released.

The operation of this system will be described by taking the READ operation shown in FIG. 17 as an example. As can be seen from this, in this system, data transfer is normally performed using 6 cycles of the bus clock BCLK. The overall flow of the data bus DB is as shown in FIG. In the transfer condition designation step 300, first, as shown in FIG. 17 (B), when a data transfer request is generated in the master module 30 at time t10, the bus request BR is generated as described above in the subsequent clock cycle. Set (same (C)) and acquire bus master (same (D)).

In the subsequent clock cycle, the master module 30 uses the bus ID, as shown in FIG.
The command CMD and the address ADR are transmitted (Fig. 17 (D) (F) and (G)). In this example, since the READ command is sent, the command bit is "000".

From the slave module 32 which has received the address corresponding to its own logical address, the command response CR is returned to the master module 30 in the next clock cycle (FIG. 17 (H)). The command response CR is made up of 2 bits in this embodiment, “00” indicates no response, “01” indicates that execution is possible, “10” indicates that operation is not possible (execution is impossible), and “11” indicates an error.

For example, when the slave module 32 is occupied by another operation, "10" is returned. Master module
If the address ADR sent from 30 indicates a write-protected area, error "11" is returned. If it is outside the logical address space, the command response CR is not returned in this bus clock cycle (00). If these cannot be executed, the mass module 30
The data transfer is abandoned and the bus master acquisition is retried later.

The BIF 20 of each module is provided with a command response processing circuit 700 as illustrated in FIG. This circuit consists of three types of signal lines ID, CMD and A of the address bus AB.
It has a decoder (DEC) 702 which receives and decodes the DR, which outputs the signal SELECT when its module is addressed as slave module 32. Further, the decoding result 712 is transferred to the error detection circuit 704, and the latter carries out a logicality check of those parities and the like.

When the normality of the received address data ID, CMD and ADR is established, the signal ▲ ▼ is output. As illustrated, these signal lines are input to the encoding circuit (ENC) 710 via the AND gate 706 together with the signal line BUSY indicating that the module 32 is in use. Output 714 of AND gate 706
Indicates that the module 32 is in use even if the address data is normally received. Also encoder 710
To the input 716 of, the signal SELECT from the AND gate 708, ▲
The AND output of ▼ and ▲ ▼ is given. This output indicates that the module 32 is empty and ready for the data transfer.

These signals 714 and 716 are encoded by the encoding circuit 710 into the above-mentioned 2-bit command response CR and sent back to the master module 30. Each circuit element of the command response processing circuit 700 performs these operations in synchronization with the bus clock BCLK.

In this way, in the system that returns the command response, in addition to the return of the data response described below, the redundancy of the response process increases and the reliability improves. This is especially useful when the slave module encounters error handling or busy, and the bus can be handed over to another module without occupying the bus until it is resolved, which greatly contributes to improving bus usage efficiency. is doing.

Master module 30 when command response CR is received
Performs command response processing 320. Executable "0
If it is "1", the mask MSK is transmitted at the next clock cycle (Fig. 17 (I)). Further, in the subsequent bus clock cycle, the master module 30 performs data transfer (same (J)).

Since the example in the description is a READ operation (344 FIG. 13), data is transferred from the slave module 32 to the master module 30 (348). Of course, during the WRITE operation, data is transferred from the master module 30 to the slave module 32 (346, FIG. 18 (J)).

Read from slave module 32 at the next clock cycle
If it is an operation, a data response that indicates the reception result of the data
The DR is returned to the master module 30 (Fig. 17 (K)). In the case of the WRITE operation, the data response DR indicating the end of data transmission is returned to the master module 30 (FIG. 18 (K)). In the present embodiment, the data response DR consists of 2 bits, "00" indicates normal, "10" indicates a data transfer error, and "11" indicates an error, and "01" is not defined. For example, when the slave module 32 detects a transfer error in WRITE, "10" is returned, and when another error occurs in the slave module 32, "11" is returned. In response to this, the master module 30 performs the data response process 360.

As can be seen from the above description, the data transfer operation shown in FIGS. 17 and 18 is performed in a pipeline manner between the modules. When one module outputs one information unit such as a bus command in one cycle of the bus clock BCLK, another module can issue the bus command in the next clock cycle. Of course, the same applies to subsequent responses and data transmission. Looking at one module, when a command response CR is received for a bus request BR, the subsequent processing automatically proceeds in that module, so if another module issues a new bus request, it may be effectively accepted. There is.

In this way, the bus transfer operation is completed in 6 cycles of the bus clock BCLK. In the conventional synchronous bus transfer method, there is a system that does not return a command response but sends data following a bus command and waits for a data response to be returned. However, in the method of this embodiment, if error processing or busy of the slave module 32 is encountered after the bus command is sent, the occupation of the bus 10 is released by the command response reception of the master module 30. Bus 10 can be used. Therefore,
The use efficiency of the bus 10 is improved.

In such a system that performs pipeline transfer for 6 cycles, uses TTL devices for circuit elements, and uses DRAM with an average memory access time of about 100 to 300 nanoseconds, the bus clock BCLK is about 100 to 200 nanoseconds. Seconds (about 10MHz to 5MHz in frequency), preferably about 150 nanoseconds (about 6.7MH)
z) Clock cycles before and after can be advantageously used.

FIG. 14 shows the processing on the side of the slave module 32 for the above operation as a processing flow of the response bus. As can be seen from this, when the transfer condition is specified by the reception of the command CMD (400), the slave module 32 analyzes the command and returns the result to the master module 30 (420). In response to this, the master module 30 executes the command response process 320 and transfers the motor to the slave module 32 (46
0). In the slave module 32, in the case of READ, the normality of the received data is checked and the status is set to the master module.
Send to 30. In the case of WRITE, status information is sent to the master module 30 upon completion of data sending. In response to this, the master module 30 performs data response error processing (500).

By the way, in the present embodiment, the interrupt request generated in each module to the central processing system module 16 is
Process using AB. As mentioned above, address bus AB
Has the data format shown in Figure 4A, but an interrupt is identified by having all three bits on its ID line be a "1", as shown in Figures 4B and 4C. As shown in FIG. 4B, the interrupt request sets the command CMD to "001", that is, WRITE (writing to the CPU 24), and the interrupt response sets it to all "0", that is, READ (reading from the peripheral module). The address part ADR is set to the interrupt priority level of the module. Also, in a system with multiple central processing system modules 16 or multiple CPUs 24, the address section AD
May be included in R.

In this embodiment, the interrupt priority level can be set to 7 levels for the main level and 8 levels for the sub level, that is, 56 levels in total. In other words, the interrupt processing from the 56 modules that have acquired the bus master to the central processing system module 16 can be performed in each bus cycle without returning the interrupt vector.

The interrupt request is generated asynchronously with the clock in the peripheral module. As shown in FIG. 20, for example, when an interrupt request occurs in a module at time t14 (see FIG. 19).
0) In the interrupt request processing 602, the bus request line BR of the module is activated in response to the next incoming bus clock (FIG. 20 (C)). Therefore, as described above, the arbitration process adjusts the conflict with other modules, and when its own module takes the bus master, the module that takes this bus master uses the address bus in the format shown in Figure 4B.
Sends interrupt request data to AB (Fig. 20 (D) ~
(G)). Receiving this, the bus interface 21 of the central processing system module 16 returns the command response CR to the module which has taken the bus master in the next clock cycle (same (H)). Therefore, if execution is possible at this time, "01" is returned. (604). This completes the interrupt request processing.

The interrupt request data input to the bus interface 21 includes the interrupt priority level as described above, and the central processing system module 16 analyzes the priority level (606). The central processing module 16 analyzes the in-process interrupt request requested from each module, sends the interrupt request at the highest priority level to the CPU 24 at that time, and
When it confirms that 24 has accepted the interrupt, it returns an interrupt response to the module that requested this interrupt. This is also performed by activating the normal bus request line BR as shown in FIG.

In the interrupt response process 606, the central processing system module 16 activates the bus request line BR of the central processing system module 16 in synchronization with the bus clock BCLK (FIG. 21 (B)). Therefore, when the central processing system module 16 takes the bus master by adjusting the conflict with other modules as described above, the interrupt request data is sent to the address bus AB in the format shown in FIG. It is sent to the module in FIG. 21 (Fig. 21 (C) to (F)). Upon receipt of this, the module returns a command response CR in the next clock cycle (same (G)). Therefore, if execution is possible at this time, "01" is returned.

Therefore, the module that has requested the interrupt transfers the data necessary for the interrupt processing to the central processing system module 16 in synchronization with the bus clock (same (H)). In response to this, the central processing system module 16 returns the data response DR and executes the corresponding interrupt service processing 608. In service processing 608, in the same way as normal data transfer,
Processing based on the interrupt request is performed.

As can be seen from the above description, in the present embodiment, the processing peculiar to the interrupt request ends in 3 bus clock cycles until the command response CR is returned. After that, the interrupt priority level information and the like can be transferred using the normal bus transfer format.

In the present embodiment, the interrupt response described above is sent back to the module requesting the interrupt via the system bus 10 by the interrupt response circuit provided in the bus interface 21 of the central processing system module 16. This interrupt response circuit notifies the CPU 24 of the generation of an interrupt request as described above, and returns an interrupt response to the module that requested the interrupt.

However, it is not always necessary to provide the hardware for returning the interrupt response in this way. For example, the CPU 24 accepts the generation of an interrupt request, does not return the above-mentioned interrupt response at that time, and then the CPU 24 starts the service corresponding to the interrupt request and then the data corresponding to the service content It may be configured to return the interrupt requesting module to the module by a normal data transfer process. In the latter system configuration, the interrupt response in the above meaning will not be returned.

Effect The present invention thus secures a bus cycle in a synchronous manner by using the first signal for normal data transfer and interruption by the bus, and sets the corresponding status for the second signal command to the third signal. It is configured to be returned.
Therefore, even when the processing in the slave module is congested, the bus is released immediately without waiting until the congestion is resolved and occupying the bus as in the conventional case. Therefore, the time required for data transfer is short and the transfer capacity of the entire system increases. Especially effective when there is an error or busy.

Also, when the interrupt request is configured to use the same synchronous format as the normal bus request, the response status can be returned by the third signal, so an interrupt request line and its response vector return line are not required. Therefore, the device configuration is simplified.

In addition, compared to the asynchronous transfer method, standard devices such as TTL devices that have low speed and low power consumption are advantageously used, and the transfer efficiency of the entire system is maintained high.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an information transfer device of a processing system according to the present invention, FIGS. 2, 3 and 5 are explanatory diagrams showing the configuration of a bus system, and FIGS. 4A to 4C are FIG. 6 is an explanatory view showing the format of the address bus, FIG. 6 is a circuit function diagram showing an example of an arbitration circuit included in each module shown in FIG. 1, and FIGS. 7 to 14 are operation of the device shown in FIG. 15 to 18 are timing charts for explaining the operation of the apparatus shown in FIG. 1. FIG. 19 is a timing chart for explaining the interrupt operation of the apparatus shown in FIG. 20 and 21 are timing charts for explaining the interrupt operation of the device shown in FIG. 1, and FIG. 22 is a configuration of the command response return circuit in each module of the device shown in FIG. It is a circuit functional diagram which shows an example. Description of main part code 10 …… Bus 20,21 …… Bus interface 30 …… Master module 32 …… Slave module 100 …… Arbitration circuit 800 …… Interrupt processing circuit AB …… Address bus ADR …… Address line BR… … Bus request line CMD …… Command line CR …… Command response bus DB …… Data bus DR …… Data response bus ID …… Bus ID line

Claims (5)

[Claims] 1. A common transfer path for connecting a plurality of constituent units constituting a processing system in common and transferring information in parallel between the respective constituent units, and the common transfer path provided for each of the constituent units. An information transfer device in a processing system, the control means being connected to the control means for performing pipeline control of information transfer between constituent units via the common transfer path in synchronization with a clock of a predetermined frequency. The control means defines a priority order of its own constituent unit when using the common transfer path, and requests the use of the common transfer path from its own constituent unit to another constituent unit. First control means for outputting a signal in synchronization with the clock, the first control means being connected to all constituent units having a higher priority than the constituent unit of its own, based on a request in the constituent unit of its own. First control means having a monitoring means for monitoring the presence or absence of the first signal in the signal transmission means, and outputting the first signal from the first control means, Becomes a bus master, first designation information for designating at least one of the plurality of configuration units in a single address space, and operation contents for the configuration unit specified in the address space. Second control means for outputting a second signal including second designating information for designating the type of the item, and the designated configuration unit, when the designation is given by the first designating information. The third control means for outputting a third signal indicating that it is possible to respond to the information transfer of the operation content designated by the designation information, and its own constituent unit and the first designation information. Transfer information to / from other units And a fourth control means, wherein the common transfer path assigns the output of the first control means to each structural unit corresponding to the priority order of each structural unit, and independently assigns the structural unit for each priority order. A first signal transmission unit that is commonly connected and defines a priority of a structural unit in which the first control unit is housed, wherein the first signal output from the first control unit is configured in another configuration. A first signal transfer means for transferring to a unit, a second signal transfer means for transferring the second signal output from the second control means to another constituent unit, and an output from the third control means. The control unit includes a third signal transmitting unit that transfers the third signal to another structural unit, and a fourth signal transmitting unit that is connected to the fourth control unit of each structural unit and transfers the information. Means outputs the first signal when the first signal is output from the first control means. When the monitoring means detects that there is no first signal from any other constituent unit in any of the stages, the constituent unit becomes a bus master and the second control means of the constituent unit causes the second signal from the second controlling means. Second signal
On the other hand, if the control means of the structural unit that receives the second signal designating its own structural unit from the second signal transmission means is responsive to the second signal, The control means of the structural unit that outputs the third signal to the third signal transmission means, outputs the second signal, and then receives the third signal, based on the second designation information, Of the constituent unit that advances the information transfer of the above and outputs the second signal but does not receive the third signal,
An information transfer device for a processing system, characterized in that the common rolling path is opened. 2. The information transfer device according to claim 1, wherein the constituent unit includes a central processing system connected to the common transfer path via the control means, and the second designation information. Includes a request signal for requesting an interrupt with a predetermined interrupt priority to the central processing system of another structural unit, and the second control means includes the designation information when its own structural unit becomes a bus master. An information transfer apparatus, wherein the second signal is output to a second signal transfer means and transferred to the other structural unit. 3. The information transfer device according to claim 2, wherein the control means related to the central processing system has an interrupt processing means for processing the request signal according to the interrupt priority order, The information transfer device, wherein the interrupt processing means returns a third signal to a constituent unit related to the request signal when the interrupt processing means permits the requested interrupt to the central processing system. 4. The information transfer device according to claim 1, wherein the common transfer path transfers a fifth signal indicating a reception state of the information from the fourth signal transmission means. Signal control means, wherein the control means inspects a reception state of the information from the fourth signal transmission means, and outputs a fifth signal corresponding to the inspection result to the fifth signal transmission means. An information transfer device characterized by: 5. The information transfer apparatus according to claim 1, wherein the clock frequency is about 5 MHz to about 10 MHz.
An information transfer device characterized by being in the MHz range.