JPH07107478A - Sub screen data output circuit - Google Patents

Abstract

PURPOSE:To provide a sub screen without color slurring by displaying a video signal at the time of the 1st encoding processing on the sub screen after the reverse orthogonal conversion and performing the sub screen display of the still picture with the use of a video signal held in a holding means at the time of the 2nd encoding processing. CONSTITUTION:A changeover switch 85 guides the output of a reverse DCT circuit 46 to an output terminal 51 when a video signal at the time of refresh processing is supplied. A video signal at the time of refresh processing is an original picture element value as it is and requires no moving compensation processing. Thus, aliasing elimination is performed on the video signal by an LPF arithmetic circuit 45 and the reverse DCT processing reducing the size of the main screen into one sixteenth is performed by the reverse DCT circuit 46. Thus the video signal is outputted as the one for the sub screen from the output terminal 51 and is kept in a holding circuit 86. On the other hand, when the video signal at the time of non-refresh processing is supplied, the switch 85 is switched to guide the video signal at the time of refreshing kept in the circuit 86 to the terminal 51.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video compression signal decoding system for decoding a video signal compressed and coded by a hybrid DCT (discrete cosine transform) method including motion prediction coding, and more particularly to the decoding thereof. The present invention relates to improvement of a sub-screen data output circuit that outputs sub-screen data of a generated video signal.

[0002]

2. Description of the Related Art As is well known, a high-efficiency compression coding apparatus for performing compression coding processing on a video signal by a hybrid DCT method including motion prediction coding is constructed as shown in FIG. That is, the luminance signal Y and the color signal C input to the input terminals 11 and 12 are input to the preprocessing circuit 1
3, the pixel rearrangement processing is performed in units of blocks (8 × 8 pixels = 64 pixels) each having 8 pixels in the horizontal direction and 8 pixels in the vertical direction, and then the subtraction circuit 14 and the motion vector detection circuit 15 respectively. Supplied. In the subtraction circuit 14, a subtraction process described later is performed, and its output is DCT.
It is input to the circuit 16. The DCT circuit 16 fetches pixels in the block unit and outputs a coefficient obtained by converting the pixel array from the time domain to the frequency domain.

Each coefficient output from the DCT circuit 16 is
The quantization circuit 17 quantizes the signal to a finite level. In this case, the quantization circuit 17 has 32 types of quantization tables, and each coefficient is quantized based on the selected quantization table. In the quantization circuit 17,
The quantization table is provided so that the amount of generated information and the amount of transmitted information are within a certain range.

The coefficient data output from the quantizing circuit 17 is zigzag-scanned from the low band to the high band for each unit block and is extracted, and then is input to the variable length coding circuit 18 to continue the zero coefficient. Variable length coding is performed by using a number (run length) and a non-zero coefficient as one set. The encoder is
This is a variable-length encoder whose code length differs depending on the frequency of occurrence of Huffman code and the like.

The variable-length coded data is input to the buffer memory 19 and read at a prescribed speed, and then supplied to the next stage multiplexer (not shown) via the output terminal 20 and sent to the transmission path. To be done. Buffer memory 19
Is a variable rate output of the variable length coding circuit 18,
Since the rate of the transmission path is a fixed rate, it serves as a buffer that absorbs the difference between the generated code amount and the transmitted code amount. Further, the data indicating the memory occupation amount of the buffer memory 19 is supplied to the quantization circuit 17 to be used for selection of the quantization table, so that the buffer memory 19 is controlled so as not to overflow.

The output of the quantization circuit 17 is the inverse quantization circuit 2
It is input to 1 and inversely quantized. Further, the output of the inverse quantization circuit 21 is input to the inverse DCT circuit 22 and returned to the original signal. This signal is delayed by the frame memory 24 via the adder circuit 23. Frame memory 2
The output of 4 is supplied to the motion compensation circuit 25 and the motion vector detection circuit 15, respectively.

The motion vector detection circuit 15 compares the preprocessed signal with the output signal of the frame memory 24, detects the overall motion of the image, and detects the phase position of the signal output from the motion compensation circuit 25. To control. The output of the motion compensation circuit 25 can be supplied to the subtraction circuit 14 via the switch 26, and can also be fed back from the addition circuit 21 to the frame memory 22 via the switch 27. Switch 2
6, 27 are controlled to be turned on and off based on the refresh signal supplied to the input terminal 28.

The basic operation of this encoding means includes refresh processing and non-refresh processing. When the non-refreshing process is performed, the switches 26 and 27 are both controlled to the off state. The signal after preprocessing is DCT
The circuit 16 transforms the time domain into the frequency domain, and the quantization circuit 17 quantizes it. This quantized signal is subjected to variable length coding processing, and is then stored in the buffer memory 1
It is output to the transmission line via 9.

The quantized signal is returned to the original signal by the inverse quantization circuit 21 and the inverse DCT circuit 22, and delayed by the frame memory 24. Therefore, in the non-refresh processing, it is equivalent to that the information of the input video signal is variable length coded as it is. This non-refresh process is
The scene change of the input video signal and a predetermined block unit are performed at an appropriate cycle.

When the refresh process is performed, the switches 26 and 27 are both controlled to be in the ON state.
Therefore, the subtraction circuit 14 obtains a signal (prediction error signal) corresponding to the difference between the input video signal and the prediction signal obtained by motion-compensating the video signal one frame before with the motion vector. This difference signal (= prediction error signal) is input to the DCT circuit 16, converted from the time domain to the frequency domain, and quantized by the quantization circuit 17. Since the differential signal and the video signal are added to the frame memory 24 by the adder circuit 23 and input, a predicted video signal that predicts the input video signal that is the source of the differential signal is created and input. It will be.

Here, the motion vector detection circuit 15, the inverse quantization circuit 21, the inverse DCT circuit 22, the addition circuit 23, the frame memory 24, the motion compensation circuit 25 and the switch 26,
Motion compensation in a local decoder composed of 27 etc.
In general, the luminance signal Y and the color signal C are separately applied, but the motion vector itself substitutes a part of the motion vector for the luminance signal Y as the motion vector for the color signal C in order to simplify the apparatus. In many cases.

If the motion vector for the luminance signal Y is 6 bits, the motion vector for the color signal C is substituted with the upper 5 bits of the motion vector for the luminance signal Y. In addition, the refresh signal supplied to the input terminal 28 is periodically (for example, 1) in order to prevent transmission of an error generated in the transmission line.
It is a timing control signal used for the purpose of transmitting the original pixel value itself instead of the prediction error signal in 0 frame period. Then, the refresh processing timing and the motion vector are multiplexed and transmitted with the compression-coded output data.

On the other hand, FIG. 5 shows a high-efficiency decoding apparatus for performing a decoding process on a video signal compression-coded as described above. That is, the compression-encoded video signal supplied to the input terminal 29 is temporarily stored in the buffer memory 30, read by the variable-length decoding circuit 31 at a variable rate, and then the inverse quantization circuit 32 and the inverse DCT. Circuit 3
At 3 the original signal is restored.

The output of the inverse DCT circuit 33 is the addition circuit 34.
After that, the post-processing circuit 35 rearranges the pixels in the reverse order of the pre-processing, so that the luminance signal Y and the color signal C are generated and taken out from the output terminals 36 and 37.
The output of the adder circuit 34 is delayed by the frame memory 38 and then input by the motion compensation circuit 39 to the input terminal 40.
Is subjected to motion compensation processing based on the motion vector supplied to the adder circuit 34 and is supplied to the adder circuit 34 via the switch 41. The switch 41 is on / off controlled based on the refresh signal supplied to the input terminal 42.

When the video signal at the time of refresh processing is supplied to the input terminal 29, the switch 41 is controlled to the off state, the output of the inverse CDT circuit 33 passes through the adding circuit 34, and then the post-processing circuit 35. Is subjected to post-processing and is taken out from the output terminals 36 and 37 and stored in the frame memory. When the prediction error signal at the time of the non-refreshing process is supplied to the input terminal 29, the switch 41 is controlled to the ON state, and the output of the inverse CDT circuit 33 is added to the video signal stored in the frame memory 38. After that, the post-processing circuit 35 performs post-processing, takes out from the output terminals 36 and 37, and stores it in the frame memory.

By the way, in recent television receivers, those having a function of playing back a channel being viewed (main screen playback) at the same time as playing back another channel on a sub-screen have become popular. Further, since the size of the sub-screen in the television receiver is usually smaller than the size of the main screen, high image quality is not always required for the sub-screen.

FIG. 6 shows a sub-screen reproducing circuit for the video signal compressed and encoded as described above, and the same parts as those in FIG. That is, the input terminal 43
The output of the inverse quantizing circuit 32 supplied to the inverse quantizing circuit 32 is inversely DCT-processed by the inverse DCT circuit 33 in a block unit of 8 × 8 pixels = 64 pixels, and then added by the adding circuit 3.
4, the motion compensation loop including the frame memory 38, the motion compensation circuit 39, and the switch 41 performs motion compensation based on the 6-bit (upper 5 bits for the color signal C) motion vector supplied to the input terminal 40, and outputs It is sent to the post-processing circuit 35 through the terminal 44, and the main screen reproduction is performed there.

On the other hand, the dequantized signal supplied to the input terminal 43 is an LPF (low pass filter) operation circuit 45.
After the aliasing is removed by the inverse DCT circuit 46,
By the block unit of 2 × 2 pixels = 4 pixels, that is, 1/16 of the processing block in the inverse DCT circuit 33.
Inverse DCT processing is performed. The output of the inverse DCT circuit 46 is output by a motion compensation loop including an adder circuit 47, a frame memory 48, a motion compensation circuit 49, and a switch 50 that is on / off controlled based on the refresh signal supplied to the input terminal 42. Upper 4 bits of the motion vector supplied to the input terminal 40 (upper 3 bits for the color signal C)
The motion compensation is carried out based on the above, and it is taken out through the output terminal 51, and the sub screen reproduction of 1/16 the size of the main screen is performed there.

However, in the conventional sub-screen reproducing circuit as described above, it is premised that the prediction error signal which is the output of the inverse DCT circuit 46 is subjected to the motion compensation processing by the 6-bit motion vector. There is a problem in that the reproduction of the movement of the luminance signal Y and the color signal C on the screen is deviated and the color is deviated.

Next, FIG. 7 shows a two-way CATV (cable television) system. That is, the headend 52 has a terrestrial broadcast reception system 53, a satellite broadcast reception system 54, and a subscriber database management system 55. Further, the head end 52 is connected to a plurality of external database institutions 57, 57, ..., 57 via a public line or an ISDN line 56. The external database period 57, 57, ..., 57 is, for example, an airline company, a railway company, or the like.

The television signals received by the terrestrial broadcast receiving system 53 and the satellite broadcast receiving system 54 are transmitted to the headend 5.
Introduced in 2. In the headend 52, the television signal is converted to the conventional NTSC format for free broadcasting and then AM-modulated, and for the pay broadcasting, the television signal is digitally processed or scrambled and then 64QAM modulated. After being mixed and mixed, it is converted into an optical AM signal. This optical AM signal is sent to the optical output end of the head end 52.

The subscriber database management system 5
A bidirectional communication path is established between the HIB (Home Information Box) 58 and the control computer 5 (not shown). That is, the downlink data from the head end 52 to the HIB 58 is QPSK-modulated, mixed with the above-mentioned pay broadcast or free broadcast signal, etc., subjected to optical AM conversion, and sent to the optical output end of the head end 52. The upstream data from the HIB 58 is sent to the headend 52.
It is demodulated by the internal QPSK demodulator and introduced into the control computer. The optical input end of the head end 52 is connected to a QPSK data demodulator via an optical / electrical converter.

The head end 52 is capable of star connection and has a plurality of light input terminals and a plurality of light output terminals corresponding thereto. FIG. 7 shows one example of use. One pair of the optical input terminal and the optical output terminal of the head end 52 is connected to the optical / optical interface via the optical fiber cable 59.
It is connected to the optical output terminal and the optical input terminal of the electrical converter 60. The television signal and the data signal converted into an electric signal by the optical / electrical converter 60 are provided to the HIB 58 via the coaxial cable distribution system 61.

The upstream data from the HIB 58 to the head end 52 is QPSK modulated and is then sent to the coaxial cable distribution system 6
1, transferred to the headend 52 via the optical / electrical converter 60 and the optical fiber cable 59. The optical / electrical converter 60 is installed for 200 to 500 subscribers.

The output signal of the HIB 58 is the home coaxial wiring system 621, 622, 623, 624, 625, 626, 62.
It is supplied in parallel to the television receivers 631 and 632 and VTRs (video tape recorders) 641 and 642 in each room through 7, 628 and 629, and to the television receiver 633 through the expansion unit 65. Supplied. That is, for example, the output terminal of the HIB 58 is connected to the distributor 661 via the coaxial cable 621, one distributor output terminal of the distributor 661 is connected to the distributor 662 via the coaxial cable 622, and the other distributor output terminal is connected to the distributor 661. Distributor 6
It is connected to 63.

One distribution output terminal of the distributor 663 is connected to the expansion unit 65, and the other distribution output terminal is VT.
It is connected to R641. A television receiver 633 and a facsimile device 67 are connected to the expansion unit 65 via a twisted pair. Distributor 662
One distribution output terminal is connected to the television receiver 631 and the other distribution output terminal is connected to the distributor 664 via the coaxial cable 627. One distribution output terminal of the distributor 664 is connected to the VTR 64 via the coaxial cable 628.
2 and the other distribution output terminal is coaxial cable 62
It is connected to the television receiver 632 via 9.

The HIB 58 can also receive the usage data from the gas meter 68, the electricity meter 69, and the water meter 70 in the form of serial data baseband. Further, the switch data of the fire alarm 71 and the door sensor 72 are similarly supplied to the HIB 58 in an ON / OFF format.

On the other hand, the remote control unit 73
Addresses are assigned to 1, 732 and 733, respectively. Then, using the 1 MHz width of the 454 MHz band, the remote control unit 731
, 732, 733, and 455M
Communication from the remote control units 731, 732, 733 to the HIB 58 is performed using the 1 MHz width of the Hz band.

FIG. 8 shows the internal structure of the HIB 58. HIB58 can be roughly classified into two types.
One is the external bus control unit 741, the image / voice switch 7
42, two-way communication unit 743, image display memory 744,
Basic block 74 consisting of main memory 745, internal bus 746, CPU 747 and start program memory 748
And other functional block groups. The other functional block groups can be further classified into two groups: NTSC / RF modulators 751, 752, 753 and HDTV / RF modulator 761.
, 762, which are not connected to the external bus 77, and those which are connected to the external bus 77, like other units. In any case, there is a physical limit but no logical limit to how many functional blocks to use. The functional blocks connected to the external bus 77 include receiving units 781, 782, 783, moving image processing units 791, 792, 793, still image processing units 801, 802, 803, a display management control unit 81 and a data management control unit 82. There is.

During normal moving image reproduction, the CATV signal is received by the receiving units 781, 782 and 783, and the demodulated data is supplied to the external bus 77. This data is input to the moving image processing units 791, 792, 793, converted into an analog signal and passed through the video / audio switch 742 to the NTSC / RF modulators 751, 752.
, 753, and domestic coaxial wiring system 621 to 629
Via the television receiver 63 to 633 or VT
It is supplied to R641 and 642.

Receiving units 781 to 783, moving image processing units 791 to 793, still image processing units 801 to 8
03, NTSC / RF modulators 751 to 753 and HDT
A plurality of systems of V / RF modulators 761 to 763 are provided to simultaneously receive and demodulate a plurality of channels and supply signals of the respective channels to arbitrary television receivers 63 to 633 and VTRs 641 and 642. This is so that it can be done. These units can be easily added to the external bus 77.

Furthermore, the rewritable disk control unit 83 and the printer format conversion control unit 84 can be connected to the external bus 77. When the rewritable disc control unit 83 is provided, the disc reproducing device can be controlled. When the printer format conversion control unit 84 is provided, a printer can be connected to perform format conversion suitable for the printer, or an image can be converted into a format for outputting by facsimile. The data in this case is input to the bidirectional communication unit 743 of the basic block 74 via the external bus 77 and sent to the expansion unit 65.

A display management control unit 81 and a data management control unit 82 can also be connected to the external bus 77. When the display management control unit 81 is connected, for example, it is possible to have a function of temporarily storing a video signal of a moving image that has been sent, and performing still reproduction and output. Further, the data management control unit 82 manages the functional blocks connected to the external bus 77. For example, when the data management control unit 82 is connected, it is possible to perform management such that while a still reproduction image of a video signal of a certain channel is being sent, it is sent to the display unit of the system of another channel.

The basic block 74 is, as described above, the external bus control unit 741, the image / voice switch 742, the bidirectional communication unit 743, the image display memory 744, and the main memory 7.
45, an internal bus 746, a CPU 747 and a start program memory 748. The system startup program is stored in the startup program memory 748, and
The PU 747 reads the startup program via the internal bus 746 and operates the system based on this program. A main memory 745 is connected to the internal bus 746 and is used for temporarily storing various data.

The internal bus 746 has a memory 7 for image display.
4 4 is connected. This image display memory 744
Is used for superimposing reception channel data, warning data, operation guide data, etc., and its output is sent to the display section of the corresponding channel via the image / audio switch 742. further,
An external bus control unit 741 is connected between the internal bus 746 and the external bus 77.

The external bus control unit 741 has a basic block 7
The operation of each part of No. 4 and the operation of each part outside the basic block 74 are generally managed through the internal bus 746 and the external bus 77. For example, the function block is grasped and the operation timing is set. The external bus control unit 741
Control data can be sent to the data management control unit 82,
Based on this, the data management control unit 82 can control the functional blocks connected to the external bus 77.

The bidirectional communication unit 743 includes a communication unit 743a for performing bidirectional communication with the remote control units 731 to 733, a communication unit 743b for performing bidirectional communication with the expansion unit 65, and the head end 52. Communication unit 743c for performing two-way communication with, gas, electricity,
It has a communication unit 743d for performing bidirectional communication with meters 68 to 70 such as water supply and a latch unit 743e for sending out security-related information.

The interactive CATV system as described above is
One HI service is provided for a plurality of television receivers 631 to 633 and VTRs 641 and 642 in one home.
It is controllable by the B58, and a plurality of moving image processing units 791 to 793 are installed in the HIB58. In this case, a service channel A
On the other hand, when there is a request to play back the main screen on the television receiver 632 and to play back on the sub screen on the television receiver 631, there is a request to view the main screen and the sub screen for channel A inside the HIB 58. You need to play both. If such a service is to be provided to a plurality of television receivers, the main screen reproducing unit and the sub-screen reproducing unit are required for each of the television receivers, which causes an economical disadvantage. Occurs.

[0039]

As described above, the conventional sub-screen reproduction circuit has a problem that the reproduction of the movement of the luminance signal and the color signal on the sub-screen is deviated to cause the color deviation. . Further, if sub-screen reproduction is attempted for a plurality of television receivers, sub-screen reproducing units for the number of television receivers are required, which is economically disadvantageous.

Therefore, the present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a sub-screen data output circuit which can obtain a sub-screen without color shift. Further, the present invention provides a sub-screen data output circuit capable of realizing sub-screen reproduction for a plurality of television receivers without using sub-screen reproducing units for the number of television receivers. With the goal.

[0041]

A sub-screen data output circuit according to the present invention divides a television image of one frame into a plurality of spatial blocks and performs an orthogonal transform process on each block to obtain an orthogonal pattern. It is obtained by performing a first coding process of quantizing transform coefficients and variable-length coding, and dividing a television image having a difference between frames into a plurality of spatial blocks and performing an orthogonal transform process for each block. A second encoding process of quantizing the orthogonal transform coefficient and performing variable length encoding,
The target is a high-efficiency decoding system that decodes a high-efficiency coded signal obtained by adaptively repeating the motion vector of an image to reproduce a main screen.

Then, a filter calculation means for performing a filter calculation process for eliminating aliasing on the signal obtained by subjecting the high efficiency coded signal to the variable length decoding process and the inverse quantization process,
An inverse orthogonal transforming means for dividing the output of the filter computing means into a block size smaller than the block size set in the first and second encoding processes and performing an inverse orthogonal transforming process for each block, and the inverse orthogonal transforming means. Holding means for holding the component that has been subjected to the first encoding processing among the outputs of the above, and updating the held content every time the component is supplied, and the signal held in this holding means is used as the sub-screen data. It is configured to.

Further, in the above, a plurality of holding means are installed, and the filter calculating means and the inverse orthogonal transforming means perform time-division processing on the high-efficiency coded signals of a plurality of channels, and the processed signals. Is selectively supplied to a plurality of holding means, so that sub-screen reproduction of a plurality of channels can be performed.

[0044]

According to the above construction, the video signal at the time of the first encoding processing is subjected to the inverse orthogonal transformation processing and is directly used for the sub-screen display and is held by the holding means so that the video signal at the time of the second encoding processing is While the prediction error signal is being received, the sub-screen is displayed as a still image by the video signal held in the holding means. Therefore, the motion vector is used when performing the sub-screen playback process as in the conventional case. Since the previous motion compensation is not performed, it is possible to solve the problem that the reproduction of the motion of the luminance signal and the color signal on the sub-screen is deviated to cause the color misregistration.

Further, since the filter calculation means and the inverse orthogonal transformation means perform the time-division processing on the high-efficiency coded signals of a plurality of channels, the sub-screen reproducing units for the number of television receivers are provided. It becomes possible to realize sub-screen reproduction for a plurality of television receivers without using.

[0046]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. In FIG. 1, the same parts as those in FIG. 6 are designated by the same reference numerals. That is, the inverse D
The image signal for the sub-screen, which has been inversely DCT-processed by the CT circuit 46 in a block unit of 2 × 2 pixels = 4 pixels, that is, 1/16 of the processing block in the inverse DCT circuit 33, is supplied to the input terminal 42. The changeover switch 85, which is controlled to be switched by the refresh signal, switches between a route that leads to the output terminal 51 as it is and a route that leads the video signal held in the previous value holding circuit 86 to the output terminal 51.

The changeover switch 85 is provided for the inverse DCT circuit 4 when the video signal at the time of refresh processing is supplied.
The output of 6 is switched so as to be guided to the output terminal 51.
Since the video signal at the time of the refresh processing is the original pixel value itself and does not require the motion compensation processing, the LPF arithmetic circuit 45 performs aliasing removal on this video signal, and the inverse DCT circuit 46 adjusts the size of the main screen. The inverse DCT processing reduced to 1/16 is performed, and the video signal output from the inverse DCT circuit 46 is output from the output terminal 51 for the sub screen and is held in the previous value holding circuit 86.

On the other hand, when the video signal (prediction error signal) in the non-refreshing process is supplied, the changeover switch 85 outputs the video signal in the refreshing process held in the previous value holding circuit 86 to the output terminal 51. Can be switched to lead to. Therefore, if a video signal that has been refreshed once in 10 frames is received, for example, a still image is generated by the video signal held in the previous value holding circuit 86 during the 9-frame period during the non-refreshing process. The sub-screen is displayed with. When the refreshed video signal is received, that is, 10
The contents (sub-screen) of the previous value holding circuit 86 are updated once per frame.

Therefore, according to the configuration of the above embodiment, the video signal at the time of the refresh processing is directly used for the sub-screen display after the inverse CDT processing and the previous value holding circuit 8 is provided.
6 and the sub-screen display is performed as a still image by the video signal held in the previous value holding circuit 86 during the period in which the prediction error signal in the non-refreshing process is received. Since the motion compensation using the motion vector is not performed at the time of performing the sub-screen reproduction processing, it is possible to solve the problem that the reproduction of the motion of the luminance signal and the color signal on the sub-screen is deviated to cause the color misregistration. .

FIG. 2 shows another embodiment of the present invention, and shows a configuration in the bidirectional CATV system shown in FIG. 7 when a plurality of main screen outputs and sub-screen outputs are simultaneously obtained. . That is, the inverse quantized outputs supplied to the plurality (three in the case shown) of the input terminals 431, 432 and 433 are the inverse DCT circuit 33, the adder circuit 34, the frame memory 38, the motion compensation circuit shown in FIG. Main screen reproducing circuits 871, 872, 8 composed of 39 and switches 41
It is taken out from the output terminals 441, 442 and 443 via 73 and is used for main screen display. Each main screen reproduction circuit 871, 872, 873 has an input terminal 401
, 40 2 and 40 3 are supplied with the respective motion vectors.

On the other hand, each input terminal 431, 432, 433
The inverse quantized output supplied to each of the
8 is selected, the aliasing is removed by the LPF arithmetic circuit 45, and the size is 1/1 of the main screen by the inverse DCT circuit 46.
After the inverse DCT processing reduced to 6, the changeover switch 89
Is selectively led to each changeover switch 851, 852, 853. Changeover switches 851, 852, 853
Are controlled by sub-picture update signals generated from the timing generation circuit 90 based on the refresh signals supplied to the input terminals 421, 422 and 423. The other changeover switches 88 and 89 are switch-controlled by a time division changeover signal generated from the timing generation circuit 90.

FIG. 3 shows the update timing of the sub-screen. That is, if the refresh signals shown in FIGS. 3A, 3B, and 3C are supplied to the input terminals 421, 422, and 423, the timing generation circuit 90 outputs the changeover switches 851, 852, and 853 to the changeover switches 851, 852, and 853. , Fig. 3
As shown in (d), (e) and (f), sub-screen update signals are supplied at timings where they do not overlap each other, and the sub-screen outputs taken out from the output terminals 441, 442 and 443 are output as shown in FIG. 3 (g). , (H), (i) are updated at the timings shown.

Therefore, according to the embodiment shown in FIG.
LPF arithmetic circuit 45 and inverse DCT provided for sub-screen reproduction
Since the circuit 46 and the three types of video signals are shared and used in a time-divisional manner, a plurality of television receivers can be used without using sub-screen reproducing units for the number of television receivers. It becomes possible to realize sub-screen reproduction. The present invention is not limited to the above-described embodiments, but can be variously modified and implemented without departing from the scope of the invention.

[0054]

As described above in detail, according to the present invention,
A sub-screen data output circuit that can obtain a sub-screen without color shift can be provided. Further, according to the present invention, there is provided a sub-screen data output circuit capable of realizing sub-screen reproduction for a plurality of television receivers without using sub-screen reproducing units for the number of television receivers. can do.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a sub-screen data output circuit according to the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of the other embodiment.

FIG. 4 is a block configuration diagram showing a high-efficiency compression encoding device.

FIG. 5 is a block diagram showing a high efficiency decoding device.

FIG. 6 is a block configuration diagram showing a conventional sub-screen reproduction circuit.

FIG. 7 is a block diagram showing a bidirectional CATV system.

FIG. 8 is a block configuration diagram showing details of a HIB of the system.

[Explanation of symbols]

11, 12 ... Input terminal, 13 ... Preprocessing circuit, 14 ... Subtraction circuit, 15 ... Motion vector detection circuit, 16 ... DCT circuit, 17 ... Quantization circuit, 18 ... Variable length coding circuit, 19
... buffer memory, 20 ... output terminal, 21 ... inverse quantization circuit, 22 ... inverse DCT circuit, 23 ... addition circuit, 24 ... frame memory, 25 ... motion compensation circuit, 26, 27 ... switch, 28, 29 ... input terminal , 30 ... Buffer memory, 3
1 ... Variable length decoding circuit, 32 ... Inverse quantization circuit, 33 ... Inverse DCT circuit, 34 ... Addition circuit, 35 ... Post-processing circuit, 3
6, 37 ... Output terminal, 38 ... Frame memory, 39 ... Motion compensation circuit, 40 ... Input terminal, 41 ... Switch, 42,
43 ... Input terminal, 44 ... Output terminal, 45 ... LPF arithmetic circuit, 46 ... Inverse DCT circuit, 47 ... Addition circuit, 48 ... Frame memory, 49 ... Motion compensation circuit, 50 ... Switch, 5
DESCRIPTION OF SYMBOLS 1 ... Output terminal, 52 ... Head end, 53 ... Terrestrial broadcast receiving system, 54 ... Satellite broadcast receiving system, 55 ... Subscriber database management system, 56 ... ISDN line, 57 ... External database organization, 58 ... HIB, 59 ... Optical fiber cable, 60 ... Optical / electrical converter, 61 ... Coaxial cable distribution system, 621 to 629 ... Home coaxial wiring system, 631 to 63
3 ... Television receiver, 641, 642 ... VTR, 6
5 ... Expansion unit, 661-664 ... Distributor, 67 ... Facsimile device, 68 ... Gas meter, 69 ... Electricity meter, 70 ... Water meter, 71 ... Fire alarm, 72 ... Door sensor, 731-733 ... Remote control unit, 74 … Basic blocks, 751 to 753… NTSC ・
RF modulator, 761 to 763 ... HDTV / RF modulator,
77 ... External bus, 781-783 ... Receiving unit, 791
... 793 ... moving image processing unit, 801 to 803 ... still image processing unit, 81 ... display management control unit, 82 ... data management control unit, 83 ... rewritable disk control unit,
84 ... Printer format conversion control unit, 85 ... Changeover switch, 86 ... Previous value holding circuit, 871 to 873 ... Main screen reproduction circuit, 88, 89 ... Changeover switch, 90 ... Timing generation circuit.

Claims (2)

[Claims] 1. A first coding for quantizing and variable-length coding an orthogonal transform coefficient obtained by dividing a one-frame television image into a plurality of spatial blocks and subjecting each block to an orthogonal transform process. Processing, and a television image obtained by taking the difference between frames is divided into a plurality of spatial blocks, and orthogonal transformation processing is performed for each block, and the obtained orthogonal transformation coefficient is quantized and variable length coding is performed. In the high-efficiency decoding system for decoding the high-efficiency encoded signal obtained by adaptively repeating the encoding process and the motion vector of the image to reproduce the main screen, A filter calculation means for performing a filter calculation process for removing aliasing on the signal subjected to the variable length decoding process and the dequantization process, and the output of the filter calculation means are the first
And an inverse orthogonal transform unit that divides into a block size smaller than the block size set in the second encoding process and performs an inverse orthogonal transform process for each block, and the first code of the output of the inverse orthogonal transform unit. And holding means for holding the component which has been subjected to the conversion processing and updating the held content every time the component is supplied, and is configured so that the signal held in this holding means is used as sub-screen data. A sub-screen data output circuit characterized by the following. 2. A plurality of the holding means are installed, and the filter computing means and the inverse orthogonal transforming means process the high efficiency coded signals of a plurality of channels in a time division manner,
2. The sub-screen data output circuit according to claim 1, wherein the processed signal is selectively supplied to a plurality of holding means so that sub-screen reproduction of a plurality of channels can be performed.