JPH0679294B2 - Address conversion method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates generally to computer storage subsystems, and more particularly to storage subsystems organized into storage devices known to those of ordinary skill in the art as virtual storage. More particularly, the present invention relates to an apparatus for translating virtual addresses into real addresses and performing specific control functions within the storage hierarchy.

B. Conventional technology and its problems In the latest computer systems, a program is executed at some level in the system, that is, at a certain level in the cache / main memory / direct access memory (DASD) or a distributed system network. Frequently attempt to access data or code that resides on another node in the. For the most basic system, consider what a program needs to understand to make this access.

-Where is the data (or code) located? The case generally determines what kind of address should be used for access. (For example, a 24-bit main storage address, a disk sector address, or a network node address). It also depends on the location what kind of instruction should be used to accomplish the access (eg load / store / branch for main memory access, channel command word for disk access, network instruction word for network access). Communication protocol).

-Is this data shared by other programs? If this data is shared, access cannot proceed unless a certain lock is maintained. If you do not want other programs to be aware of the data changes this program is trying to make, it should be directed to a store instruction or private address.

-Should the data be recoverable? If so, some journaling method must be implemented so that the data in the same state as before can be retrieved when needed.

In such a very basic system, it is assumed that the program was actually required to distinguish between them on each access. Then, the following things will happen.

− Generally, when trying to make a program eligible for subversion,
Even with the most frequent "simple and secure" requests, in other words, with private unrecoverable data residing in main memory, its access would be very slow.

-If you lock the access mode to one for the program to work well, the program will not execute correctly for data with different properties.

-Programs will be complex, large, and error-prone.

Recent systems have addressed these issues to varying degrees. For example: -By means of the relocation architecture, private non-recoverable temporary data and programs are generally provided with 16- or 32-bit address sizes (usually adequate for computational temporary needs). Can be uniformly addressed. If the relocation architecture is implemented using suitable "index" hardware, then most such accesses will be at the cache or main memory speed. If this indexing hardware is useless (less than 100 trials and 1 occurrence)
Only the system accesses the relocation table structure. Only if the relocation table is useless (i.e., the data is not in main storage) does the system experience a "page fault" overhead. Therefore, the overhead is resolved only when it is really needed. This is the purpose of good architecture and its practice.

-When maintaining data beyond the scope of program execution, modern systems use an "access method" implemented by software instead of load / store / branch instructions.
Access is requested by an explicit request for. Such access methods generally support data organized into a defined set of foundations called "records" and "files.""Instructions" for accessing are generally "read / write" or "get / write".
It is called "Putto".

Data is not shared or is unrecoverable. It may actually be stored in main memory (a certain buffer area). However, on every access, the program must make such an explicit "read / write" call. Thus, if the access scheme is well defined, it produces a program that is less complex and generally applicable than in the underlying system. However, the performance of such access is uniformly inferior to load / store, requiring the data to be accessed to be organized into the appropriate foundation type.

-Modern systems require explicit requests to software-implemented "database subsystems" where data is shared or recoverable. Such access is generally much slower than access with the access method. This is not only due to the addition of lock and journal management functions, but also because the types of foundation groups (eg relationships, hierarchies) supported by subsystems are themselves more complex.

Again, the data may actually be in a buffer of main memory with a much simpler structure, but with each access request an overhead problem arises.

Some systems support the temporary recovery of data using a means called "checkpointing". In this case, if the program wants to write a recoverable application, it has to deal with three different means. The three means are checkpointing for computational data, explicit backups for files, and "commitment" instructions for databases.

The IBM System / 38 is ahead of the vast majority of systems, at least in terms of providing a uniform addressing structure for all data. However, this is provided at the cost of all addresses being very long, many accesses being very slow, and requiring a lot of storage and hardware to perform the archiving, and It does not provide a uniform method for sharing or recovery.

Various techniques have been known for sharing a storage device by a large number of computer programs executed by one or a plurality of basic processing units. The storage device shared by the program requires an extremely large new storage capacity. Its capacity is often much larger than the actual capacity of the storage device. For example, if the system uses a 32-bit addressing scheme, 2 ³² bytes of addressable virtual memory are available. Such virtual storage space is usually considered to be divided into a predetermined number of areas or segments. Each segment is divided into pages of a certain number of lines, each line having a certain number of bytes. Therefore, specify the segment and page, that is,
The address assigned to the virtual memory is arbitrarily designated by the program and does not indicate the actual memory location in the main memory. Therefore, virtual segments and virtual pages are usually located at arbitrary locations throughout main storage, and can be swapped in from external storage to main storage or from main storage to external storage as needed. Swapping out.

Due to the variable position of segments and pages within main memory, translation from virtual addresses to true or real addresses is required. For this conversion, a set of address conversion tables called a page frame table is usually used in the main storage device. A large number of address translation tables are used in large virtual systems. This can be configured in various ways. An essential feature of any such configuration is that a particular virtual address must be logically mapped to a storage location in the table that contains the real address (if any) for that virtual address.

Functionally, the operation of such an address translation table is as follows: the upper bit of a particular virtual address is used to access a particular section of the translation table. The upper bits used relate to one particular frame or segment. The lower bits are then used to check whether the particular virtual address is contained therein and, if so, which real address is associated with it. Each page table specified by the virtual frame address includes the actual storage locations of all the pages included in one frame. Therefore, if one particular frame is divided into, for example, 16 pages, there are 16 page tables for each frame, and there is only one entry that specifies a particular set of page tables. There is another frame table. It should be understood that the above description is generalized and that there are many different ways of organizing address translation using page tables and page table addressing means starting from virtual addresses generated by the CPU. I want to be done. In the following description of the preferred embodiment of the invention, a hash address table (HAT) and a reverse page table (IPT) basically having the functional configurations as described above will be described in detail.

When doing the actual address translation, regardless of the details of the overall system configuration and the use of the page table, an appropriate entry point to the page frame table is created and the page is given using the given virtual address as an argument. The table is accessed. Then, typically through multiple storage accesses, the desired entry in the page table is found. Normally, it is checked at that point if all system protocols were followed, and if so, the real address of the requested page is accessed from the page table. The byte portion of the virtual address, or "byte offset," is essentially a relative address and is the same on the real and hypothetical pages. Therefore, the desired real page address part of the virtual address is
Once translated, the byte offset portion is concatenated with the real page address location to provide the real byte address of main memory.

As is well known in the current virtual memory system, recently used virtual address to real address conversion is performed so that it is not necessary to convert the virtual address each time the storage device is accessed. Stored in a set of high-speed accessible tables or high-speed storage devices called a registration index table (DLAT) or a translation index buffer (TLB) which is also used in. Such tables or buffers are usually special storage devices that can be accessed at high speed, which can be accessed even faster than the page frame table described above. Thus, by storing frequently used virtual addresses in this table and accessing them at high speed, the execution time of the computer can be saved significantly. The efficiency of the TLB address translation system is based on the fact that when a virtual page is accessed in a given program execution, the same page is subsequently accessed many times. As mentioned previously, the translation of a virtual page address to a real page address addresses which line or byte, even if the subsequent accesses are to different lines and bytes within the page. Regardless of the page, it's the same as far as the page goes.

Using TLB can significantly reduce the translations needed in the page frame table. Therefore, the performance of the entire virtual memory system can be significantly improved.

Another problem with such conventional repositioning systems is the handling of the journaling problem. That is, a copy of the data is held in the external storage device while the current program is executing and using the data. Therefore, in the event of any hardware or software failure, a valid copy of the original data is still available. Such a function has heretofore been realized by time-consuming complicated hardware and software, and again, the required journaling function comes at the expense of a reduction in the performance of the storage device.

As described above, in computer technology, virtual memory systems have become popular over the years. It is also well known that virtual addresses must be translated into real addresses by some relocation or address translation means. In such address translation means,
Translatability from virtual address to real address must be guaranteed. Although it is not possible to list all patents and papers related to this subject, the following prior art is a typical example of the address translation mechanism, and shows the prior art most closely related to the present invention.

U.S. Pat. No. 3,828,327 to Berglund et al. Shows a conventional storage control technique for expanding storage by adding higher bits to addresses. This upper bit is not part of the address specified by the program, but is controlled by another system mode such as interrupt mode, I / O mode. This patent relates to a storage expansion system, which is also provided with address translation hardware. U.S. Pat. No. 4,042,911 to Bourke et al. Or a system for main memory expansion is also shown, which explicitly includes address translation means. However, these two U.S. patents do not disclose the concept of virtual address extension, as well as providing special lock bits for both the TLB and page frame tables.

Paper, George Radin, “The 801 Minicomputer”, ACM
SIGPLAN NOTICES, Volume 17, Issue 4, April 1982, 3
Pages 9-47 provide a general description of experimental computers with operating characteristics that are highly dependent on very fast storage subsystems. The repositioning mechanism of the present invention may at times be suitable for such computers.

Bourke et al., U.S. Pat.No. 4050084, shows a memory configuration that includes an address relocation translator with a stack segmentation register.The special segmentation register shown in this patent is incorporated herein by reference. It is intended to store the real address assigned to a physical block in main memory, rather than the extended virtual address memory used.

U.S. Pat. No. 4,251,860 to Mitchell et al. Shows a storage addressing system having a virtual addressing device for implementing extended virtual address storage. This patent discloses dividing a virtual address into a segment portion and an offset portion. However, the segment part and the segment register related thereto are used as an appropriate means for performing address division.
The operation is completely different from that of the address translation mechanism of the present invention.

The system shown in U.S. Pat.No. 4,037,215 to Birney et al. Is very similar to U.S. Pat. No. 4050094 in that it utilizes a series of segmentation registers to specify a particular real storage block. There is. This patent also describes the use of "read-only" valid bits incorporated into a special segmentation register. These bits are quite different from the special purpose lock bits provided in the hardware of the relocation mechanism of the present invention.

U.S. Pat. No. 4,077,059 to Gordi et al. Shows a hierarchical storage system with special control means for facilitating journaling and copyback. Multiple dual storage devices are also shown in this patent. This keeps the current data in one storage device and posts the changes to the other storage device to facilitate subsequent journaling and copyback operations. The hardware and control means of this patent are quite different from the lockbit system of the present invention.

U.S. Pat. No. 4,053,948 to Hogan et al. Shows an address exchange system with special means including a counter for each entry in the Registration Index Table (DLAT).

U.S. Pat. No. 4,218,743 to Hoffman et al. Is a 1BM system.
Examples of a number of patents listed below with respect to the / 38 rearrangement architecture. This patent suggests a method for simplifying the addressing handled by I / O in a virtual memory computer system. Other patents related to the problem of virtual memory system are No. 4170039, No. 4251860, No. 4278762
And No. 4215402.

U.S. Pat. No. 4,020,466 to Cordi et al. Also shows a storage system incorporating special means to facilitate the journaling and copyback procedures. This patent has nothing to do with the lock bit control means of the present invention.

Although US Pat. No. 3,942,155 to Lawlor discloses a segmented form of a virtual storage system, the segmentation used in this patent is the segmentation operation of the present invention utilized to extend virtual addresses. Is completely different from.

As an example of accessing the virtual memory conversion mechanism using various hash methods, US Pat. No. 4,215,402 is cited.

C. Means for Solving the Problems In accordance with the techniques of the present invention, a virtual memory subsystem is provided that fully utilizes hardware and software for address translation and overall memory control functions. All data and programs in the system are recoverable, where they are, whether they are one hour, cataloged, shared or private Addressed uniformly regardless of whether it is unrecoverable or unrecoverable. This means that, for example, private unrecoverable computational data present in the cache can be recovered at the speed of the cache. On the other hand, even if the data is shared, access by a given program holding the key is also done at cache speed.

Thus, the configuration of the storage subsystem disclosed herein that allows for such a unified type of addressing, or "single level storage" addressing, uses 32 bit virtual addresses. This virtual address is generated by the CPU, of which 4 bits form a set 16
Specify 12-bit segment registers. The contents of the selected segment register and the remaining 28 of the virtual address
Bits are concatenated to generate a 40-bit effective address.
Accordance connexion, each segment will be able to include data up to 2 ²⁸ bytes is easily understood. Note that this new 40-bit address is still a virtual address. The 40-bit address is translated by first accessing a fast sub-associative translation lookaside buffer to determine if a real address exists. If the real address does not exist, the address conversion is performed by referring to the page table as in other conversion systems.

Another unique feature of this configuration is that it has locking not only in the translation index buffer, but also in the page frame table.
It is to provide a special lockbit for checking journaling and permits.

For each real address, the translation lookaside buffer and multiple lock bits in the page frame table (in the preferred embodiment,
16) are provided. One lock bit is provided for each line in a page and is used for journaling control in the system. Access means and software means are additionally provided in the system so that these bits can be accessed by software as well as by hardware.

The main object of the present invention is to provide a virtual storage subsystem having a very large virtual address space.

Another object of the present invention is to provide a storage subsystem that functions as a "single level storage device" in all storage operations.

Another object of the present invention is to provide a storage subsystem that is less susceptible to addressing errors due to the use of incorrect translation tables.

Another object of the present invention is to provide a control mechanism that makes journaling and associated data protection within such virtual storage subsystems extremely easy.

Another object of the present invention is to provide such a control mechanism that can be used with either software or hardware.

These and other objects, features and advantages of the present invention will become apparent from the detailed description of the preferred embodiments of the invention presented below as illustrated in the accompanying drawings.

D. Embodiments The objects of the present invention are generally achieved by the storage controller disclosed herein. This storage controller interfaces with a host CPU storage channel that implements the address translation architecture previously described in general form. The address translation architecture will be described in more detail later. The conversion mechanism is 16
Contains the logic required to interface with storage devices having capacities up to megabytes. The storage device may or may not be interleaved, and may be a static type or a dynamic type. The conversion mechanism is functionally divided into three sections (see Figure 1). CPU memory channel interface (CSC) 10 logic is common front end (C
It has a section 12 of FE). Section 12 provides the appropriate protocol from the storage channel to address translation logic 14 and storage control logic 16. All communication with the memory channel is handled by this logic. The address translation logic translates the virtual address received from the storage channel into a real address used to access the storage device.
This logic includes a translation lookaside buffer (TLB) configured as a two-way set associative with 16 congruence classes. Logic is provided to automatically reload TLB entries from the page table in main memory when needed. Storage control logic 16 provides the interface from address translation logic 14 to the storage device. This logic also provides dynamic memory refresh control.

The present invention is mainly based on the well-known computer circuit,
It relates to new combinations of devices and functional units and functional operations, not to their specific detailed structure. The structure, control and arrangement of these well known circuits, devices and blocks are therefore illustrated in the drawings in the form of easily understandable block representations and functional diagrams showing in detail only the parts relevant to the invention. ing.
This is to avoid obscuring the invention due to structural details. The structural details will be readily apparent to one of ordinary skill in the art based only on their functional description. Furthermore, in order to emphasize such features of the present invention, various parts of these systems are properly organized and functionally described. With the following description,
One of ordinary skill in the art will understand the feasibility of the disclosed storage subsystem and will further be able to incorporate it into any one of a variety of computer architectures.

FIG. 1 shows the above-mentioned functional parts of the present address translation system. This address translation system could be integrated into one logic chip by VLSI technology.

Whether the address is translated (virtual address) or real address in this system
It is controlled by the value of the conversion mode bit (T bit) on the CPU memory channel (CSC). Each device issuing a request to the CSC controls the value of the conversion mode bit on each request. The T bit is fetched from the appropriate field of the storage access instruction supplied by the CPU. For storage access by I / O devices, the T bit value is generated by the adapter connection function. If T bit is 1, the storage device address (instruction fetch, data load, data storage) is converted. If T bit is 0, the storage device address is treated as a real address.

In the architecture disclosed herein, storage protection is not effective for storage requests that are not translated.

The record of references and changes is valid for all storage devices, whether or not conversion is done.

When address translation is performed, the translation operation proceeds logically as shown below.

Further, the functions of different parts may be executed in parallel instead of the strict logical sequence shown below.

This address translator implements a "single level store" addressing structure. In the preferred embodiment disclosed herein, address translation supports the following:

1. Multiple independent virtual address spaces 2.4 gigabytes of address space 3. On demand paging 4. 2048 or 4096 bytes pages 5. Storage protection 6. Shared segment for instructions and data 7. 128-byte line journaling and locking 8.16 Real storage addressable up to megabytes 9. Browse and modify bits per real page 10. Hardware support for real address loads, TLB entry invalidation, and storage exception addresses Storage devices each have a capacity of 256 megabytes Is treated as if it were mapped to a single 40-bit virtual address space consisting of 4096 segments. Select one of the 16 segment registers using the upper 4 bits of the 32 bit address received from CSC,
By concatenating the 12-bit contents of the selected segment register with the remaining 28-bits of the effective address,
Converts a 32-bit address to a 40-bit (long form virtual) address. The translator then translates the 40-bit virtual address to a real address for storage access. As can be easily seen, it is possible to change the size of the virtual address with a slight change in the hardware.

The addressable storage capacity is always only 4 gigabytes. In other words, 16 segment registers can specify 16 segments each having a capacity of 256 megabytes. Accordingly, the operating system can create multiple independent virtual address spaces by loading the segment registers with the appropriate values. In limited cases, like this,
While it may be possible to generate 256 totally independent 4 gigabyte address spaces, it is more likely that some segments (such as core code) will be shared by multiple address spaces.

Storage protection similar to the IBM System / 370 is provided in 2K or 4K byte pages. Protection key (S / 37
Memory protection and retrieval protection is achieved by the equivalent of a key at 0 PSW). By loading the same value (segment identifier) into different segment registers, it becomes possible to share a segment between different tasks (especially useful for task open communication).

Support for persistent storage classes is provided by a set of lockbits associated with each virtual page. This lockbit effectively extends the granularity of storage protection to a “line” of storage (128 bytes for 2K pages, 256 bytes for 4K pages), thus allowing the operating system to modify persistent variables. Can be detected and automatically journaled. Persistent storage class, as used herein, means that its contents are permanently stored in, for example, a disk file storage device.

The following terms are used herein and are defined herein for clarity and convenience.

Byte index For 2 Kbyte pages, a number in the range O to 2047 (11 bits) to identify a single byte within a page or page frame [0 to 40 for 4 Kbyte pages.
95 (12 bits)]. The byte index is taken from the lower 11 bits [12 bits] of the effective address.

Change Bit The bit associated with each page frame.

Whenever a memory reference (write only) is successful for that frame, it is set to "1".

Effective Address A 32-bit stored channel address generated by the device on the stored channel. This address is the instruction fetch,
It can be generated by the host CPU when loading or storing data. It can also be generated by an I / O device on the storage channel, like a DMA address.

A 128-byte portion of a page with boundaries on each 128-byte line, which is the storage capacity controlled by one lockbit.

Lock Bit One of 16 bits associated with each page of the persistent storage segment. Each lock bit is associated with one line of storage. The transaction ID, write bit, and lock bit values are combined to determine, for one line, whether storage access requests are allowed or prohibited in the persistent storage segment.

20 pages separated by 2048-byte [or 4096-byte] boundaries
A storage unit of 48 bytes [or 4096 bytes]. "page"
Is really about virtual memory, while "page frames"
Is about real memory, but historically "pages" have been used for both virtual and real memory.

Page frames 20 separated by 2048-byte [or 4096-byte] boundaries
A storage unit of 48 bytes [or 4096 bytes]. Pages reside in page frames or on external storage (ie, disks).

Page table This is a combination of the entries in the hash anchor table and reverse page table in the main memory, and is used to translate virtual addresses into corresponding real addresses (also called HAT / IPT here).

Protection Key A one-bit value in each segment register that indicates whether the currently executing process can access the data in a given segment. This protect key is functionally similar to the IBM System / 370 PSW key, but applies individually to each segment rather than globally to all addressable storage. To be done.

As a result of the real address translation operation, the real page index (10
Bit or 13 bits) and the lower 11 bits [or 12 bits] of the effective address are concatenated (real page index || byte index).

Real page index O to 8192 for identifying page frames in real memory
Numerical value in the range of (13 bits). By reducing this value to 10 bits, the maximum amount of real storage may be limited to 2 Mbytes for 2 Kbyte pages.

Reference Bit The bit associated with each page frame. It is set to "1" whenever a storage reference (read or write) is successful for that frame.

Segment ID A numeric value in the range of 0 to 4095 (12 bits) for identifying a virtual memory segment of 256 MB. The segment ID and virtual page index are concatenated to specify one page in the 40-bit virtual address space.

Storage Key A two-bit value in each TLB entry that identifies the protection level associated with a particular page. This key is functionally similar to the storage key associated with each System / 370 page.

TLB translation index buffer mechanism. The TLB is hardware that includes a virtual-real map (although in some cases only part of this map is included in the TLB). In addition to this mapping, each TLB entry contains other information about the page associated with it, such as the translation ID, storage key, and lock bit.

Transaction ID A number in the range 0 to 255 (8 bits) that identifies the "owner" of the set of lock bits currently loaded in the TLB entry.

Virtual address A 40-bit address value formed in this address translation mechanism by concatenating the segment ID and the lower 28 bits of the effective address. (Ie segment ID || virtual page index || byte index).

Virtual page index A number in the range of 0 to 131072 (17 bits) [0 to 65536 (16 bits) for a 4 Kbyte page] for identifying one page in the virtual storage segment for a 2 Kbyte page. The virtual page index is fetched from the valid address bits 4 to 20 [4 to 19].

The symbol || represents a concatenation.

The hardware required to support this address translation mechanism is described below. It should be noted that the field width may be changed depending on the embodiment.

The TLB consists of an arbitrary number of entries, each entry controlling the translation of a page's temporary address to its real address.

The detailed structure of the TLB depends on the embodiment. Two embodiments are possible. Segment ID || Content address storage (CA) that is addressed by the virtual page index and contains one entry per real storage frame.
M). The CAM entry index (ordinal number) is equal to the real page index. A set-associative TLB addressed by some value in the lower bits of the fake page index. The real page index is contained in one field of the TLB entry.

The only constraint on the shape of the TLB is that the non-CAM type implementation must be at least two ways set associative. Each TLB entry is individually read or written by the CPU using the IOR and IOW instructions. The TLB entry contains the following fields.

32-bit valid input address (from CPU or I / O device)
Is first expanded to a 40-bit virtual address by concatenating the segment identifier to the effective address.
The virtual address is then provided to the translation hardware for translation into an equivalent real address. The virtual address is converted into a real address by the process shown below.

The segment table is searched using the upper 4 bits of the input effective address and one of 16 segments is selected. The 12-bit segment identifier, the "special segment" bit, and the key bit are obtained from the selected segment register. The 12-bit segment identifier is used to generate a virtual address. The special segment bit and key bit are used for the following access validation. FIG. 2 shows the format of the segment table.

The 12-bit segment identifier is concatenated with the input valid address bits 4 through 31 to generate a 40-bit virtual address. Of the effective addresses, the lower 11 bits for 2K pages, or the 12 bits for 4K pages,
Used as a byte address for the selected real page. These bits are not changed by the conversion process. The remaining 29 (28) bits of the virtual address are then provided to the translation hardware. Figure 3 shows
6 illustrates virtual address generation performed using a segment identifier and a storage device effective address.

The address translation system shown herein utilizes a translation lookaside buffer (TLB) that contains the translation of the last used virtual address (32 in this example). Hardware is used to update the TLB entry from the main memory page table when a new virtual address is provided to the TLB for translation. A simplified data flow of the conversion hardware is shown in FIG. 4 and the format of each TLB is shown in FIG.

The system consists of two with 16 entries per LTB
Take the TLB (2-way set associative with 16 congruence classes). The lower 4 bits of the virtual page index are used to address both TLBs at the same time. The address tag entry of each TLB is compared with the segment identifier concatenated with the remaining bits of the virtual page index (25 bits for 2K pages, 24 bits for 4K pages). If any of the two comparisons are equal and the TLB entry is valid (indicated by a valid bit) then it contains the translation information for the given virtual address of the associated TLB.

Real page number field (R in the selected TLB entry
PN) contains the number of the real page in main memory. It maps to a given virtual address of the real page number. If this is not a special segment, before access is granted,
The key bit from the TLB entry and the key bit from the segment register are used to check for a memory device protection violation. If this is a special segment, as indicated by the special bit in the segment register, lock bit processing is performed before access is granted. The storage mechanism, as well as the special segment processing, will be described later. If access is granted, main memory is accessed to update the reference and change bits associated with the page. The set of reference and change bits are also described below.

If the comparison of the two TLBs does not yield a match, the address translation logic attempts to reload the absent TLB entry from the page table entry in main memory. The main memory page table resides in real memory and is logically composed of two parts: the hash anchor table (HAT) and the reverse page table (IPT). The HAT can map any virtual address to any real page by hatsing.

The inverse page table (IPT) specifies the virtual address (if any) associated with each real page frame. IPT
Is organized as an array of entries indexed by real page number, where each entry is a segment associated with it
Includes ID and virtual page number.

Since the IPT is indexed by real page number, it is very easy to determine the virtual address for a given real address. In order to efficiently determine the real address for a given virtual address, it is necessary to map the virtual address to an anchor point by hashing and chain the entries to resolve the hash collision. This will be easily understood by those skilled in the art.

The hash anchor table (HAT) is logically separated from the IPT (although it is physically built into the IPT for reasons of hardware efficiency). As shown in Figure 6, the hash function translates a virtual address into the index of one entry in the HAT, and that entry is the same.
Specifies the first entry in the chain of IPT entries (real pages) that have a HAT index. When searching a chain of IPT entries for a virtual address match, the IPT index (hence the real address) for the desired virtual address is obtained, or no match is found (the page is not mapped). The search ends. In this embodiment, one HAT and IPT for each page of real memory
The entry exists.

The translation of a virtual address to a real address is accomplished by first exclusively ORing the selected lower bits of the effective address and the bits from the segment identifier. This "hashed" address is used to index the HAT. The selected HAT entry is a pointer to the start of the list of IPT entries to be searched for a given virtual address. IPT to be searched
The entries in the list of etries are linked by a pointer in each entry that specifies the next IPT entry to search. The flag bit in the IPT entry is used to indicate the end of the search chain. Note that hashing generally produces the same HAT address for several different effective addresses, so the IPT chain to be searched contains some virtual address entries.

HAT and IPT for hardware efficiency reasons
Can be addressed by one indexing structure 1
Combined in one structure. Combined HAT and I
There is one entry in the PT for each page of real storage. For example, 1 Mbytes of real storage made up of 2 Kbytes pages requires 512 entries, and 512 Kbytes of real storage made up of 4 Kbytes pages requires 128 entries. The format of the combined HAT and IPT entries is shown in FIG. The HAT / IPT has 16 bytes for each entry, starting at an address location that is a multiple of the table size.

The first word of each entry contains the address tag. The address tag is created by connecting the segment identifier and the virtual page index. For 2K pages, the address tag is
Note that it is 29 bits, 28 bits for a 4K page. If a 4K page size was used, a 28-bit address tag would be stored in bits 3-30. Bit 2 is reserved. The first word further includes a 2-bit key. The 2-bit key is used for storage device protection, which will be described later.

The second word contains a HAT pointer, an IPT pointer, and a valid bit for each pointer. The use of pointers will be described later.

The third word contains the TID for write protection, lock bits, and special segments. The use of these fields will also be explained later.

The fourth word is not used for TLB reloads and is reserved for future use.

The HAT / IPT base address is a field in the translation control register (discussed below) that is used to calculate the starting address of the main memory page table. HAT / IPT
The value contained in the base address is multiplied by the amount shown in Table 1 depending on the size of the storage device and the page, thereby obtaining the starting address of the main storage page table. Table 1 also shows the HAT / IPT size for each of the storage size and page size.

HAT Address Generation As described above, the HAT index is calculated by exclusive ORing the bit selected from the segment identifier and the bit from the effective address. The number of bits used is chosen so that the result index selects one of the n entries in the HAT / IPT. This hatching operation is shown in FIG. The bits used to generate the HAT index are listed in Table 2. The storage address of the selected HAT entry is calculated as HAT / IPT base address + HAT index || 0100.

The selected HAT index is accessed and the free bits are checked to determine if the IPT search chain is free. If the free bit is 1, then there is no page mapped to the given virtual address and a "page fault" is reported, as will be explained later. If the free bit is 0, there is an entry in the IPT search chain and the entry in the IPT is searched. The HAT pointer field of the selected HAT entry is then used as a pointer to the starting point of the IPT search chain.

The previously accessed HAT pointer is used as the starting index into the IPT. The storage address of the first IPT entry is calculated as HAT / IPT base address + HAT pointer || 0000.

An address is made to the first entry in the IPT and its address tag is compared to a given virtual address. If they match, the real page assigned to the virtual address has been found and the absent TLB entry can be reloaded. Reloading of TLB entries will be explained later. If they do not match, the IPT pointer is accessed to continue the IPT search. The IPT pointer is calculated as HAT / IPT base address + HAT pointer || 0100. The IPT pointer is then accessed and the final bit is examined to determine if there are additional entries in the IPT search chain. If the final bit is 0, there are additional entries and the search process continues. If the final bit is 1, then there are no additional IPT entries to be searched and "page fault" is reported.

If there are additional IPT entries to be searched, the address of the next IPT entry to search is calculated as HAT / IPT base address + HAT pointer || 0000. This address is used to access the next entry in the IPT and compare the address tag contained in the selected entry with the given virtual address. If they match, the real page assigned to the virtual address is found and the absent TLB entry can be reloaded. If they do not match, the pointer to the next entry to be searched is accessed to continue the search process.
The address of the pointer to the next entry is calculated as HAT / IPT base address + IPT pointer || 0100. This word is then accessed and the final bit is examined to determine if there are additional entries in the IPT search chain. If the final bit is 1, then there are no additional IPT entries to be searched and "page fault" is reported. If the final bit is 0, there are additional entries and the search process continues. The current IPT pointer is used until the address tag of the IPT entry matches the given virtual address, or no match is found and the final bit indicates that there are no more entries in the search chain. The subsequent entry access is performed by the above-described processing.

The following is a summary of the steps required to translate a virtual address into an IPT entry index (and hence the corresponding real address).

(1) Select the lower 13 bits of the virtual page number. This is bits 7 to 19 of the effective address if a 4 Kbyte page is used and 8 to 20 if a 2 Kbyte page is used.

(2) Select the contents of 12 bits of the segment register specified by the valid address bits 0 to 3. A "0" bit is connected to the left end to form a 13-bit field.

(3) Exclusively OR the two 13-bit fields from steps (1) and (2) to form a 13-bit hash anchor table entry number.

(4) Shift the value of step (3) to the left by 4 bits. This physically forms the byte offset of the starting point of the IPT entry containing the desired HAT entry.

(5) Calculate the address of the HAT / IPT entry. This is done by adding the result of step (4) and the starting address of the IPT. This "addition" may be replaced by OR or concatenation if the IPT is constrained to start at a power of 2 byte boundary.

(6) Check the free IPT chain. HAT / IPT entry “E”
Inspect the (“empty”) bit.

If E = 1, the IPT chain is free (HAT pointer is invalid): the search is unsuccessful; the virtual page is unmapped.

(7) Select the HAT pointer from the addressed HAT / IPT entry if the IPT chain is not empty. This 13
The value of the bit is the index of the first IPT entry in the chain of entries with the same hash result [step (3)].

(8) Shift the IPT index value to the left by 4 bits. This is the IPT that should be checked for a virtual address match
The starting point of the entry forms a byte offset.

(9) Calculate the IPT entry address. This is done by adding the result of step (8) and the starting address of the IPT. This "addition" may be replaced by OR or concatenation if the IPT is constrained to start at a power of 2 byte boundary.

(10) Comparison of virtual addresses. A concatenation of the segment ID to the virtual page number (28 bits or 29 bits) from the IPT entry and a concatenation of the contents of the segment register specified by the effective address [Step (2)] to the virtual page number of the effective address. And, compare.

(11) If they match, the search ends successfully. This entry corresponds to the desired virtual address. Its index number is equal to the requested real page number.

(12) If they do not match, check the end of the chain. Check the "L"("last") bit of the IPT entry. If L = 1, then it is the last IPT entry in this chain. The search was unsuccessful and the virtual page is unmapped.

(13) If not at the end of the chain, select the IPT pointer field from the IPT entry. This 13-bit value is the index of the next IPT entry to be examined.

(14) Go to step (8).

TLB Reload When an IPT entry with an address tag field that matches a given virtual address is found, the absent TLB entry is reloaded. Reload was never used for the longest congruence class of virtual addresses
It consists of selecting a TLB entry and loading the selected entry with a given virtual address tag field, the corresponding real page number and key bit. If this is a special segment, as indicated by the special bit in the segment register,
The write bit, TID, and lock bit are also reloaded.

Not used for the longest time in each congruence class
Hardware is used to determine the TLB entry. Since the lower bits of the virtual address determine the congruence class, all that remains is to determine which TLB should have replaced the selected entry. One of the two TLBs is then selected based on which TLB had the longest unreferenced entry in the given congruence class.

Once the longest unused TLB entry for a given congluen class has been determined, the selected TLB entry can be reloaded. Address tag fields and keybits are reloaded from the IPT entries contained in main memory. The address of this entry was precomputed during the IPT discovery process. Since the IPT index calculated during the search process is equal to the real page number, this value is used to reload the TLB real page number field. If this is a special segment, the TID and lock bit are also reloaded, as indicated by the special bit in the segment register. The TID and lock bit are reloaded by accessing the third word of the selected IPT entry.

Storage Access Control This address translation mechanism provides two access control mechanisms. The first mechanism is for non-special segments and provides read / write protection for each page of real storage. The second mechanism is dedicated to special segments and is used to support persistent data types. These access control mechanisms apply only to translated access. If a violation is detected by either mechanism, storage access is terminated,
Exceptions are reported as explained later.

Storage protection processing Storage protection processing applies only to non-special segments.
Once the correspondence between the virtual address and the real address is taken by TLB, in order to guarantee proper access authority,
The requested access is verified. This feature marks each page as no access, read only, or read / write.

The access control is 1 in the selected segment register
It has something to do with the protect key of the bit, the two bit keys in the TLB entry, and whether the access is load or store operation.
Access is controlled as shown in Table 3.

If access is not granted, the conversion ends and a protection exception is reported to the CPU.

Lock Bit Handling Lock bit handling applies only to the special segment indicated by the special bit in the selected segment register. Special segments are used to support persistent data. Through lock-bit processing, the operating system automatically monitors changes to persistent variables, journals changes, generates shadow pages, and other methods for ensuring database consistency. It is possible to perform processing. Lockbit also subdivides the unit of protection from page size (2K bytes or 4K bytes) by storage protection functions to lines of 128 bytes or 256 bytes. A 128-byte protection unit is realized for a 2K page, and a 256-byte protection unit is realized for a 4K page. For 2K pages, the lock bit of each line is selected by valid address bits [21:24], and for 4K page, the lock bit of individual lines is selected by valid address bits [20:23]. To be done.

The access control is a one-bit write key in the selected TLB entry, the lock bit value of the selected line, TI
It is related to the D comparison and whether the access is a load operation or a memory operation. Access is controlled as shown in Table 4.

A data storage exception is used to report a lock bit violation. This violation does not necessarily represent an error,
It may simply indicate that the newly modified line should be processed by the operating system.

Reference and change bits are provided for each page of real memory. These bits are located in an array external to the address translation mechanism and are updated on demand for each memory access. The reference bit is set to 1 when the corresponding real page is accessed for reading or writing. The modification bit is set when the corresponding page is written.

Reference and modify bits can be accessed by I / O read instructions (IOR) and I / O write instructions (IOW) from the associated CPU. The reference and modification bits for each page of the real record are stored in the I / O base address register as X
Starts at the I / O address specified by adding '1000'. The reference and modify bit I / O address for a given page is given by:

I / O address = address specified by I / O base address register + X'1001 '+ page number Each I / O address includes a reference bit and a modification bit for one page of real memory. The format of the reference and modified bits is shown in FIG.

The data transferred by access to the reference and change bits is defined as follows.

Bit 0:29 Zero.

Bit 30 See Bit. It is set to 1 when the corresponding real page is accessed for reading or writing.

Bit 31 Change bit. Set to 1 when the corresponding real page is accessed for writing.

The reference and modify bits are not initialized by the hardware. They are initialized and cleared by the IOW instruction of system software. The reference and modify bits can be set by running a program that sets or clears them, so a write that clears or sets the reference and modify bits will not necessarily be written. You don't have to read the same data as you did.

Control Register Storage Configuration, Page Table Address, and I / O
There are several control registers used to determine the base address. These registers are I / O read (IO
R) instruction and I / O write (IOW) instruction. Their construction and format are shown in FIGS. 9 to 18. These registers are only accessible after entering the watch program state.

The I / O base address register is the 64K of the I / O address.
Specifies whether the block is assigned to the conversion system. The I / O base address is equal to the value contained in the I / O base address register multiplied by 65536 (X'10000 '). The format of the I / O base address register is shown in FIG.

The I / O base address register is defined as follows.

Bit 0:23 Reserved.

Bit 24:31 I / O base address. This 8-bit value defines which 64-Kbyte block of the I / O address is assigned to the translation system. That is, these 8 bits are the highest 8 bits of the I / O address recognized by the conversion system. The "RAM specification register" defines the RAM size, RAM start address, refresh sheet, and whether parity check or error correction code (ECC) is used. The ECC and parity check techniques do not form part of the present invention and their content is well known and will not be described further. The format of the RAM specification register is shown in Fig. 10.

The RAM specification register is defined as follows.

Bit 0:10 Reserved.

Bit 10:18 Refresh refresh. The quantity of 9 bits determines the refresh cycle rate. The refresh cycle rate is equal to the value contained in bits [10:18] multiplied by the frequency of the CPU clock. A refresh rate of zero intensifies the refresh rate. The value of the refresh rate can be calculated by dividing the desired memory refresh rate by the frequency of the CPU clock. For example, in a system with dynamic memory that requires 128 rows of refresh every 2 milliseconds, the refresh interval per row is 128/2 milliseconds or 15.6 microseconds. If the CPU clock is 200 nanoseconds, the desired refresh rate value is 15.6 microseconds / 200 nanoseconds, or 78 (X'04E '). This requires loading X'04E 'into the refresh rate.

The refresh rate is X'0 as part of the POR sequence.
Initially set to 1A '.

Bit 20:27 RAM start address. The 8 bit field defines the starting address of the RAM for translated and untranslated accesses. In the case of translated access, RAM is selected if the translated address is within the range specified by the RAM start address and RAM size. For untranslated accesses, the RAM start address along with the RAM size is used to determine if the address is within the address range specified for this storage controller. The start address of the RAM is defined as a binary multiple of the RAM size, and is calculated by multiplying the bit shown in Table 5 by the value specified by the RAM size.

For example, if a storage size of 256K is specified, 64
One of the 256 Kbyte boundaries is specified as a RAM start address by bit [20:25]. If Bit [20:25] is 011
If it is 101, the RAM start address is X'00740000 '. 1
If the Mbyte RAM size is designated, one of 16 1Mbyte boundaries is designated as a RAM start address by bit [20:23]. If Bit [20:23] is 1001, RAM
The start address is X'00900000 '.

Bit 28:31 RAM size. This 4 bit field defines the size of the RAM connected to the conversion system. The RAM size can be selected from 64 Kbytes to 16 Mbytes as shown in Table 6 below.

Table 6 Bits 28:31 RAM size 0000 No RAM 0001 to 0111 64K 1000 128K 1001 256K 1010 512K 1011 1M 1100 2M 1101 4M 1110 8M 1111 16M ROS designation register The ROS designation register is based on the ROS start address, ROS size, and ROS. Whether or not the parity is given,
Stipulate that. ROS is accessible in both translated and untranslated modes. Figure 11 shows the format of the ROS specification register.

The ROS specification register is defined as follows.

Bit 0:19 Reserved.

Bit 20:27 ROS start address. This 8-bit field defines the starting address of the ROS for both translated and untranslated accesses. For translated access, ROS if the translated address is within the range specified by the ROS start address and ROS size.
Is selected. For untranslated accesses, the ROS start address along with the ROS size is used to determine if the address falls within the address range specified for this storage controller. The start address of ROS is defined as a binary multiple of the ROS size.
It is calculated by multiplying by the value specified by the size.

For example, if a ROS size of 64K is specified, one of 256 64K byte boundaries is specified as a ROS start address by bit [20:27]. If bits [20:27] are 110010, the ROS start address is X'00C80000 '.

Bit 28:31 ROS size. This 4 bit field defines the size of the ROS connected to the conversion system. The ROS size can be selected from 64 Kbytes to 64 Mbytes as shown in Table 8 below. Bits [28:31] if ROS is not used
Is set to zero.

Table 8 Bits 28:31 ROS Size 0000 ROS None 0001 to 0111 64K 1000 128K 1001 256K 1010 512K 1011 1M 1100 2M 1101 4M 1110 8M 1111 16M Conversion Control Register The Conversion Control Register (TCR) is a TLB reload by hardware. Whether an interrupt is generated on success,
Whether parity is used for the reference and change arrays, the size of each page (2 Kbytes or 4 Kbytes),
And the starting address of the main memory page table (a combination of HAT and IPT). The format of the conversion control register is shown in FIG.

The conversion control register is defined as follows.

Bit 0:20 Reserved.

Bit 21 TLB Interrupt enable when reload is successful. This bit is used to report successful TLB reload by hardware. If it is set to 1, the TLB reload bit (bit 22) of the SER is set to 1 due to the successful reloading of the TLB by the hardware. If this bit is set to zero, no successful hardware reload of the TLB entry is reported. This function can be used for software TLB performance evaluation.

Bit 22 Reference and Change Array Parity. This bit is used to indicate whether parity is used for external reference and modification arrays. If this bit is set to 1,
Use parity for reference and change arrays. If this bit is set to zero, no parity is used for the reference and change arrays.

Bit 23 page size. The value 0 is used for 2 Kbyte pages and the value 1 is used for 4 Kbyte pages.

Bit 24:31 HAT / IPT base address. The 8-bit field is used to specify the start address of the HAT / IPT entry in main memory. The start address of the HAT / IPT entry is determined by multiplying the value contained in this field by a constant determined by the size of real memory and the page size. For page sizes of 2K bytes, the bit [24: 3
1] specifies the base address, and in the case of a page size of 4 Kbytes, bits [25:31] specify the base address. The constants for each of the storage size and page size are listed in Table 1.

The Storage Exception Register (SER) is used to report errors in the conversion process and system errors that occur in storage access.

A separate bit is assigned for each error condition detected by the conversion system. If multiple errors occur, each error is reported by setting the appropriate bit. Bits set by a previous error will not be reset by a subsequent error.

SER is initialized to zero by the POR sequence. Once an exception is reported, system software clears SER after the exception is handled. The format of the storage exception register is shown in FIG.

The storage exception register is defined as follows.

Bit 0:21 Reserved.

Bit 22 TLB reload successful. This bit is set to 1 if the reload was successful while interrupts due to TLB reload success were enabled.

Bit 23 Reference and change array parity error. This bit is set to 1 if a parity error is detected in the reference and change array.

Bit 24 ROS writing trial. This bit is set to 1 when an attempt is made to write to an address contained in the ROS address space.

Bit 25 IPT specification error. This bit is set to 1 if an infinite loop is detected in the IPT search chain. The infinite loop is incorrectly specified with the value of the IPT pointer due to an error in the system software, and as a result the IPT pointer is
This occurs when the previous entry in the PT search chain is indicated.

Bit 26 External device exception. This bit is set to 1 if an exception was caused by a device on the RSC other than ROMP.

Bit 27 Multiple Exception. This bit is set to 1 if more than one exception (IPT specification error, page fault, specified, protected, or data) occurred before the exception indicator was cleared in the storage exception register.

This bit usually indicates that the system software was unable to handle the exception. However, this bit can be set even if an exception is caused by a multiple load (LM) or multiple store (STM) instruction. This is because the LM or STM instruction will attempt to store or load all the registers specified by the instruction before it is aborted by the exception.

Bit 28 pages absent. This bit is set to 1 when the translation is complete because none of the TLB entries and main memory page table entries contain translations for the virtual address.

Bit 29 specified. This bit is reset to 1 if the translation is complete because two TLB entries are found for the same virtual address.

Bit 30 protection. This bit is set to 1 when the conversion is complete because the storage protection process for the non-special segment knows that storage access is prohibited.

Bit 31 data. Transaction ID / for special segment
This bit is set to 1 when the conversion is completed because the lock bit process knows that the storage device access is prohibited.

The memory exception address register (SEAR) contains the organic memory address that caused the exception reported by the memory exception register (SER) in response to a data load and memory request from the CPU. SEAR is not loaded if the exception was caused by a ROMP instruction fetch or an external device.
The format of the memory exception address register is shown in FIG.

The storage exception address register is defined as follows.

Bit 0:31 Storage exception address. The 32-bit effective storage address that caused the exception reported by the SER. In case of multiple errors (SER bit 27 is set to 1), the address contained in SEAR is the address of the oldest exception.

The translated real address register (TRAR) contains the real storage address determined by the real address calculation operation. The real address calculation function determines whether or not the virtual address is currently mapped in the real memory, and when the virtual address is mapped, determines the corresponding real address. The real address calculation function will be described later. The format of the converted real address register is shown in FIG.

The real address translation register is defined as follows.

Bit 0 Invalid bit. This bit is set to 1 if the conversion was unsuccessful, and to 0 if the conversion was successful.

Bit 1: 7 Zero. This 7-bit field is always zero.

Bit 8:31 Real memory address. This 24-bit field contains the real memory address. This real memory address was mapped to a given virtual address if the translation was successful. This field is set to zero if the conversion fails.

The transaction identification register (TID) contains the 8-bit identifier of the task currently defined as the "owner" of the special segment. When a segment is defined as a special segment by the special bit in the selected segment register, the lock bit processing as shown in Section 6.2 is applied to the storage device access. The lock bit process uses the value contained in the TID and compares it with the TID entry in the TLB to determine if storage access is allowed. The format of the transaction identification register is shown in FIG.

The transaction identification register is defined as follows.

Bit 0:23 Reserved.

Bit 24:31 The transaction identifier. This 8-bit value specifies the owner of the special segment.

The 16 segment registers include a segment identifier, a special bit, and a key bit. A 12-bit segment identifier specifies one of 4096 256 Mbyte virtual memory segments. The special bit indicates that it is a special segment and lock bit processing is applied. The key bit indicates the level of access authority associated with the task currently being performed for storage access within a given segment. The format of each segment register is shown in FIG.

The contents of each segment register are defined as follows.

Bit 0:17 Reserved.

Bit 18:29 The segment identifier. This 12-bit value is 4096 256M
Specifies one of the byte virtual storage segments.

Bit 30 Special bit. For special segments, this bit is set to one; for non-special segments, this bit is set to zero.

Bit 31 Key bit. This bit determines the level of access authority of the currently executing task for access within a given segment. The use of this bit for storage access control is shown in Section 6.2.

In the disclosed embodiment, each of the two TLBs has 16 entries. These entries provide the translation and control information needed to translate a virtual address to a real address. In addition, each TLB entry also contains additional information used for storage access control. Since the TLB contents are automatically updated by the hardware from the main memory page table, if a TLB entry write is followed by a read, it is not necessary to read the same data that was written. In addition, changes in TLB entries may cause unpredictable results, since changes in TLB entries will result in a lack of correspondence between real and virtual addresses. Accessing the contents of the TLB should only be done for diagnostic purposes and should be considered in non-translation mode. In non-conversion mode, prohibiting all other conversion access
Writing to a TLB entry would be followed by a read, reading the same data that was written.

Each TLB entry is logically a 66-bit (excluding reserved bit) variable, including a 25-bit address tag, a 13-bit real page number, a valid bit, a 2-bit key, a write bit, and an 8-bit transaction. It consists of an ID and 16 lock bits. Each TLB entry is divided into three individually addressable fields.
Each type of TLB field is described below.

The "TLB address tag" field is for 2K pages,
Segment identifier || Includes the top 25 bits of the page index, and in the case of 4K pages, includes the top 24 bits. each
TLB entry address tag field format 18.1
Shown in the figure.

The content of each TLB address tag field is defined as follows.

Bit 0: 2 Reserved.

Bit 3:27 Address tag. This field contains the top 25 bits of the segment identifier || virtual page index for 2K pages and its top 24 bits for 4K pages.
For 4K pages, the address tag is included in bits [3:26].

Bit 28:31 Reserved.

The "TLB real page number, valid bit (V), and key bit (key)" field contains the real page number assigned to the virtual address contained in the address tag field of the TLB entry. This field also contains a valid bit indicating that the given TLB entry contains valid information, and a key bit for the access rights required for the given page. The format of this field for each TLB entry is shown in Figure 18.2.

The real page number, valid, and key field contents are defined as follows.

Bit 0:15 Reserved.

Bit 16:28 The real page number. This 13-bit field specifies one of 8192 real pages. If you use less than 8192 pages, only the low-order bits needed to address those pages are used.

Bit 29 Effective bit. This bit is 1 if the selected TLB entry contains valid information. This bit is 0 if the TLB entry contains invalid information.

Bit 30:31 Key bit. These two bit fields define the access rights for each page. The use of key bits is shown in Section 6.1.

The "TLB write bit, transaction ID, and lock bit" field is added to the virtual address contained in the write tag, transaction ID, and address tag field of the TLB entry when the TLB entry is for a special segment. Contains the assigned lock bit. The format of this field for each TLB entry is shown in Figure 18.3.

The contents of the TLB write bit, transaction ID, and lock bit field are defined as follows.

Bit 0: 6 Reserved.

Bit 7 Write bit. This bit defines the access rights associated with each page in the case of special segments. The use of this bit in lock bit processing is described in Section 6.2.

Bit 8:14 Transaction identifier. This 8-bit field defines the task that currently owns the selected page in the special segment. The use of these bits in the lock bit process has been described previously.

Bit 15:31 Rock bit. This 16-bit field defines the access rights for each "line" in a 2K or 4K page in the case of a special segment. One line is 128 bytes for 2K pages and 256 bytes for 4K pages. The use of these bits in lock bit processing is described in Section 6.2.

This conversion mechanism supports frequently required conversion functions by hardware. This hardware selectively disables TLB entries and allows IBM System / 370
A "real address load" function similar to that in a family computer can be performed.

When changing the virtual-real address mapping, it is necessary to synchronize the contents of the TLB and the contents of the page table in the main memory with the system software.
Both TLB and page frame table entries must be removed (invalidated) so that obsolete mapping information is not used in subsequent conversions.

This system uses the contents of the page table in main memory
It provides three functions that support synchronization with TLB entries. These features can be used to invalidate the entire contents of the TLB or only selected TLB entries.
I / O write instruction (IOW) to a specific I / O address in the 64K byte block of the I / O address recognized by the system
Calls these functions. Address assignments for each of these functions are provided to the system as needed.

All TLB entries are invalidated by the "Invalidate all TLB" function. This function forces the page table in main memory to update the contents of the TLB in preparation for subsequent conversions.

An I / O write to the address associated with this function invalidates all TLB entries. The data transferred by the I / O write command is not used.

The "Invalidate TLB entry in designated segment" function invalidates all TLB entries having the designated segment identifier. Subsequent conversions using this segment identifier will update the contents of the TLB from the page table in main memory.

An I / O write to the address associated with this function invalidates the TLB entry with the specified segment identifier. I / O
The bits [0: 3] of the data transferred by the write command are used to select the segment identifier. All TLB entries containing this segment identifier are invalidated. The contents of the TLB are updated from the page table in main memory by a subsequent translation with the effective address in the invalidated segment.

The "Invalidate TLB entry for specified effective address" function invalidates the TLB entry having the specified effective address.

The contents of the TLB are updated from the page table in seed storage by subsequent translation with the effective address within the page containing the specified effective address.

An I / O write to the address associated with this function invalidates the TLB entry with the specified effective address. Bits [0:31] of the data transferred by the I / O write command are used as the effective address. A normal translation process is applied using the contents of the segment register included in this address translation mechanism.

The "real address calculation" function is used by system software to determine if a given virtual address is currently mapped into real memory and, if so, which real address is assigned to that virtual address. Determine what is being done.

If a virtual address is not mapped, its use results in a page fault; this information is important for system routines running with interrupts disabled. I /
Most of the O operations are performed using real addresses, so the result of the virtual to real address translation is requested by the system I / O routines.

The real address calculation function uses the I /
It is called by O inclusion. Bits [0:31] of the data transferred by the instruction including I / O are used as the effective address. This effective address is used for the normal exchange process, but the translation result is loaded into the translated address register (FIG. 15) (TRAR) and not used for storage access. TRAR contains a bit indicating whether the conversion was successful and, if successful, the corresponding real memory address. Normal storage protection and lockbit processing is performed upon successful conversion. The result of the real address calculator is obtained by the TRAR I / O read.

A 64-Kbyte block of I / O addresses is assigned to the translation system. The 64-Kbyte block starts at the I / O address specified by the I / O base address register. The I / O base address is defined to be on a 64K boundary. The I / O address assignments listed in Table 9 are the displacements within the specified 64K byte block. The absolute I / O address is equal to the I / O base address plus this displacement.

Conclusion From the above description of the preferred embodiment of the invention, both
Various changes in system hardware and software format and details may be made without departing from the spirit and scope of the invention to provide lock bits for the TLB and page frame table and utilize conventional segmentation schemes. It will be obvious to the king that it can be done easily. Obviously, these changes include storage size, register size and control field definitions, address size,
It includes, but is not limited to, changes in page frame table access methods and configurations, and hash address methods.

E. Effect of the Invention As described above, according to the present invention, the cooperative operation of the special bit provided in each segment register and the lock bit for each line provided in the conversion index buffer mechanism and the page frame table is performed. This enables more detailed memory protection. This is especially useful for controlling journaling within the system.

[Brief description of drawings]

FIG. 1 is a functional block diagram of the main part of the address translation and access control system of the present invention. FIG. 2 is a diagram showing the format of the segment register used in this address translation mechanism. FIG. 3 is a combination of a functional block diagram and a data flow diagram showing effective address to virtual address translation. FIG. 4 is a combination of a block diagram and a data flow diagram showing the whole address translation mechanism from an effective address to a real address. FIG. 5 is a diagram showing the structure and contents of a translation index buffer mechanism used in the entire address translation mechanism of the present invention. Figure 6 is a conceptual diagram of a combined hash anchor table / reverse page table and a data flow diagram showing the operation of such tables when no TLB entry is found for a given virtual address. is there. FIG. 7 is a diagram schematically showing the structure and contents of the actual hash anchor table / reverse page table stored in the storage device. FIG. 8 shows the format of the reference and change bits used with each I / O address. FIG. 9 is a diagram showing the configuration of the I / O base address register. FIG. 10 is a diagram showing the format of the RAM designation register. FIG. 11 is a diagram showing the format of the ROS designation register. FIG. 12 is a diagram showing the format of the conversion control register. FIG. 13 is a diagram showing the format of the storage exception register. FIG. 14 is a diagram showing the format of the storage exception address register. FIG. 15 is a diagram showing the format of the converted real address register. FIG. 16 is a diagram showing the format of the transaction identification register. FIG. 17 is a diagram showing the contents of one of 16 segment registers. FIGS. 18.1, 18.2, and 18.3 diagrammatically show the three field types utilized for each page reference in each of the translation lookaside buffers. Note that in the disclosed embodiment, there are two independent translation index buffers, and there are 16 real page references stored in each of the buffers at one time.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Margin, Mark F, New York, USA 10549, Mount Kisco, Cliffside Lane Earl Arr. 4 (72) Inventor Radein, George, New York 10968, USA Pearmont, Franklin No. 26 (56) Reference JP-A-53-34429 (JP, A) JP-A-56-153576 (JP, A) JP-A-54-105930 (JP, A)

Claims (1)

[Claims] 1. A hierarchical storage system for converting a virtual address supplied by a central processing unit into a real address using a conversion index buffer and a page frame table, wherein bits of the virtual address are larger than a segment identification field. A plurality of segment registers for storing a large number of segment identifiers and special bits associated with the segment identifiers are provided, and a lock bit is provided for each line forming a page in both the conversion index viewing mechanism and the page frame table, The segment identification field of the virtual address supplied by the central processing unit is used to access the plurality of segment registers, and the segment identifier and the virtual address stored in the addressed segment register are stored. A page offset field and a byte offset field are concatenated to generate a second virtual address having a larger number of bits than the virtual address, the second virtual address is converted to a real address, and the special bit has a predetermined value. When set to a value, the address translation method is characterized in that locking or journaling is performed for each line of the real page according to the lock bit.