JPH0670868B2 - Digital data recorder - Google Patents

Description

The present invention relates to a digital data recording device applied to a device for storing code data on an optical disk, for example.

[Background technology and its problems]

A storage device for writing code data on a recording medium such as an optical disk, a magnetic disk, or a magnetic tape is used.
Code data means digital data in which no error is allowed, and can be modified such as image data and audio data, and is therefore called code data in order to distinguish it from data in which some error is allowed. When the code data is stored in the recording medium, it is necessary to judge whether or not it was correctly written by using some method at the time of writing. If not correctly written, an alternative data area is secured and rewriting is performed there.

By the way, since the optical disk has a high error rate, strong error correction is performed on the read data (read data). Therefore, if the written data (write data) is immediately reproduced and the write data is checked in the state after the error correction, even if the write data is correct, when this write data is read After all, it is unknown whether the data will be read correctly. That is, the read data may become error data due to the addition of an error not only at the time of writing but also at the time of reading.

[Object of the Invention]

Therefore, an object of the present invention is to provide a digital data recording device which determines whether or not write data is correctly recorded with respect to a margin of error correction, and eliminates a possibility of erroneous read data. To do.

[Outline of Invention]

According to the present invention, when writing digital data to a recording medium, the written data is read out after writing and error correction is performed, and the error state of the written data is detected by the decoding state at the time of error correction. The digital data recording device is adapted to judge whether or not to write again from an error state.

〔Example〕

In FIG. 1, reference numeral 1 denotes a disk, and the disk 1 is rotated by a spindle motor 2 at a constant linear velocity. The disk 1 is formed by coating a surface of a substrate made of glass or synthetic resin with a metal layer such as bismuth and the surface of which is plated. Disk 1 is
The recording laser beam from the optical head 3 causes the metal layer to undergo a phase transition to form a pit. On the other hand, the pit is read by the reading laser light from the optical head 3.
The recording laser light is modulated by the write data.

A large number of spiral tracks are formed on the disk 1, and each of the tracks is divided into a plurality of sectors. The address part for each sector is stored in the disk 1 in advance.
Is recorded as the presence or absence of a pit, and a digital signal can be recorded in the target sector or reproduced from the target sector according to the address reproduced from the address section.

The optical head 3 has an objective lens, a beam splitter, an optical modulator, a light receiving element, etc., and laser light is applied to the optical head 3 from a laser generation circuit 4 including a semiconductor laser. Write data is supplied to the laser generation circuit 4 via the drive interface 5, and read data read by the optical head 3 is taken out via the drive interface 5. At the time of writing (recording), a power control signal is supplied from the drive interface 5 to the laser generating circuit 4 in order to increase the power of the laser light more than at the time of reading (reproducing).

A servo circuit 6 is provided to rotate the disk 1 at a constant linear velocity. Further, the optical head 3 can be sled in the radial direction of the disk 1 by means of a thread feeding section 7 composed of a linear motor. The focusing and tracking of the optical head 3 are made good by the focusing and tracking servo 8. The reproduction output of the optical head 3 is supplied to the system controller 9 for detecting focusing error and tracking error.
A command is supplied to the system controller 9 via the drive interface 5, and a control signal for the servo circuit 6, the thread feeding unit 7, the focus and the tracking servo 8 is generated from the system controller 9.

The drive interface 5 has the configuration shown in FIG. In FIG. 2, reference numeral 21 denotes a block coding encoder for converting 8 bits into a pattern of 10 bits, that is, a pattern capable of reducing the DC component. The output of the encoder 21 is supplied to the parallel / serial converter 22 to write data. Is formed. The read data from the optical head 3 is supplied to the serial / parallel converter 24 and the PLL 25 via the limiter 23. Serial-parallel converter 2
The output of 4 is supplied to the decoder 26 and the sync / mark detection circuit 27 of the block coding.

PLL25 extracts the bit clock from the read data,
This bit clock is supplied to the decoder 26 and the sync / mark detection circuit 27. The sync / mark detection circuit 27 detects a sync signal and a mark (address mark or data mark) in the read data, generates a timing signal synchronized with the read data, and decodes this timing signal.
Supply to 26. Further, the drive controller 28 generates a command for the drive system controller 9 and a power control signal for the laser generation circuit 4.

The formation of write data, the processing of read data, and the formation of data in the drive controller 28 are carried out by the error correction signal processor 11, the buffer memory 12, and the system controller 13. In addition, the host processor 15 and the optical disk recording / reproducing device are connected via the interface 14.

As will be described later, the error correction signal processor 11 performs error correction coding processing at the time of recording, converts this error correction coded recording data into write data of a predetermined format, and at the time of reproduction, read data. Error correction processing.

A format according to an embodiment of the present invention will be described with reference to FIGS. 3A and 4
As shown in FIG. A, one track is divided into 20 sectors (0 to 19). Data is written in and read from this sector unit, and data is transferred between the disk drive unit and the host processor 15 in sector units. Figures 3B and 4B for each of the sectors
As shown in, the address part and the data part are included.

An address part is recorded in advance on the disk by the manufacturer. As shown in FIG. 3C, the address portion is formed by sequentially recording the same address 0, address 1 and address 2. A 16-byte sync signal is located at the beginning of the address part. This sync signal has a bit pattern of (AA ... A) in hexadecimal notation. FIG. 3D shows
The number of bytes and the bit pattern of the first part of the address part are shown. After this sync signal, an address 0 consisting of a 2-byte address mark, a 2-byte track number, a 1-byte sector number and a 2-byte CRC code is located. One byte of this data is converted into 10 bits by encoding 8 → 10 conversion and recorded on the disk.

The sync signal is a pulse signal having a repetition frequency equal to the maximum frequency generated by the 8 → 10 conversion, and is used as an ampoule signal for bit synchronization. The address mark has a peculiar bit pattern (CC3CC bit pattern in hexadecimal notation) that does not occur in the data recorded in the data section and that bit synchronization is not easily lost. This address mark is used for word synchronization. Track number and sector number are
A CRC code (error detection code using a cyclic code) is added to the addresses of the track and the sector to detect errors in both. Data ID0 for identifying address 0 is inserted in the sector number.

A 3-byte sync signal is interposed between the address 0 and the address 1 and between the address 1 and the address 2. This sync signal is a pulse signal having the same frequency as the sync signal at the beginning of the address part, and prevents the bit synchronization from being lost. Recording the same address in the address section three times is a countermeasure against an error. That is, among the reproduced addresses, as a result of the error detection of the CRC code, the address which has no error is validated. However, when the address is recorded in triple, since the sync signal is inserted at the boundary between the two addresses, the bit synchronization is facilitated, and the burst error generated at the time of disk reproduction causes the two addresses to be recorded together. An error is prevented. In this embodiment, the length of the burst error that occurs during disk playback is 3 bytes (30 bytes on the disk).
The length of the sync signal inserted between two addresses is set to 3 bytes because the bit signal is almost not exceeded. By doing so, even if a burst error occurs at the boundary between two addresses, it is possible to prevent only one address and an error in the sync signal and prevent both of these two addresses from becoming an error. Further, the reliability of word synchronization can be improved by repeatedly inserting the address mark a plurality of times. When the first address mark is detected, an accurate window is generated for the address marks from the second address mark.

Further, a gear is provided between the end of the address part, that is, the rear end of the CRC code of address 2 and the next data part. This gear is provided to compensate for the rising time from the detection of the target address to the generation of laser light of sufficient power for recording. For example, the length of the gap between the address part and the data part is 10 bytes. It should be noted that the data in these address parts is data in which no error is allowed and corresponds to the above-mentioned code data.

FIG. 4C shows the format of the data section, and FIG. 4D
Indicates the number of bytes and the bit pattern at the beginning of the data part. The data portion is composed of a sync signal and a data mark in addition to the error correction coded data. A 16-byte sync signal is inserted at the beginning of the data section. This sync signal is a pulse signal having a repetition frequency equal to the maximum frequency generated by the 8 → 10 conversion, and is for pulling in bit synchronization. A 2-byte prefix data mark is inserted after this sync signal. This front data mark has a unique bit pattern (330CF in hexadecimal notation) and is used for data synchronization. After this prefix data mark, set 0 to set
32 sets up to 31 are inserted. Each set consists of a 2-byte unique bit pattern (hexadecimal notation 33C33) data mark and 96 bytes of data.

One sector contains 1.5K bytes of data. The CIRC code is encoded with the data of one sector as a unit, and the interleaving is completed within one sector. Similar to the address mark described above, a plurality of data marks are recorded in the data portion in one sector. With this data mark, even if the word synchronization is lost in the middle, subsequent data is invalid. Is prevented. At the last position of the data part of each sector,
For example, a gear with a length of 30 bytes is provided. This gear gap between sectors is to prevent the sector length from becoming longer than the specified one due to uneven rotation of the disc, eccentricity of the disc, etc., and overlapping to the beginning of the next sector. is there.

In this embodiment described above, the data processing at the time of recording and reproducing is explained by the block diagram of FIG. 5 corresponding to the order thereof.

During recording controlled by the system controller 13,
A write command is sent from the host processor 15 and the interface controller 14 to the system controller 13 to start data transfer. The scramble / unscramble circuit 31 performs a scramble operation of diffusing data on a disk and recording the data at the time of recording. The C2 encoder / decoder 32 encodes a C2 code, for example, a (20,16) Reed-Solomon code, at the time of recording. The interleave / deinterleave circuit 33 performs an interleave operation during recording, and the interleaved data and C2 code redundant data are supplied to the C1 echo decoder / decoder 34. The C1 encoder / decoder 34 encodes a C1 code, for example, a (24,20) Reed-Solomon code, at the time of recording. Further, the output of the C1 encoder / decoder 34 is supplied to the 1-symbol delay circuit 35 for distributing the data. This 1-symbol delay circuit
The output of 35 is passed through an 8-10 modulation / demodulation circuit 36 and a formatting / defattering circuit 37, and is recorded on the optical disk 1 with the signal format shown in FIGS. 3 and 4.

At the time of reproduction, a read command is sent from the host processor 15 to the system controller 13, and the reproduced data is processed in the reverse order described above. The C1 encoder / decoder 34 performs a C1 code decoding operation to detect burst errors and correct random errors. The C2 encoder / decoder 32 corrects burst errors. Interleave / Deinterleave circuit 33
Performs a deinterleave operation for returning the data array to the original one during reproduction, whereby the burst error is dispersed.

FIG. 6 shows a specific structure of the error correction code processor 11. In FIG. 6, 40 is an error correction code processor.
It is a sequencer that controls the overall operation of 11. Error detection is data from the data bus 42 (including redundant code)
Is taken into the syndrome generation circuit 41, a syndrome is generated, and this syndrome is supplied to the sequencer 40. In this case, 1
A Galois field arithmetic circuit 43 is provided to determine a symbol error, a 2-symbol error, an error of 3 symbols or more, and to obtain an error location in the case of a 1-symbol error and a 2-symbol error. The calculated error location is stored in the error location register 44.
Stored in.

The error correction is performed in the syndrome generation circuit 41 by reading the symbol indicated by the error location register 44 from the buffer memory 12. Further, interleaving and deinterleaving are realized by controlling the address of the buffer memory 12 by the address generating circuit 45. At the time of recording, the sequencer 40 and the Galois field arithmetic circuit 43 encode the C1 code and the C2 code.

At the time of reproduction, the error detection information of the C1 code is used as a C1 pointer for more reliable error correction when the C2 code is coded. The pointer number register 46 is composed of a counter that counts pointers and a register that stores the count value. An example of a coding method using both the C1 code and the C2 code will be described.

First, the decoding of the C1 code is performed as follows. The syndrome calculated from the reproduced data is S _1, and the pointer passed to restore C ₂ is P ₁ .

(1) When the syndrome S ₁ has no error, no correction is made and (P ₁ = 0).

(2) When a single error is detected from syndrome S ₁ Correct the single error and set (P ₁ = 0).

(3) When a double error is detected from syndrome S ₁ Correct the double error and set (P ₁ = 1).

(4) When an error of triple or more is detected from the syndrome S ₁ , do not correct and set (P ₁ = 1).

That is, in C1 decoding, even double error correction is performed. At that time, there is a possibility of incorrect correction, so that (P ₁ = 1) is set and C2 decoding is checked again.

C2 decoding will be described next. The syndrome calculated at the time of C2 decoding is S ₂ , the pointer information formed by C1 decoding is P ₁ , N (P ₁ ) is the number of pointers P ₁ of 1 out of 20 symbols input to C2 decoding, L (P ₁ = S ₂ ) to the syndrome S ₂
The final flag is the number of pointers P ₁ and P ₂ that match the error location calculated from ₁ .

(1) When it is judged from the syndrome S ₂ that there is no error, it is set to (P ₂ = 0) without correction.

(2) performs a single error correction when a single error is detected from the syndrome S _2, and (P ₂ = 0).

(3) When a double error is detected from the syndrome S ₂ (I) When N (P ₁ ) ≦ 4 and L (P ₁ = S ₂ ) = 2, double error correction is performed, and (P ₂ = 0).

(II) N (P ₁ ) ≦ 3 and L (P ₁ = S ₂ ) = 1 or N
When (P ₁ ) ≦ 2 and L (P ₁ = S ₂ ) = 0, no correction is made and (P ₂ = 1).

(III) In cases other than (I) and (II), no correction is made and P ₁ is directly used as P ₂ .

(4) When three or more errors are detected from the syndrome S ₂ (I) When N (P ₁ ) ≦ 2, no correction is made and (P ₂
= 1).

(II) In other cases than the above, no correction is made and P ₁ is directly used as P ₂ .

In this embodiment, when writing data, after writing,
The written data is read and the above-mentioned error correction is performed to determine the error state. Error correction after the state code sequence number EPT was excisional the pointer P ₁ during C1 decoding
Number of composite sequences EC with one symbol error corrected at R, C2 decoding
Number of code sequences E with 2 symbol error corrected during W1 and C2 decoding
Number of code sequences that cannot be error-corrected during CW2 and C2 decoding ECER 4
It is determined using the status signals. The four status signals are stored in the decode status register 47. In this embodiment, the code sequence of the C1 code is composed of 24 symbols, and the code sequence of the C2 code is composed of 20 symbols. EPTR above
Indicates the state of error distribution, and ECW1, ECW2, and ECER indicate the number of error symbols at the time of C2 decoding. As mentioned above, C1
The code is used for burst error detection and random error correction, the C2 code is used for burst error correction, and the performance as a decoder is mostly determined by the C2 code. The number of error symbols in 1 contributes greatly to the correctability. Therefore, the number of errors when decoding the C2 code is expressed by the following equation.

ECW1 + 2 ECW2 + 3ECER (1) In the above equation, ECW2 and ECER have a coefficient added because ECW2 has a 2-symbol error and ECER has a probability of 3
Indicates a symbol error.

On the other hand, the interleaving depth in the C2 code is such that 49 symbols or 97 symbols appear alternately, and this sum corresponds to 6 code sequences of the C1 code. That is, if the number of errors in decoding the C1 code is 6 or less, the error is always corrected by the C2 code. When decoding C1 code, the pointer is set to 1 when an error of 2 symbols or more occurs.
When TR exceeds 6, the possibility that the error cannot be corrected increases even with the C2 code. Therefore, the EPTR boundary condition is set to (EPTR = 6).

The boundary condition regarding the number of errors at the time of C2 decoding expressed by the above-mentioned equation (1) is determined as follows from the randomness and burstiness of errors.

The worst condition in which a random error cannot be corrected is when there are three C1 code sequences each including a three-symbol error, and three of these nine error symbols are included in the same C2 code sequence. At this time, it becomes impossible to correct 9 error symbols. Therefore, (ECW1 ≦ 3, EPTR ≦ 6) is set as a boundary condition in order to allow up to one C1 code sequence having a 3-symbol error and reduce the risk of C2 decoding error. Regarding the burst error, since the C2 code sequence has a length of 20 symbols, the value of equation (1) is divided by numerical values of 20, 40 and 60, and when the value is 10 or less, the burst error is small.

In consideration of the above points, based on the four status signals indicating the decoding status stored in the decoding status register 47,
The system controller 13 determines the error state of the written data (this data includes code data such as an address or normal data written in the data section).

In the present invention, the error state is determined according to the degree of random error and burst error included in the write data, which is estimated based on the four state signals indicating the decode state.

FIG. 7 shows the criteria for judging the error state. In FIG. 7, the "decoding state at the time of C2 decoding" indicates the number of each of four state signals indicating the decoding state obtained as a result of C2 decoding. The “error state” indicates the degree of random error and burst error in the write data, which is estimated when the “decoding state at the time of C2 decoding” is discriminated as A to F. What is "margin"?
It shows how much margin of correction capability is available when error correction is applied to write data.

By the way, the fact that the correction capability has a margin means that the write data has few errors, and the fact that the correction capability does not have a margin means that the write data has many errors. In other words, this also means how exactly the data was written in the data recording area on the disc 1. From this fact, the "margin" in the figure indicates what kind of data the data recording area on the disc 1 in which the write data is recorded is suitable (is usable). There is.
That is, when the determination result is estimated to be "somewhat random error" such as A, code data in which no error is allowed is suitable, and the determination result is "There are many short burst errors" such as C. When it is estimated, it is suitable for general digital data such as audio data and video data, and when it is estimated that “there is a long burst error” such as F, which data is It means that it is not suitable for recording.

The system controller 13 determines whether the four status signals sent from the decoding status register 47 are applicable to the decoding statuses A to F in FIG.
The error status is judged, and as a result of the judgment, the error status is A
Interface with a determination signal indicating which one of
To the host processor 15 via 14.

The host processor 15 determines whether the write data needs to be rewritten based on the received determination signal. For example, the host processor 15 is separately informed as to whether the received determination signal is for the address portion or the data portion. Based on this information and the determination signal, the determination signal for the address portion is received. Is A,
When it indicates a value other than B, or when the determination signal indicates A or B but the determination signal in the data section indicates F, it is determined that rewriting is necessary and a write command to the replacement sector is generated.

Note that the criterion for determining whether or not this rewriting is necessary is not limited to this example, and is appropriately set according to the type of data in the data section, the quality of the disc, and the like. In addition, the system controller 13 determines whether or not this rewriting is necessary.
May be performed in.

〔The invention's effect〕

According to the present invention, when the write data is recorded, it is checked whether or not the recording was correctly performed with a margin of error correction, so that the read data may be erroneously read. Can be removed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a part of the configuration of an embodiment of the present invention, and FIG. 3 is an embodiment of the present invention. 4 is a schematic diagram showing the structure of the address part of the data format of FIG. 4, FIG. 4 is a schematic diagram showing the structure of the data part of the format of one embodiment of the present invention, and FIG. 5 is an embodiment of the present invention. A block diagram used for explaining the operation of the error correction coding and decoding of the example, FIG. 6 is a block diagram showing the configuration of an encoder / decoder of the error correction code, and FIG. 7 is a description of the operation of one embodiment of the present invention. It is a schematic diagram used for. 1 ... disk, 3 ... optical head, 4 ... laser generation circuit, 5 ... drive interface, 11 ... error correction code processor, 12 ... buffer memory, 13 ... system controller, 15 ... host processor , 47 ……
Decode status register.

Claims (1)

[Claims] 1. A digital data recording apparatus adapted to write digital data on a recording medium, and encoding means for encoding an error correction code on the digital data, and encoded data from the encoding means. Writing means for writing the data in a recording medium, and a control means for reading the written data from the recording medium after writing a predetermined amount of the encoded data in a predetermined recording area of the recording medium, The read coded data is supplied, and the same error correction processing as that performed at the time of reproduction is performed, and a code sequence that cannot be corrected in the error correction processing with respect to a predetermined amount of the read coded data. Number, the number of code sequences that have been error-corrected, and the number of code sequences that have been detected as error by the error-correcting code, Error correction means for outputting a decode status signal indicating the decode status of encoded data, decode status signal storage means for storing the decode status signal, output of the decode status signal storage means, and error correction By comparing with a threshold value determined from the correction capability of the code, the error state determination means for determining the error state of the written encoded data, and the determination result of the error state determination means A digital data recording apparatus, characterized in that the writing means comprises rewriting judgment means for judging whether or not the encoded data should be rewritten.