JPH0668674A - Semiconductor storage circuit - Google Patents

Abstract

PURPOSE:To attain high integration and to reduce power consumption. CONSTITUTION:A flip-flop 1 is constituted by cross-connecting the inputs and outputs of two inverters INV1, INV2 composed by connecting a load elements D1, D2 and driving elements E1, E2 in series between a power source line with high potential VDD and a power source line with low potential VSS. The flip-flop 1 and two bit lines BL, -BL are connected by switching transistors 2, 3 connected to a word line WL having the same gate electrode, respectively. Current decreasing elements 4, 5 for decreasing the current flowing between the relevant load elements D1, D2 and the driving elements E1, E2 are provided between the load elements D1, D2 and the driving elements E1, E2 composing the inverters INV1, INV2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit, and more particularly, for example, SRAM (Static Random Acce
Suitable for use in the field of semiconductor memory such as ss Memory),
The present invention relates to a semiconductor memory circuit that reduces current consumption while achieving high integration. BACKGROUND OF THE INVENTION In recent years, with the reduction in size and weight of semiconductor devices, many semiconductor memory circuits with higher integration have been developed.

Among semiconductor memory circuits, a memory called SRAM has two inverters I as shown in FIG.
A flip-flop 1 formed by cross-connecting the inputs and outputs of NV1 and INV2, and switching transistors 2 and 3 having gate electrodes connected to the same word line WL. The switching transistors 2 and 3 form the flip-flop 1 and the bit line BL. , ￣ BL (hereinafter, ￣ XX is a top bar indicating the inversion of XX) is connected to a DRAM (Dynamic Random Access Me).
mory) and the like, the device configuration becomes larger.

However, in such a semiconductor memory, the power consumption tends to increase due to high integration in order to increase the capacity. Therefore, it is required to suppress the current consumption of the memory cell in order to reduce the power consumption of the memory.

[0004]

2. Description of the Related Art As a conventional semiconductor memory circuit of this type, an inverter system which constitutes a memory cell
For example, an E / D type SRAM as shown in FIG.
There is a CMOS type SRAM as shown in 0 and a high resistance load type SRAM as shown in FIG.

Hereinafter, the E / D system, the CMOS system,
The characteristics of each of the three typical high resistance load methods are described. E / D type SRAM is a depletion type MOS
The inverter uses a transistor as a load. Since the load current of the inverter is large, the current consumption of the memory cell is large and it is difficult to increase the capacity.

The CMOS type SRAM uses a CMOS inverter as an inverter, and in a stable state, only a leak current flows through the CMOS inverter. Therefore, the current consumption of the memory cell is most advantageous, but in the CMOS circuit, Since a region for separating the nMOS and the pMOS is required, the memory cell size becomes very large.

The high resistance load type SRAM uses an inverter which is not doped with impurities or uses a small amount of doped polysilicon as a load, and this resistance shows a very high resistance of several hundred GΩ. Since a minimum load current for maintaining the high level output of is supplied, the current consumption of the memory cell can be significantly reduced as compared with the E / D method.

Further, since the polysilicon resistance originally has a high specific resistance, the area occupied by the resistance is small and the MOS transistor needs to be formed on the substrate. However, the polysilicon resistance can be formed on the upper layer of the MOS transistor. Since this is possible, the memory cell size of the high resistance load method is the smallest as compared with other methods. Therefore, the high resistance load method is used for the purpose of reducing the memory cell size to increase the capacity, and the CMOS method is used for the purpose of reducing the power consumption.

[0009]

However, in such an SRAM excluding the conventional CMOS method, the load current flowing through the load element forming the inverter is relatively large, and therefore there is a problem with respect to power consumption. . Also,
The CMOS type SRAM has a problem that it is not suitable for high integration because the memory cell size becomes large as described above.

Therefore, in order to increase the degree of integration, power consumption increases, and in order to suppress the power consumption, it is necessary to sacrifice the degree of integration. [Purpose] Therefore, an object of the present invention is to provide a semiconductor memory circuit that achieves high integration while reducing power consumption.

[0011]

In order to achieve the above object, a semiconductor memory circuit according to the present invention has a principle diagram shown in FIG. 1 in which a semiconductor memory circuit is provided between a high potential power supply line V _DD and a low potential power supply line V _SS. Two inverters INV1 and INV2 in which load elements (in this case, depletion type N-channel transistors) D1 and D2, and drive elements (in this case, enhancement type N-channel transistors) E1 and E2 are connected in series.
The input and output of are cross-connected to form the flip-flop 1.
In the semiconductor memory circuit in which the flip-flop 1 and the two bit lines BL and BL are connected by switching transistors 2 and 3 whose gate electrodes are connected to the same word line WL, the inverters INV1 and INV are provided.
2, load elements D1 and D2, and drive elements E1
Between E2, the load elements D1 and D2 and the drive element E
Current reducing elements 4, 5 for reducing the current flowing between 1 and E2
Is provided.

In this case, the current reducing elements 4 and 5 are depletion type N-channel transistors or enhancement type N-channel transistors, or diodes in the forward direction from the high potential power line side to the low potential power line side. It is preferable.

[0013]

According to the present invention, the current reducing element is provided between the load element and the driving element forming the inverter of the flip-flop, so that the current flowing through the memory cell can be reduced without using the CMOS circuit. That is, since the current flowing through the memory cell is suppressed in the configuration in which the integration degree is prioritized, the power consumption is reduced while maintaining the high integration degree.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing a first embodiment of a semiconductor memory circuit according to the present invention, and is a circuit diagram showing a configuration of a main part thereof. First, the configuration will be described.

In FIG. 2, the same numbers as the numbers given to the principle diagram shown in FIG. 1 indicate the same parts. The semiconductor memory circuit of this embodiment is roughly classified into two inverters INV.
1, an inverter INV2, and a switching transistor 2 and 3.
1, INV2 are high potential power line V _DD and low potential power line V _SS
And a depletion-type N-channel MESFET (Metal-Semiconductor Field)
Effect Transistor: hereinafter simply referred to as a transistor)
D1, D2, depletion type N which is a current reducing element
Channel transistors 4a and 5a and enhancement type N-channel transistors E1 and E2 which are driving elements
It consists of

In this embodiment, depletion type N-channel transistors 4a and 5a are used as the current reducing elements.
Using depletion type N-channel transistor 4
a and 5a are commonly connected to the drain terminal of the depletion type N-channel transistors D1 and D2, and the drain terminals of the depletion type N-channel transistors 4a and 5a are connected to the enhancement type N-channel transistors D1 and D2. It is connected to the drain terminals of the channel transistors E1 and E2.

Next, the operation will be described. FIG. 3 shows a drain current curve obtained from the characteristic of the output current with respect to the input voltage of the depletion type N-channel transistor (hereinafter referred to as the IV characteristic). In FIG. 3, ˜ denotes the IV characteristics of the depletion type N-channel transistor when the gate bias voltage V _G is changed in five steps, and the broken line curve in FIG. 3 indicates the source at each gate bias voltage V _G. It is a drain current curve _{calculated |} required from the drain current Ids.

That is, as shown in FIG. 3, the characteristics of the depletion type N-channel transistor in this embodiment are as follows: when the gate bias voltage V _G is lowered from V _G2 to V _G1 by ΔV _G. Since the source-drain current I _ds can be narrowed down by ΔI _ds by utilizing the IV characteristic of the N-channel transistor, the power consumption can be reduced.

FIG. 4 is a diagram showing a second embodiment of the semiconductor memory circuit according to the present invention, and is a circuit diagram showing the configuration of the main part thereof. First, the configuration will be described. In addition, in FIG.
The same numbers as those given to the first embodiment shown in FIG.

In this embodiment, enhancement type N-channel transistors 4b and 5b are used as current reducing elements,
Enhancement type N-channel transistors 4b and 5b
Of the depletion type N-channel transistors D1 and D2 are commonly connected to the drain terminals of the enhancement type N-channel transistors 4b and 5b, and the source terminals of the enhancement type N-channel transistors 4b and 5b are connected to the enhancement type N-channel transistors E1 and E2. It is connected to the drain terminal of.

Like the depletion type transistor, no current flows in the enhancement type transistor when the voltage is 0 V, and the operating region thereof is limited. However, when the operating region is within the operating region of the enhancement type transistor in advance. Does not always flow current unlike a depletion type transistor, so in this embodiment,
Power consumption can be further reduced as compared with the first embodiment.

FIGS. 5 and 6 are views showing a third embodiment of the semiconductor memory circuit according to the present invention, FIG. 5 is a circuit diagram showing the configuration of the main part thereof, and FIG. 6 is a configuration example of the diode of FIG. It is a circuit diagram. First, the configuration will be described. In addition, in FIG.
The same numbers as those given to the second embodiment shown in FIG. 4 indicate the same parts.

In this embodiment, the diodes 4c and 5c which are in the forward direction from the high potential power line side to the low potential power line side are used as the current reducing element. The diodes 4c and 5c in this embodiment are As shown in FIG. 6, the Schottky gate contact between the gate terminal and the drain terminal of the depletion type N-channel transistor having the open source terminal is used.

Next, the operation will be described. FIG. 7 shows a drain current curve obtained from the IV characteristic of the depletion type N-channel transistor. In FIG. 3, ˜ denotes IV characteristics of the depletion-type N-channel transistor when the gate bias voltage V _G is changed in five steps,
The curve indicated by the broken line is a drain current curve obtained from the source-drain current I _{ds at} each gate bias voltage V _G.

That is, as shown in FIG. 3, the characteristics of the depletion-type N-channel transistor in this embodiment are as follows: The depletion-type N-channel transistor when the gate bias V _{G2 is} lowered to V _G1 by ΔV _G. I-
By utilizing the V characteristic, the source-drain current I
_{Since ds} can be narrowed down by ΔI _ds , power consumption can be reduced. Next, the operation will be described.

FIG. 7 shows the IV characteristic of the diode. That is, as shown in FIG. 7, since the IV characteristic of the diode is expressed by an exponential function, as in the case of the depletion type N-channel transistor in the first embodiment,
When the gate bias voltage V _G is reduced from V _G2 to V _G1 by ΔV _{G, the} source-drain current I _ds can be narrowed down by ΔI _ds by utilizing the IV characteristic of the diode. Can be reduced.

Incidentally, the amount of change ΔI _ds of the source-drain current I _ds in this case is smaller than the amount of change ΔI _ds of the gate bias voltage in comparison with the case of the first embodiment (see FIG. 3).
Since the IV characteristic exponentially changes steeply with respect to V _G , the source-drain current I _ds can be greatly reduced. As a result, in this embodiment, the power consumption can be further reduced as compared with the above-described first and second embodiments.

As described above, in this embodiment, as the current reducing element, for example, in the inverter portion forming the memory cell,
By using a diode, a depletion-type N-channel transistor, or an enhancement-type N-channel transistor, power consumption can be suppressed even for a memory cell having a structure in which the degree of integration is prioritized.

Therefore, a high degree of integration can be ensured and power consumption can be reduced. In addition,
Although the above embodiment describes the E / D type SRAM configuration, the present invention is not limited to this, and the SRAM configuration may be a high resistance load type.

[0030]

According to the present invention, the current flowing through the memory cell can be reduced without using the CMOS circuit by providing the current reducing element between the load element and the driving element which constitute the inverter of the flip-flop. Therefore, since the current flowing through the memory cell can be suppressed in the configuration in which the integration degree is prioritized, the power consumption can be reduced while maintaining the high integration degree.

[Brief description of drawings]

FIG. 1 is a principle diagram of a semiconductor memory circuit of the present invention.

FIG. 2 is a circuit diagram showing a main configuration of the first embodiment.

FIG. 3 is a diagram showing characteristics of a depletion type transistor.

FIG. 4 is a circuit diagram showing a main configuration of a second embodiment.

FIG. 5 is a circuit diagram showing a main configuration of a third embodiment.

6 is a circuit diagram showing a configuration example of a diode of FIG.

FIG. 7 is a diagram showing a characteristic of an output current with respect to an input voltage of a diode.

FIG. 8 is a circuit diagram showing a configuration of a conventional SRAM.

FIG. 9 is a circuit diagram showing a configuration of an E / D type SRAM.

FIG. 10 is a circuit diagram showing a configuration of a CMOS SRAM.

FIG. 11 is a circuit diagram showing a configuration of a high resistance load type SRAM.

[Explanation of symbols]

1 Flip-flop 2, 3 Switching transistor 4,5 Current reduction element 4a, 5a Depletion type N channel transistor (current reduction element) 4b, 5b Enhancement type N channel transistor (current reduction element) 4c, 5c Diode (current reduction element) ) D1, D2 Depletion type N-channel transistor (load element) E1, E2 Enhancement type N-channel transistor (driving element) INV1, INV2 Inverter BL, ￣ BL Bit line WL Word line

Claims (3)

[Claims] 1. A flip-flop is formed by cross-connecting the input and output of two inverters in which a load element and a drive element are connected in series between a high potential power line and a low potential power line. A semiconductor memory circuit in which two bit lines are connected by switching transistors each having a gate electrode connected to the same word line, wherein the load element and the drive element are arranged between the load element and the drive element that form the inverter. A semiconductor memory circuit having a current reducing element for reducing a current flowing between the elements. 2. The semiconductor memory circuit according to claim 1, wherein the current reduction element is a depletion type N channel transistor or an enhancement type N channel transistor. 3. The semiconductor memory circuit according to claim 1, wherein the current reducing element is a diode that is forward from the high potential power line side to the low potential power line side.