JPH0656839B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0656839B2 JPH0656839B2 JP5824684A JP5824684A JPH0656839B2 JP H0656839 B2 JPH0656839 B2 JP H0656839B2 JP 5824684 A JP5824684 A JP 5824684A JP 5824684 A JP5824684 A JP 5824684A JP H0656839 B2 JPH0656839 B2 JP H0656839B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- laser
- substrate
- amorphous
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000000034 method Methods 0.000 title description 16
- 239000000758 substrate Substances 0.000 claims description 14
- 239000011521 glass Substances 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 4
- 230000001678 irradiating effect Effects 0.000 claims 2
- 239000000463 material Substances 0.000 claims 1
- 239000010408 film Substances 0.000 description 34
- 229910021417 amorphous silicon Inorganic materials 0.000 description 16
- 239000010410 layer Substances 0.000 description 13
- 238000010438 heat treatment Methods 0.000 description 6
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 6
- 239000007789 gas Substances 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000005224 laser annealing Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- -1 argon ion Chemical class 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052779 Neodymium Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000002441 X-ray diffraction Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000010979 ruby Substances 0.000 description 1
- 229910001750 ruby Inorganic materials 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Optics & Photonics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】 〔発明の利用分野〕 本発明は、半導体装置の製造方法に関し、詳しくは低抵
抗のアモルファス相を含有するｎ又はｐ形半導体部を有
する薄膜半導体装置の製造方法に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a thin film semiconductor device having an n-type or p-type semiconductor portion containing a low resistance amorphous phase.
従来のアモルファスＳｉ相を含有する半導体薄膜は、ガ
ラス、金属又は高分子薄板上にプラズマＣＶＤ法などの
方法で形成され、導電型の制御はＰＨ３やA5H3ガスを流
してのｎ型ドーピングもしくはB2H6ガスを流してのｐ形
ドーピンクによって行っていた。かかるドープドＳｉ膜
の抵抗率はｐ形で約１０３Ω・ｃｍ、ｎ形で１０２Ω・
ｃｍと高く、高い直列抵抗のため素子性能が劣ってい
た。又、ｎ形ドーピングの場合、プラズマパワーを増加
するなどの方法でアモルファス相を微結晶化することも
可能であるが、得られた抵抗率は約１Ω・ｃｍとあまり
低くはない。A conventional semiconductor thin film containing an amorphous Si phase is formed on a glass, metal or polymer thin plate by a method such as a plasma CVD method, and the conductivity type is controlled by n type by flowing a PH 3 or A 5 H 3 gas. Doping or p-type doping with B 2 H 6 gas flow was used. The resistivity of such a doped Si film is about 10 3 Ω · cm for p-type and 10 2 Ω · for n-type.
cm, and the device performance was poor due to the high series resistance. Further, in the case of n-type doping, it is possible to microcrystallize the amorphous phase by increasing the plasma power, but the obtained resistivity is not so low as about 1 Ω · cm.
本発明の目的は、かかる従来の問題点を解決し、低抵抗
の導電型層を形成できる半導体装置の製造方法を提供す
ることにある。An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the above-mentioned conventional problems and can form a conductive layer having a low resistance.
従来、半導体膜の低抵抗化を実現する方法として熱処理
法がある。しかし、アモルファス膜の場合、通常の電気
炉を用いる長時間熱処理法では、活性層であるノヴドー
プ層が変質し、デバイスが劣化してしまう。この点を解
決するため、本発明では、熱処理時間が１秒以下のレー
ザを用いた短時間熱処理法を用いる。レーザとして、パ
ルスレーザとＣＷレーザがあり、ＣＷの場合走査速度を
早くすれば実質的に短時間の熱処理が可能である。Conventionally, there is a heat treatment method as a method for realizing a low resistance of a semiconductor film. However, in the case of an amorphous film, the long-time heat treatment method using an ordinary electric furnace deteriorates the nove-doped layer that is the active layer and deteriorates the device. In order to solve this point, in the present invention, a short-time heat treatment method using a laser having a heat treatment time of 1 second or less is used. There are pulse lasers and CW lasers as lasers, and in the case of CW, heat treatment can be performed in a substantially short time by increasing the scanning speed.
かかるレーザとして次のものがある。パルスレーザとし
て、エキシマレーザ（波長１５７〜３５１ｎｍ）、ルビ
ーレーザ（６９４ｎｍ）、ネオジウムＹＡＧ（２６６，
５３２，１０６４ｎｍ）、ガラスレーザ（５３１ｎｍ）
やアレキサンドライトレーザ（７００〜８１８ｎｍ）な
どがある。ＣＷレーザとして、Ａｒイオンレーザ（２５
７ｎｍ）はHeNeレーザ（６３３ｎｍ）などがある。今
迄、アモルファスＳｉのレーザアニールとして、Ｑスイ
ッチのＮｄ：ＹＡＧレーザ（１０６４ｎｍ）が用いられ
た例は知られているが、アモルファスＳｉ膜の吸収係数
からして適切な波長では無く、従って良好なデバイス特
性は得られていない。The following are such lasers. As a pulse laser, an excimer laser (wavelength 157 to 351 nm), a ruby laser (694 nm), a neodymium YAG (266,
532, 1064 nm), glass laser (531 nm)
And alexandrite laser (700 to 818 nm). As a CW laser, an Ar ion laser (25
7 nm) includes HeNe laser (633 nm). Up to now, an example in which a Q-switched Nd: YAG laser (1064 nm) is used for laser annealing of amorphous Si has been known, but it is not an appropriate wavelength because of the absorption coefficient of the amorphous Si film, and therefore it is preferable. Device characteristics have not been obtained.
アモルファスＳｉ半導体装置で用いられる半導体膜の厚
さは通常１μｍ以下であるので吸収係数として１０４ｃ
ｍ−１以上の値を持つレーザ波長を選択する必要があ
る。このためには、アモルファスＳｉ膜の場合、７５０
ｎｍより短かい波長のレーザ光を用いる必要がある。特
に、上記各種レーザ光の中で、波長３００ｎｍ以下のレ
ーザ光を用いれば吸収係数は１０６ｃｍ−１となり光の
吸収深さは約１０ｎｍで縦方向の上部半導体層のみ熱処
理できるなどの利点を有する。これに適したレーザとし
て、エキシマレーザ、アルゴンイオンレーザとＮｄ：Ｙ
ＡＧレーザ（波長＝重型で２６６ｎｍ）がある。特に、
エキシマレーザは励起ガスの種類を変えて、発振波長を
変えることが可能である。例えば、Ｆ２（１５７ｎ
ｍ）、ＡｒＦ（１９３ｎｍ）、ＫｒＣｌ（２２２ｎ
ｍ）、ＫｒＦ（２４８ｎｍ）、ＸｅＢｒ（２８２ｎ
ｍ）、ＸｅＣｌ（３０８ｎｍ）とＸｅＦ（３５１ｎｍ）
で出力も数十Ｗ迄の大出力で大口径のレーザが得られて
いる。Since the thickness of the semiconductor film used in the amorphous Si semiconductor device is usually 1 μm or less, the absorption coefficient is 10 4 c.
It is necessary to select a laser wavelength having a value of m −1 or more. To this end, in the case of an amorphous Si film, 750
It is necessary to use laser light having a wavelength shorter than nm. In particular, among the various laser lights described above, if a laser light having a wavelength of 300 nm or less is used, the absorption coefficient becomes 10 6 cm −1 , the light absorption depth is about 10 nm, and only the upper semiconductor layer in the vertical direction can be heat-treated. Have. Suitable lasers for this are excimer laser, argon ion laser and Nd: Y
There is an AG laser (wavelength = heavy type 266 nm). In particular,
The excimer laser can change the oscillation wavelength by changing the kind of excitation gas. For example, F 2 (157n
m), ArF (193 nm), KrCl (222n)
m), KrF (248 nm), XeBr (282n)
m), XeCl (308 nm) and XeF (351 nm)
Therefore, a large output laser with a large output up to several tens of watts has been obtained.
本発明は、かかる短波長のレーザを用い、アモルファス
Ｓｉ相を含有する半導体膜の熱処理を行う。半導体膜と
して、Ｂ又はＡｌなどのｐ形不純物、Ｐ又はＡｓなどの
ｎ形不純物を含有するアモルファスＳｉ：Ｈ膜、微結晶
化Ｓｉ：Ｈ膜、SiGe：Ｈ膜、ＳｉＮ：Ｈ膜やＳｉＣ：Ｈ
膜などがある。不純物を該Ｓｉ膜中に含有させる工程と
して、プラズマＣＶＤなどの膜形成中にガスから導入す
る方法とノンドープ又は低濃度ドープ層中にイオン打込
み法で導入する方法の２種類がある。In the present invention, the semiconductor film containing the amorphous Si phase is heat-treated by using such a short wavelength laser. As the semiconductor film, an amorphous Si: H film containing a p-type impurity such as B or Al and an n-type impurity such as P or As, a microcrystallized Si: H film, a SiGe: H film, a SiN: H film or a SiC: H
There are membranes. There are two types of steps of incorporating impurities into the Si film, a method of introducing from a gas during film formation such as plasma CVD and a method of introducing into a non-doped or low-concentration doped layer by an ion implantation method.
以下、本発明の実施例を説明する。 Examples of the present invention will be described below.
実施例１ グロー放電を用いるプラズマＣＶＤ法により、ＳｉＨ４
−Ｂ２Ｈ６（又は、ＰＨ３）系ガスを用い、Ｂ又はＰド
ープのアモルファスＳｉ膜を形成した。その膜の抵抗率
を第１表に示す。Example 1 SiH 4 was formed by a plasma CVD method using glow discharge.
-B 2 H 6 (or, PH 3) with system gas to form an amorphous Si film of B or P-doped. The resistivity of the film is shown in Table 1.
レーザとして、ＫｒＦ系エキシマレーザ（波長２４８ｎ
ｍ、パルス幅１５ｎｓ）を用い、該アモルファスＳｉ膜
を照射した。第１図は、レーザ照射強度を変えて照射し
た後の抵抗率変化を示す。レーザパワー密度０．２Ｊ／
ｃｍ２迄はスーパーリニアに抵抗率が減少し、その後直
線的に減少している。得られた抵抗率は第１表の値に比
べて極めて小さく、通常の多結晶膜と同程度の値となっ
ている。特に、レーザパワー密度０．２Ｊ／ｃｍ２以上
でのアニール膜はＸ線回折によると結晶化していること
が明らかになった。レーザパワー密度０．２Ｊ／ｃｍ２
以下でアニールした膜は、微結晶相を含む非晶質膜で、
膜表面の形状は平滑であり、デバイス作製用として適し
ている。 As a laser, a KrF excimer laser (wavelength 248n
m, pulse width 15 ns) was used to irradiate the amorphous Si film. FIG. 1 shows the change in resistivity after irradiation with varying laser irradiation intensity. Laser power density 0.2J /
The resistivity decreases super linearly up to cm 2 , and then decreases linearly. The obtained resistivity is extremely smaller than the values shown in Table 1, and is about the same value as that of an ordinary polycrystalline film. Particularly, it was revealed by X-ray diffraction that the annealed film at a laser power density of 0.2 J / cm 2 or more was crystallized. Laser power density 0.2 J / cm 2
The film annealed below is an amorphous film containing a microcrystalline phase,
The shape of the film surface is smooth and suitable for device fabrication.
実施例２ ＣＷ（連続発振）のアルゴンイオンレーザを用い、実施
例１と同様な非晶質膜にレーザアニールを行った。Example 2 The same amorphous film as in Example 1 was laser-annealed using a CW (continuous oscillation) argon ion laser.
波長はＡＤＰ光学結晶を用い第２高調波である２５７ｎ
ｍとし、走査速度１ｍｍ／秒で該ドープ非晶質シリコン
膜をアニールした。照射後の抵抗変化は第１図と同様で
あった。この方法では、ビーム走査により、均質に熱処
理を行える特長がある。The wavelength is 257n which is the second harmonic using ADP optical crystal.
m, and the doped amorphous silicon film was annealed at a scanning speed of 1 mm / sec. The change in resistance after irradiation was the same as in FIG. This method has a feature that the heat treatment can be performed uniformly by beam scanning.
実施例３ グロー放電を用いるプラズマＣＶＤ法により、第２図に
示したように、ガラス基板１上に、ｎ形層２、ｉ形層３
およびｐ形層４を形成した。その後、波長１９３ｎｍの
ＡｒＦエキシマレーザ７を照射した結果、照射前の抵抗
率２．４×１０５Ω・ｃｍが照射後３．１×１０Ω・ｃ
ｍと抵抗率が低下した。Example 3 As shown in FIG. 2, an n-type layer 2 and an i-type layer 3 were formed on a glass substrate 1 by a plasma CVD method using glow discharge.
And p-type layer 4 was formed. Then, as a result of irradiation with ArF excimer laser 7 having a wavelength of 193 nm, the resistivity before irradiation was 2.4 × 10 5 Ω · cm and the resistivity after irradiation was 3.1 × 10 Ω · c.
m and the resistivity decreased.
これにより、ｐｉｎ型ダイオードの直列抵抗が低下し、
整流比が改善された。This reduces the series resistance of the pin diode,
The rectification ratio was improved.
実施例４ 実施例３においてｐ形層４として、炭素入りの非晶質シ
リコンカーバイド膜を用いた。レーザ照射前の抵抗率３
×１０７Ω・ｃｍが照射後３．０×１０６Ω・ｃｍと抵
抗率を低減することができた。Example 4 In Example 3, as the p-type layer 4, an amorphous silicon carbide film containing carbon was used. Resistivity before laser irradiation 3
The resistivity of × 10 7 Ω · cm was 3.0 × 10 6 Ω · cm after irradiation, and the resistivity could be reduced.
実施例５ シリコン薄膜を用いたＭＯＳＦＥＴの製造方法を第３図
に示す。Example 5 A method of manufacturing a MOSFET using a silicon thin film is shown in FIG.
ガラス基板１上にゲート電極（Ｍｏ，Ｃｒなど）１１を
形成後、プラズマＣＶＤ法によりＳｉＯ２膜１２および
ｎ形非晶質シリコン膜１３を形成した。ソースおよびド
レイン電極１４および１５を蒸着し、ガラス基板１の下
部からレーザ７の照射を行った。レーザ照射条件は実施
例１〜３と同様で良い。このレーザ照射により、ゲート
電極１１上の非晶質シリコン膜は変化しないがソースお
よびドレイン電極１４と１５の下部の非晶質シリコン膜
は結晶質を含むシリコン膜１６に変質した。After forming the gate electrode (Mo, Cr, etc.) 11 on the glass substrate 1, the SiO 2 film 12 and the n-type amorphous silicon film 13 were formed by the plasma CVD method. The source and drain electrodes 14 and 15 were vapor-deposited, and the laser 7 was irradiated from below the glass substrate 1. The laser irradiation conditions may be the same as in Examples 1 to 3. By this laser irradiation, the amorphous silicon film on the gate electrode 11 was not changed, but the amorphous silicon film below the source and drain electrodes 14 and 15 was changed to a silicon film 16 containing a crystalline substance.
実施例６ シリコン薄膜ＭＯＳＦＥＴの他の製造方法を第４図に示
す。Example 6 Another method of manufacturing a silicon thin film MOSFET is shown in FIG.
ガラス基板１上にソースおよびドレイン電極２１および
２２を形成後、プラズマＣＶＤ法によりＳｉＯ２２３お
よびｎ−形非晶質シリコン膜２４を連続形成した。ゲー
ト電極２５を形成後、該ゲート電極をマスクとしてp+イ
オン８の打込みを行い、実施例１〜３と同様なレーザア
ニールを行った。このレーザアニールにより、低抵抗シ
リコン膜２６を形成した。この方法で、ＭＯＳＦＥＴの
セルファラインによる形成が可能となり、得られたＦＥ
ＴのＯＮ／ＯＦＦ比も向上した。After forming the source and drain electrodes 21 and 22 on the glass substrate 1, a SiO 2 23 and an n − -type amorphous silicon film 24 were continuously formed by a plasma CVD method. After forming the gate electrode 25, p + ions 8 were implanted using the gate electrode as a mask, and the same laser annealing as in Examples 1 to 3 was performed. By this laser annealing, the low resistance silicon film 26 was formed. By this method, the MOSFET can be formed by self-alignment, and the obtained FE
The ON / OFF ratio of T has also improved.
本発明によれば下記のことが実現できる。 According to the present invention, the following can be realized.
(1) 極めて低抵抗のｎ形およびｐ形層を作製できる。(1) Extremely low resistance n-type and p-type layers can be produced.
(2) セルアラインが可能である。(2) Self-alignment is possible.
(3) 極く表面層のみアニールできる。(3) Only the surface layer can be annealed.
(4) 低温プロセスである。(4) It is a low temperature process.
従って、本発明により、安価な大面積基板上に、秀れた
性能を有する半導体薄膜装置を作製することができる。Therefore, according to the present invention, a semiconductor thin film device having excellent performance can be manufactured on an inexpensive large-area substrate.
第１図は本発明の効果を説明するための図、第２図乃至
第４図は、それぞれ本発明の異なる実施例を示す工程図
である。 １……ガラス基板、２……ｎ形層、３……ｉ形層、４…
…ｐ形層、７……レーザ光、８……イオン、１１……ゲ
ート電極、１２……ＳｉＯ２膜、１３……ｎ形非晶質シ
リコン膜。FIG. 1 is a diagram for explaining the effect of the present invention, and FIGS. 2 to 4 are process diagrams showing different embodiments of the present invention. 1 ... Glass substrate, 2 ... n-type layer, 3 ... i-type layer, 4 ...
... p-type layer, 7 ... laser light, 8 ... ion, 11 ... gate electrode, 12 ... SiO 2 film, 13 ... n type amorphous silicon film.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 29/784 (72)発明者 斉藤 昭男 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内 (72)発明者 中谷 光雄 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内 (56)参考文献 特開 昭57−155726（ＪＰ，Ａ) 特開 昭55−75225（ＪＰ，Ａ)─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 5 Identification number Reference number within the agency FI Technical indication location H01L 29/784 (72) Inventor Akio Saito 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock company Hitachi Manufacturing Engineering Laboratory (72) Inventor Mitsuo Nakatani 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture Manufacturing Engineering Laboratory, Hitachi Ltd. (56) Reference JP-A-57-155726 (JP, A) JP-A 55-75225 (JP, A)
Claims (3)
形成する工程と、該ゲート電極を有する基板上に絶縁膜
を形成する工程と、該絶縁膜上に不純物が添加された非
晶質相シリコン膜を形成する工程と、該非晶質相シリコ
ン膜上に該ゲート電極を挾んでソース及びドレイン電極
を形成する工程と、その後、波長が３００ｎｍ以下で照
射強度０．２Ｊ／ｃｍ２以下の紫外レーザを該基板に照
射する工程とを有することを特徴とする半導体装置の製
造方法。1. A step of forming a gate electrode having a desired shape on a substrate, a step of forming an insulating film on a substrate having the gate electrode, and an amorphous material doped with impurities on the insulating film. Of a phase-phase silicon film, a step of sandwiching the gate electrode on the amorphous phase-silicon film to form source and drain electrodes, and then a wavelength of 300 nm or less and an irradiation intensity of 0.2 J / cm 2 or less. And a step of irradiating the substrate with an ultraviolet laser.
ン電極を形成する工程と、該ソース及びドレイン電極を
有する該基板上に不純物が添加された非晶質相シリコン
膜を形成する工程と、該非晶質相シリコン膜上に絶縁膜
を形成する工程と、該絶縁膜上で、かつ、該ソース及び
ドレイン電極の間に形成されたゲート電極を形成する工
程と、その後、波長が３００ｎｍ以下で照射強度０．２
Ｊ／ｃｍ２以下の紫外レーザを該基板に照射する工程と
を有することを特徴とする半導体装置の製造方法。2. A step of forming source and drain electrodes on a substrate in close proximity to each other, and a step of forming an impurity-doped amorphous phase silicon film on the substrate having the source and drain electrodes. A step of forming an insulating film on the amorphous phase silicon film, a step of forming a gate electrode formed on the insulating film and between the source and drain electrodes, and then at a wavelength of 300 nm or less. Irradiation intensity 0.2
And a step of irradiating the substrate with an ultraviolet laser of J / cm 2 or less.
とする特許請求の範囲第１項または第２項に記載の半導
体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein the substrate is a glass substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5824684A JPH0656839B2 (en) | 1984-03-28 | 1984-03-28 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5824684A JPH0656839B2 (en) | 1984-03-28 | 1984-03-28 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60202931A JPS60202931A (en) | 1985-10-14 |
| JPH0656839B2 true JPH0656839B2 (en) | 1994-07-27 |
Family
ID=13078761
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5824684A Expired - Lifetime JPH0656839B2 (en) | 1984-03-28 | 1984-03-28 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0656839B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8679973B2 (en) | 2006-10-11 | 2014-03-25 | Fujitsu Semiconductor Limited | Method of manufacturing semiconductor device |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07107894B2 (en) * | 1986-06-18 | 1995-11-15 | 松下電器産業株式会社 | Annealing method for polycrystalline thin film substrate |
| TW232751B (en) | 1992-10-09 | 1994-10-21 | Semiconductor Energy Res Co Ltd | Semiconductor device and method for forming the same |
| US5643801A (en) | 1992-11-06 | 1997-07-01 | Semiconductor Energy Laboratory Co., Ltd. | Laser processing method and alignment |
| US6544825B1 (en) | 1992-12-26 | 2003-04-08 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating a MIS transistor |
| US5719065A (en) | 1993-10-01 | 1998-02-17 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device with removable spacers |
| JP2546538B2 (en) * | 1994-07-11 | 1996-10-23 | ソニー株式会社 | Thin film transistor manufacturing method |
| JP3778456B2 (en) | 1995-02-21 | 2006-05-24 | 株式会社半導体エネルギー研究所 | Method for manufacturing insulated gate thin film semiconductor device |
| JP3989761B2 (en) | 2002-04-09 | 2007-10-10 | 株式会社半導体エネルギー研究所 | Semiconductor display device |
| US7038239B2 (en) | 2002-04-09 | 2006-05-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
| US7256421B2 (en) | 2002-05-17 | 2007-08-14 | Semiconductor Energy Laboratory, Co., Ltd. | Display device having a structure for preventing the deterioration of a light emitting device |
-
1984
- 1984-03-28 JP JP5824684A patent/JPH0656839B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8679973B2 (en) | 2006-10-11 | 2014-03-25 | Fujitsu Semiconductor Limited | Method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60202931A (en) | 1985-10-14 |
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