JPH0648439B2 - Sampling frequency converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial field B Outline of the invention C Conventional technology (Fig. 3) D Problems to be solved by the invention E Means for solving problems (Fig. 1) F Action G Example (1st embodiment) H of the present invention A Industrial field of application The present invention relates to a sampling frequency conversion device for converting a sampled and quantized sample sequence into a sample sequence having a sampling period different from this.

B SUMMARY OF THE INVENTION The present invention relates to a sampling frequency conversion device for converting a sampled and quantized sample sequence into a sample sequence having a sampling period different from this, and a timing pulse obtained by multiplying an input sampling frequency fsi by a clock input signal. And a counter that uses a timing pulse obtained by dividing the output sampling frequency fso as a reset input signal, and a first pulse that is supplied with the output signal of the counter and that uses a timing pulse obtained by dividing the output sampling frequency fso as a latch input signal. Register and this first
The hold data of the register is used as one input signal, and the output signal of the adder is used as a data input signal, and the second register is used as a latch input signal for the timing pulse having the output sampling frequency fso. The hold data of the second register is used as the other input signal of the adder, and the hold data of the second register is used as a parameter for calculating the output sample value or a control amount for converting the sampling frequency. The sampling frequency fsi of the above can be converted into an output sample sequence of a desired sampling frequency fso as a digital signal as it is, and the decomposition accuracy can be improved.

C Conventional Technology Generally, a PCM signal transmission system has been put to practical use, but the sampling frequency of the put to practical use is, for example, 44.1 kHz for a compact disc (CD),
There are various differences such as 32 kHz and 48 kHz in satellite broadcasting and 44.056 kHz in PCM processor, and it is required to make PCM signals having different sampling frequencies compatible with each other.

Conventionally, when converting the sampling frequency of this PCM signal, first, the PCM signal is digital-analog converted,
The converted analog signal is sampled again at a desired sampling frequency and then quantized to form a PCM signal having a desired sampling frequency. In this case, it is necessary to use a digital-analog converter and an analog-digital converter, the configuration is complicated and the cost is high, and the signal passes through the digital-analog converter and the analog-digital converter. There was an inconvenience that the quality deteriorated.

Therefore, as a sampling frequency conversion device for converting the sampling frequency of the PCM signal as a digital signal, there has been proposed a device shown in FIG. 3 (Japanese Patent Laid-Open No. 57-57).
No. 115150).

That is, in FIG. 3, (1) is the sampling frequency fs of the sample string for which the sampling frequency is to be converted.
The input sampling frequency signal input terminal to which the i signal is supplied is shown.
The sampling frequency fsi signal supplied to (1) is supplied to the PLL circuit (2) that doubles the frequency by 2 ^N times, for example, 2 ⁷ times, and 2 ^N · f obtained at the output side of this PLL circuit (2) is supplied.
The signal of frequency si is supplied to the clock signal input terminal c of the counter (3), and (4) shows the output sampling frequency signal input terminal to which the sampling frequency fso signal to be obtained is supplied. The sampling frequency fso signal supplied to the signal input terminal (4) is supplied to the reset terminal r of the counter (3) as a reset signal and to the latch terminal l of the register (5) that latches the count data of the counter (3). This output sampling frequency fso signal is supplied as the latch timing signal. In this case, since the counter (3) uses 1 / fsi as the count cycle, it requires an N-bit length.
The count data of the counter (3) is latched in the register (5) at the output sampling frequency fso, and immediately after that, the counter (3) is reset and continuously starts counting from 0. Therefore, the data stored in this register (5) consequently means the phase of the input sample point immediately before the output sample point (however, this phase is an instantaneous value, and 2 ^N is 1). I think it is standardized.) The hold data of this register (5) is supplied to the arithmetic circuit (6). Further, (7) shows an input sample string input terminal to which a sample string whose sampling frequency is to be converted is supplied, and the input sample string supplied to this input sample string input terminal (7) is an arithmetic circuit.
An output sample string output terminal for supplying to (6) and obtaining a sample string of a desired sampling frequency from this arithmetic circuit (6)
Derive (8).

In this case, the arithmetic circuit (6) can calculate the sample value of the desired output sample point from the input sample value using the phase data obtained in the register (5) as a parameter or control amount. This phase data {φJ}
The relationship between the input sample sequence {x _i } and the output sample sequence {yJ) on the time axis is as shown in FIG. Here, in order to facilitate understanding of this example, a typical method of the conventional configuration of the arithmetic circuit (6) will be described.

One of the methods is output sample value calculation by polynomial interpolation. FIG. 5 is a diagram for explaining a procedure of calculating an approximate value of an output sample value by linear interpolation (primary interpolation) as an example of polynomial interpolation. x _i and x _i−1 are amplitude values of the input sample sequence, yj is an amplitude value of the output sample value, and φj is a phase (0φj <1) with respect to the input sample point immediately before the output sample point. yj is calculated from x _i , x _j−1 , φj by the following relational expression.

yj = x _i-1 + (x _i −x _i-1 ) φ _j (1) This relational expression also shows that if the phase data of the output sample point is obtained, the value of the output sample sequence can be derived from the input sample sequence. means.

Even if a higher-order polynomial is used to further reduce the error in the approximate value, the output sample value can still be calculated from the input sample sequence using the phase data as a parameter.

When the arithmetic circuit (6) in FIG. 3 performs this polynomial interpolation operation, the data held in the register (5) indicates the phase data {φj} itself shown here.

Another method is a method that applies digital filtering.

The conversion of the sampling frequency such that the conversion ratio is L / M (L, M: integer) can be performed by the following procedure as shown in FIG.

First, L-1 between each sample of the input sample sequence {x _i }
Fill a sample with 0 values. As a result, the sampling frequency apparently increases L times, but the frequency spectrum of the sample sequence does not change. Next, change this sample string to "L / 2 times the sampling frequency range,
Sample sequence interpolated L times by performing convolution with "count sequence consisting of impulse response" having the characteristics of a low-pass filter in which only the signal band having the lower one of the input and output sampling frequencies is the pass band However, it is not necessary to perform this convolution operation over all the sampled points zeroed, because we are now trying to obtain the sampled value on the output sample point, and only calculate this output point. By doing so, the number of calculations is reduced to 1 / M.

Here, K ₀ , K ₁ , K ₂ , ... Is taken as an example of a counting sequence composed of impulse responses of a low-pass filter.
₂ r + 1 counting sequences of K _r , ... K _2r-1 , K _2r .

Convolve the input sample sequence {x _i } and this counting sequence,
The operation of obtaining the output sample sequence {yj} is represented by the following relational expression.

yj = ... + x _iz・ K _{r + L-φjL} + x _i-1・ K _r-φjL + x _i・ K _rL-φjL + x _{i + 1}
・ K _r-2L-φjL + …… (2) (φj = φ / L, 1 / L, 2 / L,…, (L-1) / L) As is clear from this equation, one output In order to calculate a sample, every L coefficients are extracted at equal intervals and a product-sum operation is performed. Therefore, as shown in the table of FIG. 7, a coefficient table composed of L coefficient sets is formed in advance by extracting and rearranging coefficients for every L coefficients, and a suitable coefficient set is calculated from the value of φj. It is convenient to set up a sequence to be selected.

Specifically, a method of selecting a coefficient set by separately storing the coefficient set in a memory element such as a ROM and allocating the addresses so that the phase data φj corresponds to each address can be considered.

Although the method of calculating the output sample value applying the digital filtering has been described above, the output sample value can be obtained from the input sample sequence by using this as a control amount by knowing the phase φj.

Although the operation of the typical configuration of the arithmetic circuit has been described above, the output sample value obtained by them is an approximate value obtained from the input sample sequence in any case. Then, increasing the resolution accuracy of the phase data supplied to the arithmetic circuit is a necessary condition for reducing the approximation error of the output sample value.

D Problems to be Solved by the Invention In the conventional configuration of FIG. 3, the resolution accuracy of the counter (3) cannot exceed 2 ^N. In order to further improve the disassembly accuracy with the configuration of FIG. 3, the frequency multiplication ratio of the PLL circuit (2) must be increased, but a certain range such as PLL
It is technically difficult to increase the frequency multiplication ratio when the output frequency of the circuit (2) exceeds 10 MHz (N = 7 when the input sampling frequency fsi is 44.1 kHz in this case), and the disassembly accuracy can be increased with a simple configuration. There was no inconvenience.

The present invention has been made in view of the above points and is configured to improve the disassembly accuracy with a simple configuration.

E Means for Solving the Problems The sampling frequency conversion device of the present invention is a counter having a timing pulse obtained by multiplying the input sampling frequency fsi as a clock input signal and a timing pulse obtained by dividing the output sampling frequency fso as a reset input signal.
(9) and the first register (10) which receives the output signal of the counter (9) and uses the timing pulse obtained by dividing the output sampling frequency fso as a latch input signal.
And an adder (11) which uses the hold data of the first register (10) as one input signal and an output signal of the adder (11) as a data input, and the output sampling frequency fs
Second with a timing pulse of o as a latch input signal
Register (12) of the second register (12), and the hold data of the second register (12) is used as the other input signal of the adder (11) and the hold data of the second register (12) is output as a sample value. It is used as a parameter for calculation or a control amount for sampling frequency conversion.

In the present invention, the sampling frequency fsi of the input sample sequence is changed to the desired sampling frequency fs in the present invention.
can be converted to the output sample sequence of o as a digital signal,
Further, in the present invention, the content of the first register (10) is fso /
It is rewritten every 2 ^M , but the same data is saved during that time, and this saved data is output sampling frequency f
Each so signal is cumulatively added through the adder (11), and the addition result is stored in the second register (12).
The lower bit of the hold data of the register (12) of is finally cut off and equivalently an M-bit shift write (1/2 ^M
Of the input sampling frequency fsi is divided into 2 ^N times and the output sampling frequency fso is divided into 1/2 ^M. The accuracy is 2 ^{N + M} , for example N = 7
When M = 9, the resolution precision is 2 ¹⁶ = 65536, and the conventional resolution precision of the configuration in FIG. 3 is, for example, 2 ⁷ = 128.
It is 512 times as compared with.

G Embodiment An embodiment of the sampling frequency conversion device of the present invention will be described below with reference to FIGS. 1 and 2. In FIG. 1, parts corresponding to those in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted.

Is In Figure 1, PLL for Baishu frequency sampling frequency fsi signal sample sequence to be converted sampling frequency supplied to the input sampling frequency signal input terminal (1) to 2 ^N times for example 2 ^7-fold 2 ^N · f supplied to the circuit (2) and obtained at the output side of this PLL circuit (2)
A signal of frequency si is supplied to the clock signal input terminal c of the counter (9). The sampling frequency fso signal to be supplied to the output sampling control signal input terminal (4) is divided into 1/2 ^M, for example, 1/2 ^9, and 1/2 ^M.
Divider fed to (13), supplies a signal of a frequency fso / 2 ^M obtained at the output side of the 1/2 ^M frequency divider (13) as a reset signal to the reset terminal r of the counter (9). In this case the counter
(9) has a bit length of N + M or more. A signal of a frequency fso / 2 ^M obtained at the output side of the 1/2 ^M divider (13) is supplied to the data input terminal of the count data first register (10) of the counter (9) The first It is supplied as a latch timing signal to the latch terminal 1 of the No. 1 register (10). In this case, the first register 10 has a bit length of N + M or more. Add hold data for this first register (10)
The output supplied to one input terminal of (11), the addition result of this adder (11) to the data input terminal of the second register (12) and the output sampling frequency signal input terminal (4) The sampling frequency fso signal is supplied to the latch terminal 1 of the second register (12) as a latch timing signal. In this case the adder (11) and the second register
(12) has a bit length of N + 2M or more. Out of the hold data of the second register (12), the upper N + M bits excluding the lower M bits are supplied to the arithmetic circuit (6), and all the hold data of the second register (12) are transferred to the adder (11). ) To the other input terminal. Others are the same as those in FIG.

Since this example is configured as described above, the count result of the counter (9) is the frequency obtained at the output side of the 1/2 ^M frequency divider (13).
It is latched in the first register (10) at the timing of the fso / 2 ^M signal, and immediately after this, the content of the counter (9) is reset, and the counter (9) starts counting from 0 again. The data held in the first register (10) is added to the hold data in the second register (12), and the addition result is latched in the second register (12) again for each output sampling frequency fso signal. It That is, the first register
The content of (10) is rewritten for each frequency fso / 2 ^M , but during that time the same data is saved. This saved data is cumulatively added via the adder (11) for each output sampling frequency fso signal, and this The result of addition is returned to this second register (1
It will be saved in 2). Furthermore, the meaning that the lower bits of this data are removed means that a shift operation is performed in the lower direction of M bits, and the phase data sent to the arithmetic circuit (6) by this operation has been added and averaged 2 ^M times. Become.

FIG. 2 shows a timing waveform chart of each part of FIG.
2A is the output sampling frequency fso signal, FIG. 2B is the output signal of the 1/2 ^M frequency divider (13), and FIG. 2C is the PLL circuit.
The output signal of (2), the output signal of the counter (9) in FIG. 2D, the output signal of the first register (10) in FIG. 2E, the output signal of the adder (11) in FIG. FIG. 2G shows the output signal of the second register (12).

It will be considered below that the phase data obtained by the configuration of FIG. 1 actually has a resolution accuracy of N + M bits.

The following consideration focuses on one cycle of 1 / (fso / 2 ^M ), and the count result is standardized and treated with 2 ^{M + N} as 1. If the data held in the first register (10) is Q _A , Is represented by Q _A. Where τ = 1 / (fso /
2 ^M ), that is, the period of the output pulse of the frequency divider (13), ε _i
Is the error of the counting result.

Next, hold data of the second register (12) in the process of being accumulated through the adder (11) is Q _Bn (n =
0, 1, 2, ..., 2 ^M -1) Becomes Where T is 2 in the second register (12)
^{The N + 2M} count value, P = 0 or 1, ie PT, is an overflow of the second register (12). Initial value of Q _Bn Q _B0
Is a true value; τ ′ ₀ , error: ε ′ ₀ , and Q _B0 = τ ′ ₀ + ε ′ ₀ (5), then equation (4) is expressed by equation (6). However τ _'n is Q
True value epsilon _'n of _Bn represents errors.

If you divide this into a true value and an error component, The (8) ε _'0 Focusing on error of expression is an error of the initial value in the count cycle. This is If set to It can be seen that there is a range in ε _'n of. (Where ε _i ma
x is the maximum value of ε _i . ) The hold data of the second register (12) is finally the lower M
Bits are truncated and equivalently, M bits of shift write (1/2 ^M averaging) are equivalently performed. The error of the phase data finally obtained by this operation is Therefore, it can be seen that it becomes 1 LSB or less of N + M bit length. Therefore, it was confirmed that the phase data obtained by the configuration of FIG. 1 realized the resolution accuracy of N + M bits.

In this case, for example, when N = 7 and M = 9, the resolution accuracy is 2 ^{7 + 9} = 2 ¹⁶ = 65536, which is 512 times that of the conventional resolution accuracy of FIG. 3, for example, 2 ⁷ = 128. .

Upper N + M of the hold data of the second register (12)
When the bits are supplied to the arithmetic circuit (6), the sampling frequency fs of the input sample sequence is input from the input sample sequence input terminal (7) in this arithmetic circuit (6) as in the conventional case.
i is a digital signal and is output as sampling frequency fs
The output sample sequence converted into o can be obtained.

As another embodiment, there is a means for replacing part or all of the configuration shown in FIG. 1 with a programmable arithmetic processor represented by a digital signal processor. In this case, the function and effect similar to those of the embodiment of FIG. 1 can be realized by appropriately setting the instruction sequence. Further, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention.

H Effect of the Invention According to the present invention, the sampling frequency f of the input sample sequence is
si can be converted into an output sample sequence of a desired sampling frequency fso as a digital signal as it is, and further, according to the present invention, there is an advantage that the resolution accuracy can be improved without changing the frequency multiplication ratio of the PLL circuit (2). .

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a sampling frequency converter of the present invention, FIG. 2 is a timing waveform diagram of FIG. 1, and FIG. 3 is a block diagram showing an example of a conventional sampling frequency converter. FIG. 5, FIG. 6, FIG. 6 and FIG. 7 are diagrams for explaining the sampling frequency converter, respectively. (1) is input sampling frequency signal input terminal, (2) is PL
L circuit, (4) output sampling frequency signal input terminal,
(6) is an arithmetic circuit, (9) is a counter, (10) is a first register, (11) is an adder, and (12) is a second register.

Claims (1)

[Claims] 1. A counter that uses a timing pulse whose frequency is an input sampling frequency as a clock input signal, and a timing pulse that is supplied with an output signal of the counter and that has a frequency obtained by dividing the output sampling frequency as a latch input signal. A first register; an adder that uses the hold data of the first register as one input signal; a second input that uses the output signal of the adder as a data input signal and the timing pulse that is the output sampling frequency as a latch input signal And the hold data of the second register is used as the other input signal of the adder, and the hold data of the second register is used as an output sample value calculation parameter or a control amount for sampling frequency conversion. A sampling frequency converter characterized by being used as.