JPH064651A - Image processor - Google Patents

Abstract

PURPOSE:To closely specify a processing area and to quicken a processing by having the values of scanning starting/finishing addresses at each horizontal scanning and controlling a scanning area by each horizontal scanning line. CONSTITUTION:An address switching circuit 23 switches an address for accessing a horizontal scanning starting address holding memory 21 and a horizontal scanning finishing address holding memory 22 to an address value from CPU or the count value of a vertical address counter 14 and a data buffer 24 temporarily holds data of the scanning starting/finishing address at each horizontal scanning line, which are sent from CPU. Then, at the time of the image processing, address data of starting/finishing the scanning is previously set to control the address switching circuit 23 to give a vertical address outputted from a vertical address counter 14 to the memories 21 and 22. After this, a dot clock 10 is given and the value of the horizontal address is made increment in synchronizing with it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for processing image data digitized and held in a memory by a dedicated processing circuit.

[0002]

2. Description of the Related Art FIG. 10 shows, for example, a magazine "OHM" 19
The article "Development and problems of visual inspection system by image recognition" published on pages 29-32 of the October 1986 issue, and Hideto Fujiwara et al. At the 42nd National Convention of the Information Processing Society of Japan (the first half of 1991). It is a block diagram which shows the conventional image processing apparatus shown by the published paper "high-speed image processing apparatus for surveillance." In the figure, 1 is an original image memory in which an original image to be image-processed is held, and 2 is a memory and a flip-flop for the purpose of executing only desired image processing, not program processing by a microcomputer. It is a processing circuit by dedicated hardware composed of elements such as. Reference numeral 3 denotes a processing result memory for holding the image processing result processed by the processing circuit, and reference numeral 4 holds the read address for reading the original image from the original image memory 1 and the image processing result in the processing result memory 3. Is an address generator that generates a write address for.

Next, the operation will be described. In the image processing in the processing circuit 2 formed by dedicated hardware,
As shown in FIG. 11, M × N pieces of one-dimensional image data stored in the original image memory 1 are displayed in M pixels in the horizontal direction and N pixels in the vertical direction.
Addresses in the horizontal and vertical directions are generated by the address generator 4 by treating them as two-dimensional data of pixels. When performing image processing in the processing circuit 2, in order to clarify which position in the two-dimensional space the pixel data to be processed corresponds to, the pixel data is read from the original image memory 1 completely at random. As shown in FIG. 11, for example, only the horizontal address is sequentially incremented from the upper left, and the rightmost pixel is read out, and then the vertical address is set to 1 as shown in FIG.
The same scan is performed by incrementing, the M × N pixel data is sequentially read, and the processing circuit 2 executes desired image processing.

FIG. 12 shows a configuration example of the address generator 4 in such a conventional image processing apparatus. In the figure, 10 is a dot clock input to the address generator 4, 11 is a horizontal address to be output, and 12 is a vertical address. 13 is the dot clock 10
Is a horizontal address counter that outputs a horizontal address 11 in synchronism with, and 14 is a vertical address counter that outputs a vertical address 12 in synchronization with a horizontal synchronization signal 19 described later. Reference numeral 15 is a horizontal size register that holds the number M of pixels in the horizontal direction, and 16 is a vertical size register that holds the pixel N in the vertical direction. Reference numeral 17 resets the count value of the horizontal address counter 13 and increments the count value of the vertical address counter 14 when the horizontal address 11 output from the horizontal address counter 13 is compared with the value of the horizontal size register 15 and becomes equal. Is a horizontal address comparator for outputting the horizontal synchronizing signal 19 for 18 is the same as the vertical address counter 1
4 is a vertical address comparator for comparing the vertical address 12 output from the No. 4 with the value of the vertical size register 16, and the horizontal synchronizing signal 19, the vertical address value 12 and the value of the vertical size are input to display on one screen. , And determines whether or not the last pixel address is output, and outputs the vertical synchronizing signal 20 for resetting the count value of the vertical address counter 14.

FIG. 13 shows a time chart of the operation of the address generator 4 thus constructed. The value of the horizontal address 11 output from the horizontal address counter 13 changes in synchronization with the rise of the dot clock 10, and the output value of the horizontal address 11 during one cycle of the dot clock 10 is
Is kept constant. The address generator 4 gives an address to the original image memory 1 and the processing result memory 3 during the period when the value of the horizontal address 11 is constant, reads the pixel value held in the original image memory 1 and processes it. 2, the processing circuit 2 performs desired image processing on the read pixel value and writes the image processing result in the processing result memory 3.

The value of the horizontal address 11 is normally incremented from 0 in synchronization with the dot clock 10.
The scanning is performed as indicated by the arrow. When the horizontal address comparator 17 detects that the value of the horizontal address 11 is the value indicating the right end, that is, "M-1", the horizontal synchronizing signal 19 being output is made significant for one dot clock. In FIG. 13, the significance of the horizontal synchronizing signal 19 is associated with the low level of the signal. The vertical address 12 is held constant while the horizontal address 11 is being incremented, and is incremented in synchronization with the change of the horizontal synchronizing signal 19. Similarly, by incrementing the horizontal address 11 and the vertical address 12 and detecting that the final pixel address (M-1, N-1) is output, the vertical address comparator 18 finishes scanning one screen. Tell the outside what you have done.

Therefore, in the image size shown in FIG. 11, M dot clocks are required to scan one horizontal line, and M × N dot clocks are required to scan the entire screen.

[0008]

Since the conventional image processing apparatus is configured as described above, since the horizontal pixel size is fixed, the original image can be scanned only in a predetermined rectangular area. Therefore, since the circumscribed quadrilateral area to be processed must be scanned, there is a problem that the time required for image processing becomes long.

The present invention has been made in order to solve the above problems, and an image processing apparatus which can perform efficient scanning according to the shape of a processing object and further detects an effective scanning area. Aim to get.

[0010]

According to the image processing apparatus of the present invention, the address generator has a function of controlling the scanning start address value and the scanning end address value for each horizontal scanning. The address generator is provided with a control processing circuit (hereinafter referred to as CPU) for designating the scanning start address value and the scanning end address value of each horizontal scanning line and for executing the overall control of the image processing apparatus.

Further, in the image processing apparatus according to the second aspect of the present invention, the processing circuit has a function of generating a next processing area signal capable of determining whether or not it is a processing area for the next processing from the image processing result. At the same time, based on the next processing area signal, a next processing scan address holding circuit for detecting and holding the scanning start address and the scanning end address for each horizontal scan for the target area of the next processing is provided.

Further, in the image processing apparatus according to the third aspect of the invention, the address generator is provided with the function of the next processing scan address holding circuit.

[0013]

According to the first aspect of the present invention, the image processing apparatus has the values of the scan start address and the scan end address for each horizontal scan, and controls the area to be scanned for each horizontal scan line to perform image processing. (EN) An image processing apparatus capable of finely designating an area for executing.

The image processing apparatus according to the second aspect of the present invention controls the scanning start address and the scanning end address for each horizontal scanning line in the next processing based on the next processing area signal from the processing circuit. As a result, it is unnecessary to set the image processing area in advance.

In the image processing apparatus according to the third aspect of the present invention, the address generator also has the function of the next processing scan address holding circuit, so that the image processing apparatus is downsized and the image processing is made efficient. .

[0016]

【Example】

Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the invention described in claim 1. In the figure, 1 is an original image memory, 2
Is a processing circuit by dedicated hardware, and 3 is a processing result memory, which is the same as or equivalent to those of the conventional one denoted by the same reference numeral in FIG. Further, 6 is that the scanning start address value and the scanning end address value can be controlled for each horizontal scanning.
Reference numeral 4 is an address generator different from 0, and reference numeral 7 is a CPU that executes overall control of the image processing apparatus, including designation of the scan start address value and the scan end address value.

FIG. 2 is a block diagram showing an example of the configuration of the address generator 6. In the figure, 10 is a dot clock, 11 is a horizontal address, 12 is a vertical address, 13 is a horizontal address counter, 14 is a vertical address counter, 16 is a vertical size register, 17 is a horizontal address comparator, 18 is a vertical address comparator, Reference numeral 19 is a horizontal synchronizing signal, and 20 is a vertical synchronizing signal, which are the same as or equivalent to those of the conventional one denoted by the same reference numeral in FIG.

Reference numeral 21 is a horizontal scanning start address holding memory for holding the value of the scanning start address for each horizontal scanning line, and 22 is a horizontal scanning end address for holding the value of the scanning end address for each horizontal direct scanning line. It is a holding memory. An address switching circuit 23 switches the address for accessing the horizontal scanning start address holding memory 21 and the horizontal scanning end address holding memory 22 to either the address value from the CPU 7 or the count value of the vertical address counter 14. Reference numeral 24 is a data buffer for temporarily holding the data of the scanning start address and the scanning end address for each horizontal scanning line sent from the CPU 7. Reference numeral 25 is a CPU interface circuit for interfacing signals with the CPU 7, and 26 is a C for accessing the horizontal scanning start address holding memory 21 and the horizontal scanning end address holding memory 22 from the CPU 7.
It is a PU address data line.

Next, the operation will be described. Now, consider that desired image processing is performed only within the polygonal area shown in FIG. 3A in the M × N original image memory area shown in FIG. Therefore, the area other than the polygon (A) in FIG. 3 is an area where image processing is unnecessary. At this time, the horizontal address is incremented in order from the smallest horizontal address on one horizontal scanning line whose vertical address is i.
Xis is the horizontal address value of the point (B) that enters inside the polygon (A), and the point (C) that goes out of the polygon (A) when the horizontal address is continuously incremented. Let Xie be the horizontal address value of
The following relation holds between ie and Xis.

0 ≦ Xis ≦ Xie ≦ M (0 ≦ i ≦ N−1) ‥‥‥‥‥‥‥‥‥‥ (1)

These N sets of horizontal scanning start address values X
C. is and the horizontal scanning end address value Xie in advance
The horizontal scanning start address holding memory 21 and the horizontal scanning end address holding memory 22 are set by the PU 7. That is, the address switching circuit 23 is switched, the address value received from the CPU interface circuit from the CPU 7 is sent to the horizontal scanning start address holding memory 21 and the horizontal scanning end address holding memory 22, and the CPU interface circuit 25 receives it. The scan start address data and the scan end address data for each scan line are set in the memories 21 and 22 via the data buffer 24. FIG. 4 shows a memory map of the horizontal scanning start address holding memory 21 and the horizontal scanning end address holding memory 22 at that time. Scan start address data or scan end address data is stored in the areas of the memories 21 and 22 corresponding to the horizontal scan lines.

In this way, the scanning start and end address data for each horizontal scanning line is stored in the horizontal scanning start address holding memory 21 and the horizontal scanning end address holding memory 22.
After setting to, the dot clock 10 is input to the address generator 6 and the horizontal address value generated when the vertical address value is i is controlled to be within the range of Xis to Xie. With, it becomes possible to scan only the target area. If this control is performed over all horizontal scanning lines, it becomes possible to efficiently scan only the designated image processing target area within one screen.

When performing image processing, the address switching circuit 23 is controlled after the scanning start and end address data is set in advance, and the vertical address 12 output from the vertical address counter 14 becomes the horizontal scanning start address. After being provided to the holding memory 21 and the horizontal scanning end address holding memory 22, the dot clock 10
give. As a result, the respective memories 21, 22
Outputs the corresponding scan start address and scan end address while scanning one horizontal scan line.
Therefore, when starting a new horizontal scan, the scan start address value is loaded into the horizontal address counter 13 from the scan start address holding memory 21, and the value of the horizontal address 11 is incremented in synchronization with the dot clock 10. . In the horizontal address comparator 17, the horizontal address 1
When the value of 1 is compared with the address value output from the horizontal scanning end address holding memory 22 and it is detected that it is the end address of the horizontal scanning, the vertical address counter 14
The horizontal synchronizing signal 19 for incrementing is output.

When the horizontal synchronizing signal 19 is generated, the value of the vertical address 12 is updated, so that a new horizontal scanning start address and a new horizontal scanning end address are output from the respective memories 21 and 22. The horizontal address counter 13 loads the horizontal scanning start address to generate a new horizontal scanning address 11. The end of the scanning of one screen unit is detected by the vertical address comparator 18 by the vertical address 12 and the output of the vertical size register 16 and the horizontal synchronizing signal 19 in the same manner as in the conventional case.
It is output as the vertical synchronizing signal 20.

A time chart of the operation of the address generator 6 is shown in FIG. The changing timing of each address and the synchronizing signal is the same as in the conventional case shown in FIG.
The number of clocks required for one horizontal scanning is not constant because it is defined by (Xie-Xis). From the formula (1), (X
ie-Xis) ≦ (M−1) is clear, and the number of clocks required for scanning one horizontal line is decreasing.

Example 2. Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a block diagram showing an embodiment of the invention described in claim 2. The same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. In the figure, reference numeral 8 denotes a processing circuit by dedicated hardware corresponding to the one denoted by reference numeral 2 in FIG. 1, but a next processing area signal for determining whether or not it is a processing area for the next processing according to the image processing result. It differs from that in that it has the function of outputting. A next processing scan address holding circuit 9 detects and holds the data of the next processing scan start address and the next processing scan end address based on the next processing area signal.

FIG. 7 is a block diagram showing an example of the configuration of the next processing scan address holding circuit 9. In the figure, 27 is a next processing area signal output from the processing circuit 8, and 28 is a write control circuit for generating write signals 29 and 30 based on the next processing area signal 27. Reference numeral 31 denotes a next processing scan start address holding memory which holds the value of the next processing scan start address under the control of the write signal 29,
A next processing scan end address holding memory 32 holds the value of the next processing scan end address under the control of the write signal 30. 33 is a memory 31 for holding the next processing scan start address.
And an address switching circuit for switching the address for accessing the next processing scan end address holding memory 32 to either the address value from the CPU 7 or the vertical address 12 from the address generator 6, and 34 indicates the start of the next processing scan. This is a data buffer that temporarily holds the values of the next processing scan start address and the next processing scan end address that are written / read in the address holding memory 31 and the next processing scan end address holding memory 32.

Next, the operation will be described. Here, in the first embodiment described above, the case where the processing area in the original image is known has been described, but in actual image processing, it is difficult to determine the processing area in advance. Also, 1
It is difficult to complete the desired image processing only by scanning the screen, and it is common to obtain the desired image processing result by performing different processing a plurality of times.

Here, FIG. 8 is an explanatory diagram showing the relationship between the scanning of the image data and the next processing area signal output from the processing circuit 2 in the second embodiment. Now, let us consider measuring the area of the hole inside the polygon in the original image shown in FIG. At this time, the original image is scanned from the upper left to the lower right for each horizontal scanning line to remove noise, and at the same time, the original image is binarized with a luminance value intermediate between the luminance values of the object and the background. From the processing circuit 2 to the next processing area signal 2
Output as 7. When the vertical address of the horizontal scanning line to be scanned is (D) or (E) shown in FIG. 8, the next processing area signal 27 indicates the shape of the object as shown in (a) and (b) of FIG. And so on. In addition, FIG.
Shows the case where the vertical address is (D) and (B) shows the case where the vertical address is (E). Here, the horizontal address value at the time (S) when the next processing area signal 27 rises for the first time in one horizontal scan is held as the next processing scan start address, and further when the last time it falls (G). If the horizontal address value of) can be held as the next processing scan end address, it is not necessary to scan the area without the target object in the area measurement of the next processing, so that the processing speed can be increased.

That is, in the processing of the horizontal scanning line at the vertical address (E) shown in FIG. 8B, the write control circuit 28 raises the next processing area signal 27 only when writing the next processing scan start address. The horizontal address 11 given by the address generator 6 only when
The write signal 29 is controlled so that the value of is written in the next processing scan start address holding memory 31. When writing the next processing scan end address, the contents of the next processing scan end address holding memory 32 are rewritten with the value of the horizontal address 11 provided from the address generator 6 when the next processing area signal 27 falls. The write signal 30 is controlled so that If such write signals 29 and 30 are generated by the write control circuit 28, the horizontal address 11 corresponding to (F ₁ ) and (F ₂ ) in FIG. However, when one horizontal scanning is completed, the value of the horizontal address 11 corresponding to (G) which is the true next processing scan end address value is the next processing scan end address holding memory 32. It is held in the start address holding memory 32.

When the scanning of all the pixels of one screen is completed, the CPU 7 switches the address switching circuit 33 of the next processing scan address holding circuit 9 and the next processing scan start address holding memory 31 via the data buffer 34. And the content of the next processing scan end address holding memory 32 is read out and sent to the address generator 6. Address generator 6
Then, by transferring the corresponding address values to the horizontal scanning start address holding memory 21 and the horizontal scanning end address holding memory 22, the screen scanning of the next process can be performed efficiently.

Example 3. In the second embodiment,
Although the values of the horizontal scan start address and horizontal scan end address and the values of the next process scan start address and the next process scan end address when performing certain image processing are shown in different memories, the same memory is used. May be used, which can reduce the number of parts and further increase the CPU.
Therefore, the transfer of the address value due to is unnecessary, and the processing efficiency can be improved. FIG. 9 is a block diagram showing an embodiment of such an invention described in claim 3. In the figure, reference numerals 35 and 36 denote the horizontal scanning start address holding memory 21 and the horizontal scanning end address holding memory 22, respectively, from the horizontal address counter 13 which is the value of the next processing scan start address or the next processing scan end address. Reference numeral 37 is a data buffer for writing the output horizontal address 11, and 37 is a latch circuit for holding the end address of one horizontal scan and giving it to the address comparator 17. A control circuit 38 controls each of the data buffers 35 and 36 and the latch circuit 37 to write the next processing start address or the next processing end address to the horizontal scanning start address holding memory 21 and the horizontal scanning end holding memory. Is.

Next, the operation will be described. As in the case of the second embodiment, the original image is read from the upper left of the original image for each horizontal scanning line, the processing circuit 2 performs the image processing, and the next processing area signal 27 is also output. In each horizontal scanning line, when scanning is started, the horizontal synchronizing signal 19 loads the scanning start address into the horizontal address counter 13 only once to start scanning, and then the address value is held in the horizontal address counter 13. Since the increment is performed, reading of the scan start address holding memory is not necessary in the same scan. Therefore, as in the case of the second embodiment, the control circuit 38 controls so that the horizontal address value at the first rising of the next processing area signal 27 is written via the buffer 35.

Similarly to the scan start address value, if the scan end address value is read only once at the start of each horizontal scan line and held in the latch circuit 37, the scan end address value can be maintained during the scan. The contents of the holding memory 22
Each time the next processing area signal 27 falls, the value of the horizontal address 11 at that time may be rewritten.

[0035]

As described above, according to the first aspect of the invention, since the scanning start address value and the scanning end address value can be controlled for each horizontal scanning, the horizontal scanning is performed for each horizontal scanning. It becomes possible to set the processing area,
It is possible to obtain an image processing apparatus capable of designating a processing area in a fine manner and accelerating the processing.

According to the second aspect of the invention, the scanning start address and the scanning end address for each horizontal scanning line in the next processing are controlled based on the next processing area signal from the processing circuit. Therefore, it is not necessary to set the image area in advance, and a series of image processing can be speeded up.

Further, according to the third aspect of the invention, the horizontal scanning start address holding memory and the horizontal scanning end address holding memory can directly store the scanning start address and the scanning end address for the next process. In addition, the device can be downsized and the price can be reduced, and the processing can be made more efficient to achieve high-speed processing.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of an address generator in the above embodiment.

FIG. 3 is an explanatory diagram showing a scanning method of image data in the above embodiment.

FIG. 4 is an explanatory diagram showing a memory map of a horizontal scanning start address holding memory and a horizontal scanning end address holding memory in the above embodiment.

FIG. 5 is a time chart showing the operation of the address generator in the above embodiment.

FIG. 6 is a block diagram showing a second embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration example of a next processing scan address holding circuit in the embodiment.

FIG. 8 is an explanatory diagram showing a scanning method of image data and a relationship between the scanning method and the next processing area signal in the embodiment.

FIG. 9 is a block diagram showing a configuration example of an address generator according to a third embodiment of the present invention.

FIG. 10 is a block diagram showing a conventional image processing apparatus.

FIG. 11 is an explanatory diagram showing a scanning method of the image data.

FIG. 12 is a block diagram showing a configuration example of an address generator in a conventional image processing apparatus.

FIG. 13 is a time chart showing the operation of the address generator in the conventional image processing apparatus.

[Explanation of symbols]

 1 original image memory 2 processing circuit 3 processing result memory 6 address generator 7 CPU (control processing circuit) 8 processing circuit 9 next processing scan address holding circuit 13 horizontal address counter 14 vertical address counter 17 horizontal address comparator 18 vertical address comparator 21 horizontal scan start address holding memory 22 horizontal scan end address holding memory 23 address switching circuit 28 write control circuit 31 next processing scan start address holding memory 32 next processing scan end address holding memory 33 address switching circuit 35, 36 data buffer 38 control circuit

Claims (3)

[Claims] 1. An original image memory for holding image data of a digitized original image, a processing circuit for executing predetermined image processing on the image data read from the original image memory, and the processing circuit. The processing result memory for holding the image processing result processed by the above, and the value of the scanning start address and the scanning end address for each horizontal scanning line when scanning the image data A control processing circuit that executes overall control, a horizontal scan start address holding memory that holds the value of the scan start address for each horizontal scan line, and a horizontal scan end that holds the value of the scan end address for each horizontal scan line Address holding memory, a horizontal address counter for incrementing the value of the scan start address held in the horizontal scan start address holding memory to generate a horizontal address Counter, a horizontal address comparator that detects the end of scanning of each horizontal scanning line from the horizontal address output from the horizontal address counter, a vertical address counter that generates a vertical address for designating each horizontal scanning line, and the vertical A vertical address comparator for detecting the scanning end of one screen of the image data from the vertical address output from the address counter, and an address for accessing the horizontal scanning start address holding memory and the horizontal scanning end address holding memory are provided. An image processing apparatus comprising: an address generator having an address switching circuit for switching between an address value from the control processing circuit and a count value of the vertical address counter. 2. The processing circuit has a function of determining whether or not it is a processing area for the next processing according to the result of the image processing and outputting a next processing area signal, and the next processing area from the processing circuit. A write control circuit that generates a write signal based on the signal, a next processing scan start address holding memory that holds the surface of the next processing scan start address according to the write signal from the write control circuit, and the write control A next processing scan end address holding memory that holds the value of the next processing scan end address according to the write signal from the circuit, and an address for accessing the next processing scan start address holding memory and the next processing scan end address holding memory, Next processing having an address switching circuit for switching to either the address value from the control processing circuit or the count value of the vertical address counter The image processing apparatus according to claim 1, further comprising a physical scanning address holding circuit. 3. The processing circuit has a function of determining whether or not it is a processing area for the next processing according to the image processing result and outputting a next processing area signal, and the address generator is provided with the horizontal signal. A data buffer for writing the horizontal address from the horizontal address counter, which is the next processing scan start address, to the scanning start address holding memory; and a next processing scan end address for the horizontal scanning end address holding memory. A data buffer for writing a horizontal address from the horizontal address counter, and a control circuit for controlling each data buffer based on a next processing area signal from the processing circuit are provided. Item 1. The image processing device according to item 1.