JPH0644795A - Redundant memory cell selection circuit - Google Patents

Abstract

PURPOSE:To provide the inexpensive selection circuit of the redundant memory cell with high yield by suppressing the increase of a chip area. CONSTITUTION:The redundant memory cell selection circuit is provided with eight memory cell blocks MCB0 to MCB7 having 1st and 2nd redundant memory cell groups and eight selection fuse circuit blocks FB00 to FB07. Respective selection fuse circuit blocks FB00, FB02, FB04, and FB06 can select 1st redundant word line groups RWL00, RWL10,..., RWL60 or RWL70 of any of the memory cell blocks MCB0-MCB7. On the other hand, respective selection fuse circuit blocks FB01, FB03, FB05 and FB07 can select the 2nd redundant word line groups RWLO1, RWL11,..., RWL61 or RWL71 of any of the memory cell blocks MCB0 to MCB7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundant memory cell selection circuit for repairing a defective memory cell group in a memory cell group by replacing it with a previously prepared redundant memory cell group.

[0002]

2. Description of the Related Art Recently, with the increase in capacity of semiconductor memory devices, the degree of integration and density of memory cell groups have increased. Therefore, the memory cell group may be defective in the manufacturing process. The defective memory cell group is replaced with a redundant memory cell group prepared in advance by a redundant memory cell selection circuit to repair the device as a good product. This is an essential technique for improving the device yield. Therefore, it is important to design a redundant memory cell selection circuit in which a sufficient number of redundant memory cell groups can be efficiently relieved in the manufacturing process in order to improve the device yield. Become.

A conventional redundant memory cell selection circuit will be described below with reference to FIGS. 17 and 18.

FIG. 17 shows a conventional redundant memory cell selection circuit, FIG. 18 shows a selection fuse circuit block FB100 in FIG. 17, and selection fuse circuit blocks FB101 to FB115 are selection fuse circuit blocks FB100. Is similar to.

17 and 18, MCB0 to MB
CB7 is a memory cell block, FB100 to FB115
Is a fuse circuit block for selection, RWL00, RWL0
1, RWL10, RWL11, ..., RWL70, RWL
71 is a redundant word line group, A0-A8, / A0- /
A8 is an address signal, SPE0, SPE1, R00, R
01, R10, R11, ..., R70, R71, / RA,
N01 is a signal, F00 to F11 are fuses, VCC is a power supply voltage, VSS is a ground voltage, QN00 to QN14 are N-channel type MOS transistors, and QP00 is a P-channel type MOS transistor.

In the conventional example, the redundant memory cell selection circuit is
Replace and repair a defective memory cell group of a plurality of memory cell groups formed at the intersections of word lines and bit lines configured in a lattice with a redundant memory cell group that is connected to a redundant word line group and prepared in advance. To do.

The redundant memory cell selection circuit has eight memory cell blocks MCB0 to MCB7 which are selected by the logic voltages of the address signals A6 to A8, respectively.

2 for each memory cell block
One redundant word line group is prepared. For example,
RWL20, R for the memory cell block MCB2
Two redundant word line groups of WL21 are provided. That is, 16 redundant word line groups are prepared as a whole.

In order to select these redundant word line groups, 16 fuse circuit blocks FB100 to FB for selection corresponding to the 16 redundant word line groups, respectively.
115 is provided. For example, when it is desired to use two redundant word line groups RWL20 and RWL21 of the memory cell block MCB2, the fuses corresponding to the address of the defective memory cell group in the fuse circuit blocks FB104 and FB105 for selection are cut off, respectively. Normally, the word line groups are replaced with redundant word line groups, and these redundant word line groups are used.

The detailed circuit operation of the conventional redundant memory cell selection circuit will be described below with reference to FIG. FIG. 18 shows a fuse circuit block FB100 for selection.
And shows a fuse circuit block FB101 for selection.
To FB115 are fuse circuit blocks for selection FB100
Is similar to.

First, the signal / RA becomes the logic voltage "Low (hereinafter referred to as L)", the P-channel MOS transistor QP00 is turned on, and the signal N01 becomes the logic voltage "High".
(Hereinafter referred to as H). ”After that, the signal / RA becomes the logical voltage“ H ”, and then the address signals A0 to A5, / A0 to / A5 which are initially all the logical voltage“ L ”.
Changes to the address of the selected defective memory cell group. Here, the address signals / A0 to / A5 are logic voltage signals which are the reverse of the address signals A0 to A5.

The address signals A0-A5 // A0
~ / A5 is an N-channel MOS transistor QN00-
Each of them is input to the gate of QN11, and half of the twelve N-channel type MOS transistors N00 to QN11, six of which are turned on.

At this time, among the fuses F00 to F11, six fuses corresponding to the address of the selected defective memory cell group are blown, and the memory cell block selection address of the memory cell block MCB0 is selected. Then, the signal N01 becomes the logical voltage "H" and the signal R00 becomes the logical voltage "L". Then, the signal SPE0 becomes the logical voltage "H", and the redundant word line group RWL00 is selected by the logical product signal of the address signal corresponding to the memory cell block selection address of the memory cell block MCB0 and the signal SPE0.

As described above, in the redundant memory cell selection circuit according to the conventional example, two redundant word line groups are prepared for each of the eight memory cell blocks.
2 × 8 = 16 selection fuse circuit blocks are required. Twelve fuses are required for one fuse circuit block for selection, and the total number of fuses is 12 × 16 = 192.

[0015]

However, in the redundant memory cell selection circuit according to the conventional example as described above, a redundant word line group and a selection fuse circuit block required for each memory cell block are prepared. Therefore, a large number of redundant word line groups and fuse circuit blocks for selection are required, which requires a large area in layout, which increases the area of the entire device and increases the cost per device. . Also,
Since the number of redundant word line groups, that is, the number of redundant memory cell groups, increases, the probability that the redundant memory cell group itself is defective increases, and the defective memory cell group is replaced with the redundant memory cell group to repair the device as a good product. However, there is a problem that the repair rate due to the redundant memory cell group is reduced.

The present invention has been made in view of the above, and an object thereof is to provide a redundant memory cell selection circuit which suppresses an increase in chip area and is inexpensive and has a high yield.

[0017]

In order to achieve the above object, the invention of claim 1 provides one redundant memory cell group among a plurality of redundant memory cell groups included in any of a plurality of memory cell blocks. By providing a selectable fuse circuit block that can be selected, any of the redundant memory cell groups can be selected by a number of selectable fuse circuit blocks that is less than the number of prepared redundant memory cell groups. It is a thing.

More specifically, the solution provided by the invention of claim 1 is directed to a redundant memory cell selection circuit, and a plurality of memory cell blocks each having a plurality of redundant memory cell groups, and one selection fuse circuit. And a redundancy memory cell group corresponding to the one selection fuse circuit block among the plurality of redundancy memory cell groups included in any one of the plurality of memory cell blocks. Is selectable.

The invention of claim 2 is specifically, claim 1.
In addition to the configuration of the present invention, a configuration including another fuse circuit block for selection capable of selecting any of the plurality of redundant memory cell groups included in any of the plurality of memory cell blocks is added.

The invention of claim 3 is, specifically, claim 1
In addition to the configuration of the invention described above, a plurality of the one fuse circuit block for selection is provided, and the total number of the one fuse circuit block for selection is smaller than the total number of the redundant memory cell groups.

The invention of claim 4 is, specifically, claim 1
In the configuration of the invention described above, each of the plurality of memory cell blocks has a plurality of memory cell groups, and the one fuse circuit for selection has a memory cell block selection address corresponding to each of the plurality of memory cell blocks. Any one of the memory cell group selection addresses corresponding to the plurality of memory cell groups in the memory cell block corresponding to the memory cell block selection address stored in the one fuse circuit for selection is stored. When the memory cell block selection address and the memory cell group selection address stored in the one fuse circuit block for selection are selected, the plurality of memory cell blocks corresponding to the memory cell block selection address have Memory cell group The memory cell group corresponding to the selected memory cell group selection address corresponds to the one selected fuse circuit block of the plurality of redundant memory cell groups included in the memory cell block corresponding to the selected memory cell block selection address. A configuration that can be replaced with the redundant memory cell group is added.

Specifically, the present invention is directed to a redundant memory cell selection circuit, and a plurality of memory cells each having M (M is a natural number) redundant memory cell groups and a plurality of memory cell groups. Block, first,
The second, third, ..., M−1, Mth selection fuse circuit blocks (N is a natural number satisfying 2 ≦ N ≦ M),
The total number of the first, second, third, ..., M−1, Mth selection fuse circuit blocks is L (L is a natural number),
Nth selection fuse circuit block (N is a natural number satisfying 1 ≦ N ≦ M), which is each of the first, second, third, ..., M−1, Mth selection fuse circuit blocks.
Can select any one of the N redundant memory cell groups corresponding to the N-th fuse circuit block for selection among the M redundant memory cell groups included in any of the plurality of memory cell blocks. Yes, the above Nth
The total number of fuse circuit blocks for selection is [{L × (M
−N + 1)} / M] −1 <K ≦ {L × (M−N + 1)}
Is less than or equal to K, which is a natural number that satisfies / M, and the first selection fuse circuit block stores any one of the memory cell block selection addresses corresponding to the plurality of memory cell blocks and the first selection fuse circuit block. Storing the memory cell block selection address stored in the selection fuse circuit block, the memory cell group selection address corresponding to the plurality of memory cell groups included in the memory cell block corresponding to the memory cell block selection address,
When the memory cell block selection address and the memory cell group selection address stored in the selection fuse circuit block of are selected, among the plurality of memory cell groups included in the memory cell block corresponding to the memory cell block selection address. The memory cell group corresponding to the memory cell group selection address corresponds to the first selection fuse circuit block of the M redundant memory cell groups included in the memory cell block corresponding to the memory cell block selection address. The configuration is such that it can be replaced with a redundant memory cell group.

To achieve the above object, the invention of claim 6 provides a selecting fuse circuit block capable of replacing a memory cell group of one memory cell block with a redundant memory cell group of another memory cell block. It is provided.

Specifically, the means for solving the problems according to the invention of claim 6 is directed to a redundant memory cell selection circuit, and a plurality of memory cell blocks each having a memory cell group and a redundant memory cell group, and the plurality of memories. And a fuse circuit block for selection capable of replacing a memory cell group included in any one of the cell blocks with a redundant memory cell group included in any of the memory cell blocks other than the memory cell block including the memory cell group. It is to be configured.

In order to achieve the above-mentioned object, the invention of claim 7 provides a dedicated block for a redundant memory cell having only a redundant memory cell group, and sets the memory cell group of the memory cell block to the redundant memory of the dedicated block for the redundant memory cell. A fuse circuit block for selection that can be replaced with a cell group is provided.

Specifically, the solving means devised by the invention of claim 7 is directed to a redundant memory cell selection circuit, and a plurality of memory cell blocks each having a memory cell group, and a redundant memory having only a redundant memory cell group. A configuration including a cell dedicated block and a selection fuse circuit block capable of replacing a memory cell group included in any one of the plurality of memory cell blocks with a redundant memory cell group included in the redundant memory cell dedicated block; To do.

In order to achieve the above-mentioned object, the invention of claim 8 is to provide a selecting fuse circuit block capable of replacing any one of the plurality of memory cell blocks together with the memory cell block.

Specifically, the means for solving the problems according to the invention of claim 8 is for a redundant memory cell selection circuit, wherein a plurality of first memory cell blocks each having a memory cell group and a first memory cell block having a memory cell group are provided. Two memory cell blocks and one selection fuse circuit block capable of replacing any of the plurality of first memory cell blocks with the second memory cell block. is there.

The invention of claim 9 is, specifically, claim 8
In the configuration of the invention described above, each of the plurality of first and second memory cell blocks has a redundant memory cell group,
It is possible to replace the memory cell group included in any of the plurality of first and second memory cell blocks with the redundant memory cell group included in the first or second memory cell block including the memory cell group. A configuration including a fuse circuit block for selection is added.

According to a tenth aspect of the present invention, specifically, in the configuration of the eighth aspect of the invention, a first memory which is replaced with the second memory cell block among the plurality of first memory cell blocks is provided. A configuration including another selection fuse circuit block capable of selecting a memory cell group included in a cell block as a redundant memory cell group is added.

The eleventh aspect of the invention is, specifically, in the configuration of the eighth aspect of the invention, wherein each of the plurality of first memory cell blocks has a bit line and a word line. Of the memory cell blocks of the first memory cell block to be replaced with the second memory cell block, the bit line and the word line of the first memory cell block have the same potential.

In order to achieve the above object, the invention of claim 12 provides a fuse circuit block for selection which can cancel the stored memory cell group selection address.

Specifically, the solving means devised by the invention of claim 12 is directed to a redundant memory cell selection circuit, and comprises a plurality of memory cell groups, a plurality of redundant memory cell groups,
Any one of the plurality of memory cell group selection addresses respectively corresponding to the plurality of memory cell groups is stored, and the memory cell group corresponding to the stored memory cell group selection address is stored in one of the plurality of redundant memory cell groups. A selection fuse circuit block to be replaced is provided, and the selection fuse circuit block is configured to be able to cancel the stored memory cell group selection address.

[0034]

According to the configurations of claims 1, 3 and 4, one selection fuse circuit block is one of a plurality of redundant memory cell groups included in any of a plurality of memory cell blocks. A redundant memory cell group can be selected, that is, one can be selected from the same number of redundant memory cell groups as the number of memory cell blocks. As a result, it becomes possible to select any one of all the redundant memory cell groups with the number of selection fuse circuit blocks smaller than the number of prepared redundant memory cell groups. Therefore, the total area of the fuse circuit block for selection which requires a large layout area can be reduced without reducing the number of redundant memory cell groups, that is, without lowering the repair rate by the redundant memory cell groups. The area of the entire device can be reduced.

According to the second and fifth aspects of the invention, another selection fuse circuit block, second, third and third fuse circuit blocks are provided.
..., the M-th and M-th fuse circuit blocks for selection are
It is possible to select one from two or more redundant memory cell groups of the plurality of redundant memory cell groups included in any of the plurality of memory cell blocks.
Therefore, it is possible to increase the degree of freedom of relief by the redundant memory cell group.

According to the configuration of the sixth aspect of the present invention, in the fuse circuit for selection, the redundant memory cell in which the memory cell group of the one memory cell block is included in any of the memory cell blocks other than the one memory cell block. It can be replaced with a group. This allows
Since the total number of redundant memory cell groups and the number of selection fuse circuit blocks can be reduced without lowering the degree of relief by the redundant memory cell groups, the area of the entire device can be reduced. In addition, the repair rate by the redundant memory cell group can be improved.

According to the configuration of the seventh aspect of the present invention, the fuse circuit block for selection can replace the memory cell group of any of the plurality of memory cell blocks with the redundant memory cell group of the dedicated block for the redundant memory cells. . As a result, the total number of redundant memory cell groups and the number of selection fuse circuit blocks can be reduced, and the total area of the device can be reduced.
Further, the number of relievable memory cell groups in each memory cell block can be increased, and the degree of freedom of relieving by the redundant memory cell groups can be increased.

According to the structure of the eighth aspect of the invention, one fuse circuit block for selection can replace any one of the plurality of first memory cell blocks with the second memory cell block. Thereby, the memory cell block having the defective portion can be replaced with the second memory cell block together with the memory cell block.

According to the configuration of the ninth aspect of the invention, the other fuse circuit block for selection can replace the memory cell group with the redundant memory cell group in the memory cell block to which the memory cell group belongs. Therefore, a defective memory cell block can be replaced for each memory cell block, and a defective memory cell group can be replaced with a redundant memory cell group in each memory cell block.

According to the structure of the tenth aspect of the present invention, the other fuse circuit block for selection can select the memory cell group of the first memory cell block replaced with the second memory cell block as the redundant memory cell group. is there. Therefore, the defective memory cell block can be replaced for each memory cell block, and the defective memory cell group in each memory cell block can be replaced with the memory cell group in the replaced defective memory cell block. .

According to the eleventh aspect of the invention, the redundant memory cell selection circuit can make the bit line and the word line of the first memory cell block replaced with the second memory cell block the same potential. As a result, in the case where a defect in which the bit line and the word line of the memory cell block are short-circuited occurs in the manufacturing process, the memory cell block in which such a defect occurs can be replaced with the memory cell block. By making the potentials of the bit line and the word line in the defective memory cell block the same, it is possible to remedy the power supply current defect.

According to the structure of the twelfth aspect of the invention, the fuse circuit block for selection can cancel the stored memory cell group selection address. Thus, when the redundant memory cell group replaced with the defective memory cell group is defective, the memory cell group selection address corresponding to the defective memory cell group stored in the selection fuse circuit block is canceled,
By newly storing the memory cell group selection address of the defective memory cell group in the other fuse circuit block for selection, the defective memory cell group can be replaced with another redundant memory cell group. Therefore, the repair rate by the redundant memory cell group can be significantly improved.

[0043]

【Example】

(First Embodiment) A redundant memory cell selection circuit according to the first embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows a redundant memory cell selection circuit according to the first embodiment, FIG. 2 shows a selection fuse circuit block FB00 in FIG. 1, and selection fuse circuit blocks FB01 to FB07 are for selection. It is similar to the fuse circuit block FB00.

1 and 2, MCB0 to MCB
7 is a memory cell block, FB00 to FB07 are selection fuse circuit blocks, and RWL00, RWL01, RW
, LWL70, RWL71 are redundant word line groups, A0-A8, / A0- / A8 are address signals, SPE0, SPE1, R00, R01, R.
10, R11, ..., R30, R31, / RA, N01 are signals, F00 to F17 are fuses, VCC is a power supply voltage,
VSS is a ground voltage, QN00 to QN17 are N-channel type MOS transistors, and QP00 is a P-channel type MOS transistor.

In the first embodiment, the redundant memory cell selection circuit is defective in the plurality of memory cell groups formed at the intersections of the word lines and the bit lines formed in a grid pattern, as in the conventional example. The memory cell group is replaced with a redundant memory cell group which is connected to the redundant word line group and prepared in advance for repair.

The redundant memory cell selection circuit includes eight memory cell blocks MCB0 to MCB7 (hereinafter, memory cell blocks will be collectively referred to as MCBs) selected by logic voltages of address signals A6 to A8. . Redundant word line groups RWL00 to RWL71 (hereinafter, the redundant word line groups are collectively referred to as RWL) are prepared for the memory cell blocks MCB0 to MCB7, and one memory cell block includes two redundant word lines. Have a group. For example, two redundant word line groups RW are provided for the memory cell block MCB2.
L20 and RWL21 are provided. That is, 16 redundant word line groups RWL are prepared as a whole. And 16 redundant word line groups RWL
8 selection fuse circuit blocks F for selecting
B00 to FB07 are provided. For example, the first set of redundant word line groups R of the memory cell block MCB2
When it is desired to use WL20 and the second set of redundant word line groups RWL21, the selection fuse circuit block F
In B00 and FB01, the fuses corresponding to the addresses of the defective memory cell group are cut off. As a result, the normal word line groups are respectively replaced by the redundant word line groups, and these redundant word line groups are used.

The first set of redundant word line groups RWL00, RWL1 which one of the memory cell blocks MCB has.
When using 0, RWL20, ..., RWL60 or RWL70, the selection fuse circuit blocks FB00, F
Any one of B02, FB04 and FB06 is used. The second set of redundant word line groups RWL01, RWL11, which one of the memory cell blocks MCB has
When using RWL21, ..., RWL61 or RWL71, the selection fuse circuit blocks FB01, FB0
Any one of 3, FB05 and FB07 is used.

Four selection fuse circuit blocks are prepared for the eight first redundant word line groups, and four selection fuse circuit blocks are prepared for the eight second redundant word line groups. Is being prepared.

Normally, a defective memory cell group often occurs in a plurality of word line groups at one location (one memory cell block). It is rare that a plurality of word line groups become defective in each of all the memory cell blocks MCB. The number of defects in the word line group is at most 8 in the entire device. Therefore, as in the conventional example, 8
Eight select fuse circuit blocks are prepared for one first set of redundant word line groups, and eight select fuse circuit blocks are prepared for eight second set of redundant word line groups, that is, a total of It is not necessary to prepare 16 fuse circuit blocks for selection, and repair can be performed by the redundant memory cell group only by preparing 8 fuse circuit blocks for selection.

As described above, two redundant word line groups are prepared for each memory cell block, which is the same as the conventional example, but one redundant word line group can be used as a whole.
The number is limited to 8 instead of 6. As a result, the number of selection fuse circuit blocks is reduced without lowering the repair rate of the redundant memory cell group in the device.

The detailed circuit operation of the redundant memory cell selection circuit according to the first embodiment will be described below with reference to FIG. FIG. 2 shows the selection fuse circuit block FB00, and includes the selection fuse circuit blocks FB01 to FB01-F.
B07 is similar to the fuse circuit block for selection FB00.

In FIG. 2, first, the signal / RA becomes the logical voltage "L", and the P-channel MOS transistor QP
00 is turned on, and the signal N01 becomes the logic voltage “H”. After that, the signal / RA becomes the logic voltage "H", and then all the address signals A0 to A0 which are initially the logic voltage "L".
A8, / A0 to / A8 change to the address of the selected defective memory cell group. Where address signal /
A0- / A8 are logic voltage signals which are the reverse of the address signals A0-A8.

Address signals A0-A8, / A0- / A8
Are N-channel MOS transistors QN00 to QN17
18 N-channel type M input to each gate
Nine of the half of the OS transistors are turned on.

At this time, among the fuses F00 to F11, six fuses corresponding to the address of the selected defective memory cell group are cut, and the memory cell block selection of the fuses F12 to F17 is performed. If the three fuses corresponding to the address are blown,
The signal N01 becomes the logic voltage "H", and the signal R00 becomes the logic voltage "L". Then, the signal SPE0 becomes the logic voltage "H", and the logical product signal of the signal SPE0 and the address signal corresponding to the memory cell block selection address causes the redundancy of the first set of memory cell blocks corresponding to the memory cell block selection address. A word line group is selected.

The difference between the first embodiment and the conventional example is that a fuse corresponding to a memory cell block selection address is added to the selection fuse circuit block.

As described above, in the redundant memory cell selection circuit according to the first embodiment, two redundant word line groups are prepared for each of the eight memory cell blocks. Four fuse circuit blocks for selection are prepared for each of the two redundant word line groups. That is, 2 × 4 = 8 selection fuse circuit blocks are provided. Eighteen fuses are required in one fuse circuit block for selection, and the total number of fuses is 18 × 8 = 144. This is reduced to 75% compared to the conventional example of 192 lines.

A feature of the redundant memory cell selection circuit of the first embodiment is that the number of redundant word line groups is small, that is, the number of redundant memory cell groups is not small. Therefore, it is possible to select any of the redundant memory cell groups with the number of selection fuse circuit blocks that is smaller than the number of prepared redundant memory cell groups without substantially lowering the repair rate by the redundant memory cell groups. It will be possible. As a result, the total area of the selection fuse circuit block can be reduced.

(Second Embodiment) A redundant memory cell selection circuit according to a second embodiment of the present invention will be described below with reference to FIGS. 3 and 4.

FIG. 3 shows the redundant memory cell selection circuit according to the second embodiment, FIG. 4 shows the selection fuse circuit block FB11 in FIG. 3, and the selection fuse circuit blocks FB13, FB15, FB17 are This is the same as the selection fuse circuit block FB11.

3 and 4, MCB0 to MCB
7 is a memory cell block, FB00, FB02, FB0
4, FB06, FB11, FB13, FB15, FB1
7 is a fuse circuit block for selection, RWL00, RWL
01, RWL10, RWL11, ..., RWL70, RW
L71 is a redundant word line group, A0 to A8, / A0
/ A8 is an address signal, SPE0, SPE1, R00,
R01, R10, R11, R20, R21, R30, R
31, R40, R50, R60, R70, AALL, /
RA, N01, N02, N20, N21, N22 are signals, F00-F17, F20 are fuses, VCC is a power supply voltage, VSS is a ground voltage, QN00-QN17, QN2.
0 is an N channel type MOS transistor, QP00, QP
20 is a P-channel type MOS transistor.

Fuse circuit blocks FB00, F for selection
B02, FB04, and FB06 are similar to the fuse circuit block for selection of the redundant memory cell selection circuit according to the first embodiment shown in FIG.

In the second embodiment, as in the conventional example, the redundant memory cell selection circuit has a defect in the plurality of memory cell groups formed at the intersections of the word lines and the bit lines which are arranged in a grid pattern. The memory cell group is replaced with a redundant memory cell group connected to the redundant word line group and prepared in advance for repair.

The redundant memory cell selection circuit includes eight memory cell blocks MCB0 to MCB7 selected by the logic voltage of the address signals A6 to A8. Two redundant word line groups are prepared for each memory cell block. For example, the memory cell block MCB
2 for two redundant word line groups RWL20,
RWL21 is provided. In other words, 1 as a whole
Six redundant word line groups RWL are prepared.
Then, in order to select 16 redundant word line groups RWL, eight selection fuse circuit blocks FB00,
FB02, FB04, FB06, FB11, FB13,
FB15 and FB17 are provided. For example, two redundant word line groups R of the memory cell block MCB2
When it is desired to use the WL20 and RWL21, in the fuse circuit blocks FB00 and FB11 for selection, the fuses corresponding to the address of the defective memory cell group are cut, respectively, and the normal word line group is replaced with the redundant word line group. These redundant word line groups are used. The first set of redundant word line groups RWL00, RWL10, RWL20, ..., RWL included in one of the memory cell blocks MCB
When 60 or RWL70 is used, the selection fuse circuit blocks FB00, FB02, FB04, FB06,
Any one of FB11, FB13, FB15 and FB17 is used. Second set of redundant word line group RWL0 included in one of the memory cell blocks MCB
1, RWL11, RWL21, ..., RWL61 or R
When using WL71, any one of the selection fuse circuit blocks FB11, FB13, FB15 and FB17 is used. All eight fuse circuit blocks for selection can be used to select one redundant word line group of the first set. Specific 4 of the 8 fuse circuit blocks for selection can be used for selecting one redundant word line group of the second set.

As described in the first embodiment, usually, a defective memory cell group often occurs in a plurality of word line groups at one place. It is rare that a plurality of word line groups become defective in each of all the memory cell blocks MCB. Therefore, the redundant word line group RW
Even if the total number of selection fuse circuit blocks is smaller than the total number of L, the repair rate by the redundant memory cell group does not decrease.

Further, in the second embodiment, as compared with the first embodiment, all eight fuse circuit blocks for selection can be used for selecting each of the redundant word line groups of the first set.

The detailed circuit operation of the redundant memory cell selection circuit according to the second embodiment will be described below with reference to FIG. FIG. 4 shows a fuse circuit block FB11 for selection.
Showing the selection fuse circuit block FB13,
FB15 and FB17 are selection fuse circuit blocks FB
The same as 11.

In FIG. 4, first, the signal / RA becomes the logical voltage "L", and the P-channel type MOS transistor QP.
00 is turned on, and the signal N01 becomes the logic voltage “H”. After that, the signal / RA becomes the logic voltage "H", and then all the address signals A0 to A0 which are initially the logic voltage "L".
A8, / A0 to / A8 change to the address of the selected defective memory cell group. Where address signal /
A0- / A8 are logic voltage signals which are the reverse of the address signals A0-A8.

Address signals A0-A8, / A0- / A8
Are N-channel MOS transistors QN00 to QN17
18 N-channel type M input to each gate
9 of half of the OS transistors QN00 to QN17
The pieces turn on.

At this time, among the fuses F00 to F11, six fuses corresponding to the address of the selected defective memory cell group are cut, and the memory cell block selection of the fuses F12 to F17 is performed. If the three fuses corresponding to the address are blown,
The signal N01 becomes the logic voltage "H", and the signal N02 becomes the logic voltage "L".

The circuit for deciding which of the first and second redundant word line groups is to be selected is
First, the signal / RA becomes the logical voltage "L", the P-channel MOS transistor QP20 turns on, and the signal N20 becomes the logical voltage "H". Thereafter, the signal / RA becomes the logic voltage "H", and then the signal AALL, which is initially the logic voltage "L", becomes the logic voltage "H". by this,
The N-channel MOS transistor QN20 turns on.

At this time, if the fuse F20 is not blown, the signal N20 becomes the logic voltage "L". As a result, the signal N21 becomes the logical voltage "H", and the signal N22
Becomes the logic voltage "L", and the signal R01 becomes the logic voltage "L".
On the other hand, the signal R40 becomes the logical voltage "H". Therefore, the signal SPE0 becomes the logic voltage "H", and the signal SPE0
The first AND of the memory cell block corresponding to the memory cell block selection address is generated by the logical product signal of PE0 and the address signal corresponding to the memory cell block selection address.
A set of redundant word line groups is selected.

If the fuse F20 is blown, the signal N20 remains at the logic voltage "H" and the signal N21
Becomes the logic voltage "L", and the signal N22 becomes the logic voltage "H".
Becomes As a result, the signal R01 becomes the logic voltage "H", while the signal R40 becomes the logic voltage "L", and the signal SP
E1 becomes the logic voltage "H". The logical product signal of the signal SPE1 and the address signal corresponding to the memory cell block selection address selects the second redundant word line group of the memory cell block corresponding to the memory cell block selection address.

As described above, in the redundant memory cell selection circuit according to the second embodiment, eight memory cell blocks MC
Two redundant word line groups are prepared for each B. The redundant memory cell selection circuit includes four selection fuse circuit blocks that can select only the first set of redundant word line groups and four selection fuses that can select both the first and second sets of redundant word line groups. And a circuit block. Eighteen fuses are required for one fuse circuit block for selection that can select only the first set of redundant word line groups. First set and second
19 fuses are required for one fuse circuit block for selection which can select either redundant word line group of the set. Therefore, the total number of fuses in the redundant memory cell selection circuit is 18 × 4 + 19 × 4 = 148. This is 77% less than the conventional 192 lines.

Here, in each memory cell block,
Assuming that the first redundant word line group to be used must be from the first group of redundant word line groups, the number of fuse circuit blocks for selection that can select either the first group of redundant word line groups or the second group of redundant word line groups. Is equal to or less than the number of selection fuse circuit blocks that can select only the first set of redundant word line groups.

For example, the total number of fuse circuit blocks for selection is 24, and the total number of redundant memory cell groups in one memory cell block is 4. When the third group of redundant memory cell groups is selected from among these, the first group and the second group of redundant memory cell groups have already been selected and used, so that from the first group in one memory cell block. The number of selection fuse circuit blocks that can select any redundant memory cell group up to the third set is the same as the selection fuse circuit block that can select any redundant memory cell group from the first set to the second set in one memory cell block. Less than half the number of blocks is sufficient.

Considering in this way, the number of selecting fuse circuit blocks that can select any of the first to third redundant memory cell groups in one memory cell block is 24 × (4-3 + 1) / 4 = 12 or less is sufficient.

Generally speaking, the total number of fuse circuit blocks for selection is L (L is a natural number), and the total number of redundant memory cell groups in one memory cell block is M (M
Is a natural number), the first of one memory cell block
It is sufficient that the number of selection fuse circuit blocks that can select any redundant memory cell group from the set to the Nth set (N is a natural number from 2 to M) is L × (M−N + 1) / M or less.

The feature of the redundant memory cell selection circuit according to the second embodiment is that the redundancy memory cell group has almost the same repair rate without reducing the number of redundant memory cell groups as in the first embodiment. This means that it is possible to select any of the redundant memory cell groups with the number of selection fuse circuit blocks smaller than the number of prepared redundant memory cell groups without lowering. Therefore, the total area of the selection fuse circuit block can be reduced. Further, as compared with the first embodiment, all eight fuse circuit blocks for selection can be used for selecting the first set of redundant word line groups, thereby increasing the degree of freedom of repair by the redundant memory cell group. Has been.

(Third Embodiment) A redundant memory cell selection circuit according to a third embodiment of the present invention will be described below with reference to FIGS.
7 and FIG. 7.

FIG. 5 shows a redundant memory cell selection circuit according to the third embodiment, FIG. 6 shows a selection fuse circuit block FB20 in FIG. 5, and selection fuse circuit blocks FB21 to FB27 are for selection. This is the same as the fuse circuit block FB20, and FIG. 7 shows the address conversion circuit block ATC61 in FIG. 5, and the address conversion circuit blocks ATC71 and ATC81.
Is similar to the address conversion circuit block ATC61.

In FIGS. 5, 6 and 7, MCB0-
MCB7 is a memory cell block, FB20 to FB27 are selection fuse circuit blocks, and RWL00 and RWL1.
0, ..., RWL70 are redundant word line groups, ATC6
1, ATC71, ATC81 are address conversion circuit blocks, A0-A8, / A0- / A8 are address signals, A6
R, A7R, A8R, / A6R, / A7R, / A8R are internal conversion address signals, SPE0, R00 to R07, I
NVA60 to INVA67, INVA70 to INVA7
7, INVA80 to INVA87, INVA6A, IN
VA7A, INVA8A, / RA, AALL, N01,
N21 to N23 and N30 are signals, F00 to F20 are fuses, VCC is a power supply voltage, VSS is a ground voltage, and QN and Q.
N00 to QN20 are N-channel MOS transistors,
QP and QP00 to QP03 are P-channel type MOS transistors.

In the third embodiment, the redundant memory cell selection circuit has a defective memory cell group among a plurality of memory cell groups formed at the intersections of the word lines and the bit lines arranged in a grid pattern, as in the conventional example. The memory cell group is replaced with a redundant memory cell group connected to the redundant word line group and prepared in advance for repair.

The redundant memory cell selection circuit includes memory cell blocks MCB0 to MCB7 selected by the logical voltage of the address signals A6 to A8. Each of the memory cell blocks MCB0 to MCB7 has a normal memory cell group and a redundant memory cell group connected to the redundant word line group. Memory cell block M
Redundant word line group RWL for CB0 to MCB7
00 to RWL70 are provided respectively. Therefore,
Eight redundant word line groups RWL are provided in total. Each of the redundant word line groups RWL00 to RWL70 can be replaced with any defective memory cell group in any memory cell block. For example, when it is desired to replace the defective memory cell group in the memory cell block MCB0 with the redundant memory cell group connected to the redundant word line group RWL50 in the memory cell block MCB5, for example, FIG.
In the selecting fuse circuit block FB20, 18 fuses F00 to F17 are selected so that the address of the defective memory cell group in the memory cell block MCB0 is selected.
Half of the nine are cut. In the memory cell block selection address of the memory cell block MCB0, the address signal A6 is "0", A7 is "0", and A8 is "0". In the selected address of MCB5, the address signal A6 is "1", A7 is "0", and A8 is "1". In order to switch the selection of the memory cell block from MCB0 to MCB5, different selection address signals A6 to A8 corresponding to the memory cell blocks MCB0 and MCB5 (A6 and A8, which are different logic voltages) are used. The fuses F18 and F20 respectively corresponding to and are cut off.

The circuit operation of the redundant memory cell selection circuit according to the third embodiment will be described below. FIG. 6 shows the selection fuse circuit block FB20, and the selection fuse circuit blocks FB21 to FB27 are the same as the selection fuse circuit block FB20.

In FIG. 6, first, when the signal / RA is set to the logic voltage "L", the P-channel MOS transistors QP00 to QP03 are turned on, and the signals N01 and N21 to N are set.
23 becomes the logic voltage "H". After that, the signal / RA becomes the logic voltage "H", and then the address signals A0 to A
A selected address signal of 8, / A0 to / A8 is output from an address buffer included in the device, for example. Here, the address signals / A0 to / A8 are logic voltage signals which are the reverse of the address signals A0 to A8.

Address signals A0-A8, / A0- / A8
Are N-channel MOS transistors QN00 to QN17
18 N-channel type M input to each gate
9 of half of the OS transistors QN00 to QN17
Only one turns on.

At this time, if all nine fuses corresponding to the selected address are blown, the signal N0
1 becomes the logic voltage "H", and the signal R00 is held in the state of the logic voltage "L".

The signal AALL is an address signal A0-A.
8, / A0 to / A8 are determined and selected, and become a logical voltage "H" at the same time. If the fuse F18 and the fuse F20 are disconnected, the signal N21 and the signal N23 are output.
Becomes the logic voltage "H", and the signal N22 becomes the logic voltage "L".
Becomes Further, as described above, since the signal N01 is the logical voltage “H”, the signals INVA60 and INVA80
Becomes a logical voltage "L", and the signal INVA70 becomes a logical voltage "H".

Then, the signal INVA60 having the logic voltage "L" is input to the address conversion circuit block ATC61 corresponding to the address signal A6 shown in FIG. 7, and the internal address signal A6R becomes the inverse logic signal of the address signal A6.
The internal address signal / A6R is the inverse logic signal of the address signal / A6. Similarly, the address conversion circuit blocks ATC71, A corresponding to the address signals A7, A8, respectively.
A signal INVA70 having a logic voltage "H" and a signal INVA80 having a logic voltage "L" are input to the TC81, the internal address signal A7R becomes the same logic signal as the address signal A7, and the internal address signal / A7R becomes the address signal. / A7 becomes the same logic signal and internal address signal A
8R is the inverse logic signal of the address signal A8, and the internal address signal / A8R is the inverse logic signal of the address signal / A8.

In this way, the memory cell block MC
It becomes possible to replace the defective memory cell group B0 with the redundant memory cell group connected to the redundant word line group RWL50 of the memory cell block MCB5.

As described above, in the redundant memory cell selection circuit according to the third embodiment, eight selection fuse circuit blocks are prepared, and 21 fuses are required for one selection fuse circuit block. , The total number of fuses is 2
1 × 8 = 168. This is a decrease of 87.5% from the conventional 192 lines (12 lines × 16).

The feature of the redundant memory cell selection circuit according to the third embodiment is that the total number of redundant word line groups and the number of selection fuse circuit blocks can be reduced and the total area of the device can be reduced. This means that the number of repairable memory cell groups in the memory cell block can be increased from the conventional two to eight, and the degree of freedom of repair by the redundant memory cell group can be increased.

(Fourth Embodiment) A redundant memory cell selection circuit according to the fourth embodiment of the present invention will be described below with reference to FIGS.

FIG. 8 shows a redundant memory cell selection circuit according to the fourth embodiment, FIG. 12 shows a selection fuse circuit block FB30 in FIG. 8, and selection fuse circuit blocks FB31 to FB37 are for selection. It is similar to the fuse circuit block 30.

8 and 12, MCB0 to MCB
B7 is a memory cell block, MCBR is a redundant memory cell dedicated block, FB30 to FB37 are selection fuse circuit blocks, and RWL00, RWL10, ..., RWL70.
Is a redundant word line group, A0-A8, / A0- / A8
Is an address signal, SPE0 to SPE7, R30 to R3
7, / RA and N01 are signals, F00 to F17 are fuses, VCC is a power supply voltage, VSS is a ground voltage, and QN00 to QN00.
QN17 is an N-channel type MOS transistor, QP00
Is a P-channel MOS transistor.

In the fourth embodiment, the redundant memory cell selection circuit preliminarily sets defective memory cell groups out of a plurality of memory cell groups formed at intersections of word lines and bit lines arranged in a grid pattern. The redundant memory cell group in the prepared redundant memory cell dedicated block MCBR is replaced and repaired.

The redundant memory cell selection circuit includes eight memory cell blocks MCB0 to MCB7 selected by the logical voltage of address signals A6 to A8 and a redundant memory cell dedicated block MCBR.

Here, for example, the memory cell block MC
When it is desired to replace the defective memory cell group of B3 with the redundant word line group RWL00, 1 is selected in the fuse circuit block for selection so that the address of the defective memory cell group of the memory cell block MCB3 is selected.
Half of the eight fuses F00 to F17, nine, are blown.

The circuit operation of the redundant memory cell selection circuit according to the fourth embodiment will be described below. FIG. 12 shows the selection fuse circuit block FB30, and the selection fuse circuit blocks FB31 to FB37 are the same as the selection fuse circuit block 30.

In FIG. 12, first, the signal / RA becomes the logical voltage "L", and the P-channel MOS transistor Q
P00 turns on, and the signal N01 becomes the logic voltage "H".
After that, the signal / RA becomes the logical voltage "H", and then the address signals A0 to A8 and / A0 to / A8 output the selected address. Here, the address signals / A0 to / A
Reference numeral 8 is a logic voltage signal which is the reverse of the address signals A0 to A8.

Address signals A0-A8, / A0- / A8
Are N-channel MOS transistors QN00 to QN17
18 N-channel type M input to each gate
9 of half of the OS transistors QN00 to QN17
One turns on.

At this time, if all nine fuses corresponding to the selected address are blown, the signal N0
1 becomes the logic voltage "H", and the signal R30 is held in the state of the logic voltage "L".

In this way, the memory cell block MC
It becomes possible to replace the defective memory cell group of B3 with the redundant memory cell group connected to the redundant word line group RWL00 of the redundant memory cell dedicated block MCBR.

As described above, in the redundant memory cell selection circuit according to the fourth embodiment, eight selection fuse circuit blocks are prepared and 18 fuses are required for one selection fuse circuit block. , The total number of fuses is 1
8 × 8 = 144 lines. 7 compared to 192 in the conventional example
It is reduced to 5%.

Similar to the third embodiment, the redundant memory cell selection circuit according to the fourth embodiment is characterized in that the total number of redundant word line groups and the number of selection fuse circuit blocks are reduced. This means that the total area can be reduced, and the number of relievable memory cell groups in each memory cell block can be increased from the conventional two to eight to increase the degree of freedom of relieving by the redundant memory cell groups.

(Fifth Embodiment) A redundant memory cell selection circuit according to a fifth embodiment of the present invention will be described below with reference to FIGS.
This will be described with reference to FIGS.

FIG. 9 shows a redundant memory cell selection circuit according to the fifth embodiment, FIG. 13 shows a selection fuse circuit block FB40 in FIG. 9, and FIG. 14 shows an address conversion circuit block ATC66 in FIG. And
The address conversion circuit blocks ATC76 and 86 are similar to the address conversion circuit block ATC66.

MCB0 to MCB8 are memory cell blocks, FB40 is a fuse circuit block for selection, and A0 to A.
8, / A0 to / A8 are address signals, A6R, A7R,
A8R, / A6R, / A7R, / A8R are internal conversion address signals, AR, / AR, / RA, N01 are signals, and F0
0 to F05 are fuses, VCC is a power supply voltage, VSS is a ground voltage, QN00 to QN05 are N channel type MOS transistors, QP00 is a P channel type MOS transistor, and ATC66, ATC76 and ATC86 are address conversion circuit blocks.

In the fifth embodiment, the redundant memory cell selection circuit is provided with nine memory cell blocks MCB0 to MCB8, one of the nine memory cell blocks is used as a spare memory cell block, and a defective memory cell block This is to select and use eight memory cell blocks that are not present.

The memory cell block MCB is configured to be selected by the logic voltage of the address signals A6 to A8.

For example, when the memory cell block MCB3 has a defect, the fuses F01, F03, F04 in the selection fuse circuit block FB40 are cut.

The circuit operation of the redundant memory cell selection circuit according to the fifth embodiment will be described below.

FIG. 13 shows a fuse circuit block FB for selection.
40, and in FIG. 13, first, the signal / RA
Becomes the logical voltage "L", the P-channel MOS transistor QP00 is turned on, and the signal N01 becomes the logical voltage "H". After that, the signal / RA becomes the logic voltage "H",
Next, the address signals A6 to A8 and / A6 to / A8 output the selected memory cell block selection address.
Here, the address signals / A6 to / A8 are the address signals A
6 to A8 is the reverse logic voltage signal.

When the memory cell block selection address corresponding to the memory cell block MCB3 is selected, the signal N
01 becomes the logic voltage "H", and the signal AR is held in the state of the logic voltage "H".

In this way, the memory cell block MC
The memory cell block MCB8 is selected instead of B3, and the memory cell block can be replaced.

A feature of the redundant memory cell selection circuit according to the fifth embodiment is that a defective memory cell block can be replaced for each memory cell block.

(Sixth Embodiment) A redundant memory cell selection circuit according to a sixth embodiment of the present invention will be described below with reference to FIGS. 10, 13 and 14.

FIG. 10 shows a redundant memory cell selection circuit according to the sixth embodiment, FIG. 13 shows a selection fuse circuit block FB40 in FIG. 10, and FIG.
Address translation circuit block ATC66 in FIG.
6 is the same as the address conversion circuit block ATC66. Here, the selection fuse circuit blocks FB100 to FB107 in FIG. 10 are similar to the selection fuse circuit block of the redundant memory cell selection circuit according to the conventional example shown in FIG.

In FIGS. 10, 13 and 14, MC
B0 to MCB8 are memory cell blocks, FB100 to F
B107 and FB40 are fuse circuit blocks for selection, R
WL00 to RWL08 are redundant word line groups, A0 to
A8, / A0 to / A8 are address signals, A6R, A7
R, A8R, / A6R, / A7R, / A8R are internal conversion address signals, AR, / AR, / RA, N01 are signals,
F00 to F05 are fuses, VCC is power supply voltage, VSS
Is the ground voltage, QN00 to QN05 are N-channel MOS
A transistor, QP00 is a P-channel MOS transistor, and ATC66, ATC76, ATC86 are address conversion circuit blocks.

The redundant memory cell selection circuit according to the sixth embodiment is such that each memory cell block in the fifth embodiment is provided with a redundant word line group, and MCB0 to MB are provided.
CB8 is provided with nine memory cell blocks, one of the nine memory cell blocks MCB0 to MCB8 is used as a spare memory cell block, and eight memory cell blocks with few defects are selected and used. The defective memory cell group in the memory cell block replaces the redundant memory cell group connected to the redundant word line group. The fifth method is to select the memory cell block.
It is similar to the embodiment of. Also, replacement of a defective memory cell group in each memory cell block is the same as in the conventional example.

The redundant memory cell selection circuit according to the sixth embodiment is characterized in that a defective memory cell block is replaced for each memory cell block, and a defective memory cell group is replaced with a redundant memory cell group in each memory cell block. It means that you can.

In the sixth embodiment, the same selection fuse circuit block as in the conventional example is used, but the same selection fuse circuit block as in the first embodiment is used. By doing so,
The number of selection fuse circuit blocks can be reduced, and the device area can be reduced.

(Seventh Embodiment) A redundant memory cell selection circuit according to the seventh embodiment of the present invention will be described below with reference to FIGS. 11, 12, 13 and 14.

FIG. 11 shows a redundant memory cell selection circuit according to the seventh embodiment, FIG. 12 shows a selection fuse circuit block FB30 in FIG. 11, and selection fuse circuit blocks FB31 to B37 are for selection. This is similar to the fuse circuit block FB30, FIG. 13 shows the selection fuse circuit block FB40 in FIG. 11, FIG. 14 shows the address conversion circuit block ATC66 in FIG. 11, and the address conversion circuit block A
TC76 and ATC86 are address conversion circuit blocks AT
It is the same as C66.

11, FIG. 12, FIG. 13 and FIG. 14, MCB0 to MCB8 are memory cell blocks and FB3.
0 to FB37 and FB40 are fuse circuit blocks for selection, A0 to A8, / A0 to / A8 are address signals, A6
R, A7R, A8R, / A6R, / A7R, / A8R are internal conversion address signals, SPEX, R30 to R37, A
R, / AR, ARX, / RA, N01 are signals, F00-
F17 is a fuse, VCC is a power supply voltage, VSS is a ground voltage, QN00 to QN17 are N-channel MOS transistors, QP00 is a P-channel MOS transistor, A
TC66, ATC76 and ATC86 are address conversion circuit blocks.

The redundant memory cell selection circuit according to the seventh embodiment uses a memory cell group of a memory cell block not selected in the fifth embodiment as a redundant memory cell group.

The redundant memory cell selection circuits are MCB0-M
The CB8 includes nine memory cell blocks, one of the nine MCB0 to MCB8 is used as a spare memory cell block, and the eight memory cell blocks are selected and used. For the defective memory cell group in the block, the memory cell group of the spare memory cell block is used as a redundant memory cell group. The method of selecting the memory cell block is the same as in the fifth embodiment. Further, the replacement of the defective memory cell group in each memory cell block is realized by preventing the address conversion circuit blocks ATC66 to ATC86 from operating when the address stored in the selection fuse circuit blocks FB30 to FB37 is selected. ing.

The redundant memory cell selection circuit according to the seventh embodiment is characterized in that a defective memory cell block is replaced for each memory cell block, and a defective memory cell group in each memory cell block is replaced in a spare memory cell block. That is, the memory cell group can be replaced.

(Eighth Embodiment) A redundant memory cell selection circuit according to the eighth embodiment of the present invention will be described below with reference to FIG.

FIG. 15 shows each memory cell block of the redundant memory cell selection circuit according to the eighth embodiment.
The redundant memory cell selection circuit according to the eighth embodiment is shown in FIG.
This is the same as the redundant memory cell selection circuit according to the fifth embodiment shown in FIG.

In FIG. 15, V11 is a bit line precharge power supply, F110 is a fuse, BE is a bit line equalize and precharge circuit, MC is a memory cell, and SA.
Is a sense amplifier circuit, C is a memory cell capacitor, Q
N and QNM are N channel type MOS transistors, QP is a P channel type MOS transistor, VBP, SBP, V
CP, SAP, SAN are signals, WL1, WL2, ..., W
L255 and WL256 are word lines, BL1, BL2
…, BL512, / BL1, / BL2,…, / BL51
2 is a bit line.

In the eighth embodiment, the redundant memory cell selection circuit can disconnect the transmission line of the bit line precharge power supply node signal VBP from the bit line precharge power supply V11 by cutting the fuse F110. is there.

When the device is in the standby state, the bit line equalize and precharge signal SBP is at the logical voltage "H" and the bit lines BL1 to BL512, / BL.
1 to / BL512 are connected to the transmission lines of the precharge power supply node signal VBP of the bit lines, respectively, while the word lines WL1 to WL256 are connected to the ground voltage VSS, respectively.

The feature of the redundant memory cell selection circuit according to the eighth embodiment is that when a defect that short-circuits the bit line and the word line of the memory cell block occurs in the manufacturing process, such defect occurs. The memory cell block is not used, and the fuse F110 is cut to disconnect the transmission line of the bit line precharge power supply node signal VBP and the bit line precharge power supply V11 so that the potentials of the bit line and the word line become the same. By doing so, it is possible to remedy the defective power supply current.

(Ninth Embodiment) A redundant memory cell selection circuit according to the ninth embodiment of the present invention will be described below with reference to FIG.

FIG. 16 shows each selection fuse circuit block of the redundant memory cell selection circuit according to the ninth embodiment. The selection fuse circuit block has a function of canceling an address once stored. ing. The entire structure of the redundant memory cell selection circuit according to the ninth embodiment is similar to that of the redundant memory cell selection circuit according to the conventional example shown in FIG. 17 except for the fuse circuit block for selection.

In FIG. 16, A0-A8, / A0- /
A8 is an address signal, F00 to F11, F120 are fuses, / RA, N121 to N123, R00, AALL.
Is a signal, VCC is a power supply voltage, VSS is a ground voltage, QN0
0 to QN11 and QN121 are N channel type MOS transistors, and QP00 and QP121 are P channel type MOS transistors. Signal AALL is address signal A0
This is a signal that becomes a logical voltage "H" when A8 is determined.

In the ninth embodiment, as a method of storing the address of the defective memory cell group repaired by the redundant memory cell group, as in the conventional example, the method shown in FIG.
Of the 12 fuses F00 to F11 of the fuse circuit block for selection shown in (6), 6 corresponding to the address to be selected
Just cut the book. Further, in order to cancel the address once stored in the selection fuse circuit block, the fuse F120 may be cut off.

The feature of the redundant memory cell selection circuit according to the ninth embodiment is that it is replaced with a defective memory cell group by providing a selection fuse circuit block having a function of canceling an address once stored. If the redundant memory cell group is defective, the address of the defective memory cell group stored in the selection fuse circuit block is canceled, and the address of the defective memory cell group is newly added to another selection fuse circuit block. Is stored, it is possible to replace the defective memory cell group with another redundant memory cell group, and it is possible to significantly improve the repair rate by the redundant memory cell group.

[0141]

As described above, according to the redundant memory cell selection circuit according to the inventions of claim 1, claim 3 and claim 4, the number of selected memory cells is less than the number of prepared redundant memory cell groups. Since it is possible to select any one of all the redundant memory cell groups in the fuse circuit block, a fuse circuit block for selection that requires a large layout area without reducing the repair rate by the redundant memory cell group Since the total area of the device can be reduced, the area of the entire device can be reduced.

Further, according to the redundant memory cell selection circuit according to the inventions of claims 2 and 5, the degree of freedom of relief by the redundant memory cell group can be increased.

According to the redundant memory cell selection circuit of the sixth aspect of the present invention, the total number of redundant memory cell groups and the number of selection fuse circuit blocks are reduced without lowering the degree of freedom of repair by the redundant memory cell groups. Therefore, the area of the entire device can be reduced. In addition, the repair rate by the redundant memory cell group can be improved.

According to the redundant memory cell selection circuit of the seventh aspect of the present invention, the total number of redundant memory cell groups and the number of selection fuse circuit blocks can be reduced, so that the total area of the device can be reduced. Further, the number of relievable memory cell groups in each memory cell block can be increased, and the degree of freedom of relieving by the redundant memory cell groups can be increased.

According to the redundant memory cell selection circuit of the eighth, ninth, tenth and eleventh inventions,
A memory cell block having a defective portion can be replaced for each memory cell block.

According to the redundant memory cell selection circuit of the twelfth aspect of the invention, when the redundant memory cell group replaced with the defective memory cell group is defective, the defective memory cell group is replaced with another redundant memory cell group. It can be replaced. Therefore, the repair rate by the redundant memory cell group can be significantly improved.

As a result of the above, according to the present invention, it is possible to provide an inexpensive and high-yield redundant memory cell selection circuit which suppresses an increase in chip area. As a result, a great effect that a cheaper semiconductor memory device can be supplied can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a redundant memory cell selection circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a selection fuse circuit block of a redundant memory cell selection circuit according to the first embodiment.

FIG. 3 is a block diagram showing a redundant memory cell selection circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a fuse circuit block for selection of a redundant memory cell selection circuit according to the second embodiment.

FIG. 5 is a block diagram showing a redundant memory cell selection circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing a fuse circuit block for selection of a redundant memory cell selection circuit according to the third embodiment.

FIG. 7 is a circuit diagram showing an address conversion circuit block of a redundant memory cell selection circuit according to the third embodiment.

FIG. 8 is a block diagram showing a redundant memory cell selection circuit according to a fourth embodiment of the present invention.

FIG. 9 is a block diagram showing a redundant memory cell selection circuit according to a fifth embodiment of the present invention.

FIG. 10 is a block diagram showing a redundant memory cell selection circuit according to a sixth embodiment of the present invention.

FIG. 11 is a block diagram showing a redundant memory cell selection circuit according to a seventh embodiment of the present invention.

FIG. 12 is a circuit diagram showing a fuse circuit block for selection of a redundant memory cell selection circuit according to the fourth and seventh embodiments.

FIG. 13 is a circuit diagram showing a selection fuse circuit block of a redundant memory cell selection circuit according to the fifth, sixth and seventh embodiments.

FIG. 14 is a circuit diagram showing an address conversion circuit block of a redundant memory cell selection circuit according to the fifth, sixth and seventh embodiments.

FIG. 15 is a circuit diagram showing a memory cell block of a redundant memory cell selection circuit according to an eighth embodiment of the present invention.

FIG. 16 is a circuit diagram showing a selection fuse circuit block of a redundant memory cell selection circuit according to a ninth embodiment of the present invention.

FIG. 17 is a block diagram showing a redundant memory cell selection circuit according to a conventional example.

FIG. 18 is a circuit diagram showing a selecting fuse circuit block of a redundant memory cell selecting circuit according to the conventional example.

[Explanation of symbols]

MCB0 to MCB8 memory cell block MCBR redundant memory cell dedicated block RWL00 to RWL71 redundant word line group FB00 to FB40 selection fuse circuit block ATC61 to ATC86 address conversion circuit block A0 to A8, / A0 to / A8 address signal F00 to F20, F110 , F120 fuses QN, QNM, QN00 to QN20 N-channel type MO
S transistor QP, QP00 to QP03 P channel type MOS transistor QP20, QP121 P channel type MOS transistor

Claims (12)

[Claims] 1. A plurality of memory cell blocks each having a plurality of redundant memory cell groups, and one selection fuse circuit block, wherein the one selection fuse circuit block is one of the plurality of memory cell blocks. A redundant memory cell selection circuit, wherein a redundant memory cell group corresponding to the one fuse circuit block for selection can be selected from a plurality of redundant memory cell groups included in any one of them. 2. The other select fuse circuit block capable of selecting any one of a plurality of redundant memory cell groups included in any one of the plurality of memory cell blocks. Redundant memory cell selection circuit. 3. The redundant memory according to claim 1, wherein a plurality of the one fuse circuit for selection are provided, and the total number of the one fuse circuit block for selection is smaller than the total number of the redundant memory cell groups. Cell selection circuit. 4. Each of the plurality of memory cell blocks has a plurality of memory cell groups, and the one selection fuse circuit block is one of memory cell block selection addresses corresponding to the plurality of memory cell blocks. And a memory cell block selection address stored in the one fuse circuit block, and one of memory cell group selection addresses corresponding to the plurality of memory cell groups in the memory cell block corresponding to the memory cell block selection address stored in the one selection fuse circuit block. When the memory cell block selection address and the memory cell group selection address stored in the one fuse circuit block for selection are selected, the plurality of memories included in the memory cell block corresponding to the memory cell block selection address Cell group A memory cell group corresponding to the selected memory cell group selection address corresponds to the one selection fuse circuit block of the plurality of redundant memory cell groups included in the memory cell block corresponding to the selected memory cell block selection address. 2. The redundant memory cell selection circuit according to claim 1, wherein the redundant memory cell selection circuit is configured so that it can be replaced with a redundant memory cell group. 5. A plurality of memory cell blocks each having M (M is a natural number) redundant memory cell groups and a plurality of memory cell groups, and first, second, third,
, M-1 and Mth selection fuse circuit blocks, and the total number of the first, second, third, ..., M-1, and Mth selection fuse circuit blocks is L (L Is a natural number), and is the Nth fuse circuit block for selection (N is 1 ≦ N), which is each of the first, second, third, ..., M−1, and Mth fuse circuit blocks for selection. Natural number satisfying ≦ M)
Can select any one of the N redundant memory cell groups corresponding to the N-th fuse circuit block for selection among the M redundant memory cell groups included in any of the plurality of memory cell blocks. The total number of the Nth selection fuse circuit blocks is [{L × (M−N + 1)} / M] −1 <K ≦ {L × (M
-N + 1)} / M which is a natural number of K or less, and the first selection fuse circuit block stores any one of the memory cell block selection addresses corresponding to the plurality of memory cell blocks. Storing one of memory cell group selection addresses corresponding to the plurality of memory cell groups included in the memory cell block corresponding to the memory cell block selection address stored in the first selection fuse circuit block, When the memory cell block selection address and the memory cell group selection address stored in one selection fuse circuit block are selected, among the plurality of memory cell groups included in the memory cell block corresponding to the memory cell block selection address. Select the relevant memory cell group A memory cell group and the corresponding dress,
Of the M redundant memory cell groups included in the memory cell block corresponding to the selected address of the memory cell block, the redundant memory cell group corresponding to the first fuse circuit block for selection can be replaced. A redundant memory cell selection circuit characterized in that 6. A plurality of memory cell blocks each having a memory cell group and a redundant memory cell group, and a memory cell group of any one of the plurality of memory cell blocks other than the memory cell block having the memory cell group. A redundant memory cell selection circuit comprising: a fuse circuit block for selection, which can be replaced with a redundant memory cell group included in one of the memory cell blocks. 7. A plurality of memory cell blocks each having a memory cell group, a redundant memory cell dedicated block having only a redundant memory cell group, and a memory cell group having any one of the plurality of memory cell blocks as the redundancy. A redundant memory cell selection circuit, comprising: a fuse circuit block for selection that can be replaced with a redundant memory cell group included in a memory cell dedicated block. 8. A plurality of first memory cell blocks each having a memory cell group, a second memory cell block having a memory cell group, and one of the plurality of first memory cell blocks. A redundant memory cell selection circuit, comprising one selection fuse circuit block that can be replaced with two memory cell blocks. 9. Each of the plurality of first and second memory cell blocks has a redundant memory cell group, and one of the plurality of first and second memory cell blocks has the memory cell group. 9. The redundant memory cell according to claim 8, further comprising another fuse circuit block for selection which can be replaced with the redundant memory cell group included in the first or second memory cell block including the memory cell group. Selection circuit. 10. Another selection capable of selecting a memory cell group of a first memory cell block, which is replaced with the second memory cell block of the plurality of first memory cell blocks, as a redundant memory cell group. 9. The redundant memory cell selection circuit according to claim 8, further comprising a fuse circuit block for use. 11. Each of the plurality of first memory cell blocks has a bit line and a word line, and the second of the plurality of first memory cell blocks.
9. The redundant memory cell selection circuit according to claim 8, wherein the bit line and the word line of the first memory cell block which is replaced with the memory cell block of FIG. . 12. A memory cell group for storing and storing any one of a plurality of memory cell groups, a plurality of redundant memory cell groups, and a plurality of memory cell group selection addresses corresponding to the plurality of memory cell groups, respectively. A fuse circuit block for selection that replaces the memory cell group corresponding to the selected address with any of the plurality of redundant memory cell groups, and the fuse circuit block for selection can cancel the stored memory cell group selection address. A redundant memory cell selection circuit characterized by the above.