JPH06338620A - Non-volatile semiconductor memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To suppress the fluctuation in the threshold voltage of a MOS transistor by a method wherein a gate electrode is provided on a memory gate insulating film and a MOS gate insulating film and then a source region, a drain region and an interlayer insulating film are connected to the gate electrode region by wirings through contact holes. CONSTITUTION:A memory gate insulating film 19 comprising a tunnel oxide film 13, a silicon nitride film 15 and a top oxide film 17 is provided on a semiconductor substrate 11. Next, a MOS gate insulating film 23 comprising a silicon oxide film 21 and the silicon nitride film 15 is provided adjacently to the memory gate insulating film 19. Next, a gate electrode 27 is provided on the memory gate insulating film 19 and the MOS gate insulating film 23. Next, an interlayer insulating film 39 having a source region 31, a drain region 33 and contact holes is arranged in the matching region with the gate electrode 27. Finally, wirings 43 are formed in contact holes and then the source 31 and the drain region 33 are connected to each other thereby enabling the threshold value of a MOS transistor to be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor nonvolatile memory device and a method of manufacturing the same, and particularly to a gate electrode-a top oxide film made of a silicon oxide film-a silicon nitride film-
The present invention relates to a structure of a semiconductor non-volatile memory device having a so-called MONOS structure, which has a tunnel oxide film-semiconductor substrate structure made of a silicon oxide film, and a manufacturing method for forming the structure.

[0002]

2. Description of the Related Art In a memory transistor having a MONOS structure, a threshold voltage when electric charges are accumulated at an interface between a silicon nitride film and a top oxide film and a threshold voltage when electric charges are not accumulated. Information is stored by using the voltage difference between and.

In this MONOS structure memory transistor, a channel is formed in the channel region under the gate electrode because the threshold voltage is negative when no charge is stored.

At this time, a MOS (metal-oxide-semiconductor) transistor is required to allow the drain current to flow only when the memory transistor is selected so that the drain current flowing from the source region to the drain region does not flow. And

As a semiconductor non-volatile memory device having this memory transistor and a MOS transistor, for example, there is one described in Japanese Patent Laid-Open No. 4-337672.
The structure of the memory transistor and the MOS transistor described in this publication will be described with reference to the sectional view of FIG.

As shown in FIG. 11, the MOS gate insulating film 23 and the memory gate insulating film 19 are provided on the semiconductor substrate 11 so as to be in contact with each other. The memory gate insulating film 19 is formed of the top oxide film 17 and the silicon nitride film 15.
And the tunnel oxide film 13, and the MOS gate insulating film 23 is composed of the silicon oxide film 21.

The memory gate insulating film 19 and the MO
A gate electrode 27 containing a high concentration of impurities is provided on the S gate insulating film 23.

Further, the source region 31 and the drain region 33 are formed on the semiconductor substrate 11 in the region where the gate electrode 27 is aligned.
And. That is, the memory transistor 35 and the MOS
The transistor 37 and the transistor 37 are provided so as to be in contact with each other.

[0009]

In the semiconductor non-volatile memory device described with reference to FIG. 11, since the memory transistor 35 and the MOS transistor 37 are provided so as to be in contact with each other, the size of the semiconductor non-volatile memory device can be reduced. It has an advantage that it can be realized.

However, the semiconductor nonvolatile memory device shown in FIG. 11 has a problem that the impurities of the gate electrode 27 diffuse into the semiconductor substrate 11 through the MOS gate insulating film 23.

When the impurities contained in the gate electrode 27 are introduced into the semiconductor substrate 11, there arises a problem that the impurity concentration of the semiconductor substrate 11 changes and the threshold voltage of the MOS transistor changes.

The object of the present invention is to solve the above problems by
It is an object of the present invention to provide a structure of a semiconductor nonvolatile memory device in which the threshold voltage of an OS transistor does not change and a manufacturing method for obtaining this structure.

[0013]

In order to achieve the above object, the structure of the semiconductor nonvolatile memory device of the present invention and the manufacturing method thereof adopt the following means.

A semiconductor non-volatile memory device according to the present invention comprises a memory gate insulating film made of a tunnel oxide film, a silicon nitride film and a top oxide film provided on a semiconductor substrate, and a MOS gate insulating film made of a silicon oxide film and a silicon nitride film. A film, a gate electrode provided on the memory gate insulating film and the MOS gate insulating film, a source region and a drain region provided in a region where the gate electrodes are aligned, an interlayer insulating film having a contact hole, and a source via the contact hole. And a wiring connected to the region drain region.

A method of manufacturing a semiconductor nonvolatile memory device according to the present invention comprises forming a silicon oxide film on a semiconductor substrate,
A step of forming a photosensitive resin on the silicon oxide film, patterning the silicon oxide film using the photosensitive resin as an etching mask, forming a tunnel oxide film, a silicon nitride film, and a top oxide film, and then forming a film on the top oxide film. A step of forming a photosensitive resin, removing the top oxide film using the photosensitive resin as an etching mask, and forming a gate electrode material on the entire surface,
Step of forming a photosensitive resin on the gate electrode material, patterning the gate electrode material using the photosensitive resin as an etching mask to form a gate electrode, further patterning the silicon nitride film, and then aligning the gate electrode Forming a source region and a drain region by introducing impurities into the semiconductor substrate in the region, and forming an interlayer insulating film on the entire surface,
And a step of forming a contact hole by patterning an interlayer insulating film using a photosensitive resin and forming a wiring.

[0016]

In the semiconductor nonvolatile memory device of the present invention, the MOS gate insulating film has a two-layer structure of a silicon oxide film and a silicon nitride film.

Therefore, in the semiconductor nonvolatile memory device of the present invention, the diffusion of impurities from the gate electrode is suppressed by the silicon nitride film, the introduction of impurities into the semiconductor substrate is suppressed, and the threshold voltage of the MOS transistor is changed. Does not occur.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 10 showing the structure and the manufacturing method of the semiconductor nonvolatile memory device of the present invention, the illustration of the element isolation insulating film for insulating isolation between elements is omitted.

First, the structure of the semiconductor nonvolatile memory device of the present invention will be described with reference to the sectional view of FIG.

As shown in FIG. 5, the semiconductor nonvolatile memory device of the present invention has a memory gate insulating film 19 including a tunnel oxide film 13, a silicon nitride film 15, and a top oxide film 17 provided on a semiconductor substrate 11. .

Further, a MOS gate insulating film 23 composed of a silicon oxide film 21 and a silicon nitride film 15 is provided on the semiconductor substrate 11 adjacent to the memory gate insulating film 19. That is, the memory gate insulating film 19 and the MOS gate insulating film 23 are provided so as to be in contact with each other. And the silicon nitride film 15 of the memory gate insulating film 19,
The silicon nitride film 15 of the MOS gate insulating film 23 has almost the same thickness.

The memory gate insulating film 19 and the MO
A gate electrode 27 is provided on the S gate insulating film 23.

Further, in a region aligned with the gate electrode 27,
A semiconductor substrate 11 is provided with a source region 31 and a drain region 33 of opposite conductivity type.

Further, an interlayer insulating film 39 having a contact hole 41 is provided. And this contact hole 41
A wiring 43 connecting the source region 31 and the drain region 33 is provided via the.

The semiconductor nonvolatile memory device of the present invention is an MO
The S gate insulating film 23 has a two-layer structure of a silicon oxide film 21 and a silicon nitride film 15.

Therefore, in the semiconductor nonvolatile memory device of the present invention, the diffusion of impurities from the gate electrode 27 is suppressed by the silicon nitride film 21, and the semiconductor substrate 11 of impurities is suppressed.
Can be suppressed. As a result, the threshold voltage of the MOS transistor does not change.

Next, a manufacturing method for forming the semiconductor nonvolatile memory device shown in FIG. 5 will be described with reference to the sectional views of FIGS.

First, as shown in FIG. 1, a semiconductor substrate 11 having an N conductivity type is subjected to an oxidation treatment to form a silicon oxide film 21 made of a silicon oxide film with a film thickness of 29 nm.

This silicon oxide film 21 is formed at a temperature of 1000 ° C. for 3 hours in a mixed gas atmosphere of oxygen and nitrogen.
The condition is 0 minutes.

After that, a photosensitive resin 29 is formed on the entire surface of the silicon oxide film 21 by a spin coating method, and an exposure process and a development process are performed using a predetermined photomask to form a region including a MOS transistor formation region. Patterning is performed so as to form the photosensitive resin 29.

Next, as shown in FIG.
Is used as an etching mask to pattern the silicon oxide film 21.

This silicon oxide film 21 is etched by
It is performed by wet etching using a hydrofluoric acid-based etching solution.

After that, the photosensitive resin 29 on the silicon oxide film 21 used as the etching mask is removed.

After that, an oxidation treatment is performed to form a tunnel oxide film 13 made of a silicon oxide film having a film thickness of 2 nm in the region on the semiconductor substrate 11 where the silicon oxide film 21 is not formed.

This tunnel oxide film 13 is formed in a mixed gas atmosphere of oxygen and nitrogen at a temperature of 900 ° C. for 3 hours.
It is formed by performing an oxidation treatment for 0 minutes.

By this oxidation treatment, the film thickness of the silicon oxide film 21 is increased, and the film thickness of 29 nm described above becomes a film thickness of 30 nm.

Then, dichlorosilane (SiH ₂ Cl
₂ ) and ammonia (NH ₃ ) are used as reaction gases to form a silicon nitride film 15 having a film thickness of 11 nm on the entire surface by chemical vapor deposition.

After that, an oxidation process is performed to form a top oxide film 17 made of a silicon oxide film with a thickness of 5 nm on the silicon nitride film 15. By forming the top oxide film 17 on the silicon nitride film 15, the silicon nitride film 15 is formed.
The film thickness of is reduced from the initial film thickness of 11 nm to 8 nm.

The top oxide film 17 is formed in a steam oxidizing atmosphere at a temperature of 950 ° C. for 60 minutes.

After that, a photosensitive resin 29 is formed on the entire surface by spin coating, and exposure and development processes are performed using a predetermined photomask so that the region including the MOS transistor formation region is opened, that is, silicon oxide. The photosensitive resin 29 is patterned so that the region on the film 21 is opened.

Next, as shown in FIG.
Is used as an etching mask to remove the top oxide film 17 in the region where the photosensitive resin 29 is not formed.

The etching of the top oxide film 17 is performed by wet etching using a hydrofluoric acid type etching solution.

After that, the photosensitive resin 29 used as the etching mask on the top oxide film 17 is removed.

As a result, the MOS gate insulating film 23 including the silicon oxide film 21 and the silicon nitride film 15 is formed in the MOS transistor formation region, and the tunnel oxide film 13, the silicon nitride film 15 and the top oxide film are formed in the memory transistor formation region. The memory gate insulating film 19 composed of 17 and 17 can be formed. Here, the silicon nitride film 15 forming the MOS gate insulating film 23 and the memory gate insulating film 1
The silicon nitride film 15 forming 9 has substantially the same film thickness.

After that, monosilane (Si
The film thickness is 400n by the chemical vapor deposition method using H ₄ ).
A gate electrode material 25 made of a polycrystalline silicon film of m is formed on the entire surface.

After that, a photosensitive resin 29 is formed on the entire surface of the gate electrode material 25 by a spin coating method, exposed and developed using a predetermined photomask, and exposed on the formation region of the memory transistor and the MOS transistor. Resin 2
Patterning to form 9.

Next, as shown in FIG. 4, the photosensitive resin 29
Is used as an etching mask to etch the gate electrode material 25 to form a gate electrode 27.

The etching of the gate electrode 27 is performed by using a reactive ion etching apparatus using a mixed gas of sulfur hexafluoride (SF ₆ ) and oxygen (O ₂ ) as an etching gas.

Further, the silicon nitride film 15 is etched using the photosensitive resin 29 as an etching mask.

This silicon nitride film 15 is etched by
Using a reactive ion etching apparatus, a mixed gas of sulfur hexafluoride (SF ₆ ), helium (He), and trifluoromethane (CHF ₃ ) is used as an etching gas.

After that, the photosensitive resin 29 used as an etching mask for the gate electrode material 25 and the silicon nitride film 15
To remove.

As a result, the memory gate insulating film 19 including the tunnel oxide film 13, the silicon nitride film 15 and the top oxide film 17, the silicon oxide film 21 and the silicon nitride film 15 are formed in the region under the gate electrode 27. The MOS gate insulating film 23 can be formed.

After that, boron, which is an impurity having a conductivity type opposite to that of the semiconductor substrate 11, is introduced into the semiconductor substrate 11 in the region where the gate electrode 27 is aligned to form the source region 31 and the drain region 33. The ion implantation amount of boron for forming the source region 31 and the drain region 33 is performed under the condition of about 3 × 10 ¹⁵ cm ⁻² .

Next, as shown in FIG. 5, an interlayer insulating film 39 made of a silicon oxide film containing phosphorus and boron is formed into a layer 400.
It is formed by a chemical vapor deposition method with a film thickness of about nm.

After that, a photosensitive resin (not shown) is formed on the interlayer insulating film 39 by a spin coating method, and an exposure process and a development process are performed using a predetermined photomask to form an opening corresponding to the contact hole. The patterning is performed so as to form the photosensitive resin that is included.

Thereafter, the patterned photosensitive resin is used as an etching mask to pattern the interlayer insulating film 39 to form a contact hole 41.

After that, a wiring material made of aluminum containing silicon and copper is formed by using a sputtering apparatus.
It is formed with a film thickness of about 00 nm.

Thereafter, a photosensitive resin (not shown) is formed on the wiring material by a spin coating method, and an exposure process and a development process are performed using a predetermined photomask to form a photosensitive resin having a shape corresponding to the wiring. Pattern the resin.

After that, the wiring material is patterned by using the patterned photosensitive resin as an etching mask to form the wiring 43, whereby a semiconductor nonvolatile memory device can be obtained.

As a result, a semiconductor nonvolatile memory device having the MOS transistor 37 adjacent to the memory transistor 35 can be formed.

Next, a semiconductor nonvolatile memory device according to another embodiment of the present invention will be described. First, the structure of the semiconductor nonvolatile memory device of the present invention will be described with reference to the sectional view of FIG.

As shown in FIG. 10, the semiconductor nonvolatile memory device of the present invention has a memory gate insulating film 19 including a tunnel oxide film 13, a silicon nitride film 15, and a top oxide film 17 provided on a semiconductor substrate 11. .

Further, a MOS gate insulating film 23 including a silicon oxide film 21 and a silicon nitride film 15 is provided on the semiconductor substrate 11 on both sides of the memory gate insulating film 19 so as to be in contact with the memory gate insulating film 19. .

The memory gate insulating film 19 and the MO
A gate electrode 27 is provided on the S gate insulating film 23.

Further, in a region aligned with the gate electrode 27,
A semiconductor substrate 11 is provided with a source region 31 and a drain region 33 of opposite conductivity type.

Further, an interlayer insulating film 39 having a contact hole 41 is provided. And this contact hole 41
A wiring 43 connecting the source region 31 and the drain region 33 is provided via the.

The semiconductor non-volatile memory device shown in FIG. 10 and the semiconductor non-volatile memory device shown in FIG. 5 are different in structure from each other. In the structure of FIG. 5, a MOS transistor 37 is provided in one region of the memory transistor 35. Although provided, FIG.
In the configuration of 0, in the regions on both sides of the memory transistor 35,
The MOS transistor 37 is provided so as to be in contact with the memory transistor 35.

The semiconductor nonvolatile memory device of the present invention is an MO
The S gate insulating film 23 has a two-layer structure of a silicon oxide film 21 and a silicon nitride film 15.

Therefore, in the semiconductor nonvolatile memory device of the present invention, the diffusion of impurities from the gate electrode 27 is suppressed by the silicon nitride film 21, and the semiconductor substrate 11 of impurities is suppressed.
Can be suppressed. As a result, the threshold voltage of the MOS transistor does not change.

Next, a manufacturing method for forming the semiconductor nonvolatile memory device shown in FIG. 10 will be described with reference to FIGS.
Will be described with reference to the sectional view of FIG.

First, as shown in FIG. 6, the semiconductor substrate 11 having an N-type conductivity is oxidized to form a silicon oxide film 21 made of a silicon oxide film with a film thickness of 29 nm.

After that, a photosensitive resin 29 is formed on the entire surface of the silicon oxide film 21 by a spin coating method, and an exposure process and a development process are performed using a predetermined photomask so that the formation region of the memory transistor is opened. Photosensitive resin 29
Pattern.

Next, as shown in FIG. 7, the photosensitive resin 29
Is used as an etching mask to pattern the silicon oxide film 21, and an opening corresponding to the memory transistor formation region is formed in the silicon oxide film 21. After that, the photosensitive resin 29 on the silicon oxide film 21 used as the etching mask is removed.

Then, an oxidation process is performed to form a tunnel oxide film 13 made of a silicon oxide film having a thickness of 2 nm on the semiconductor substrate 11 in the opening of the silicon oxide film 21.

By this oxidation treatment, the film thickness of the silicon oxide film 21 is increased, and the film thickness of 29 nm described above becomes the film thickness of 30 nm.

Then, dichlorosilane (SiH ₂ Cl
₂ ) and ammonia (NH ₃ ) are used as reaction gases to form a silicon nitride film 15 having a film thickness of 11 nm on the entire surface by chemical vapor deposition.

Then, an oxidation process is performed to form a top oxide film 17 of a silicon oxide film with a thickness of 5 nm on the silicon nitride film 15. By forming the top oxide film 17 on the silicon nitride film 15, the silicon nitride film 15 is formed.
The film thickness of is reduced from the initial film thickness of 11 nm to 8 nm.

After that, a photosensitive resin 29 is formed on the entire surface by a spin coating method, and exposure and development processing is performed using a predetermined photomask so that a region including a MOS transistor formation region is opened, that is, silicon oxide. The photosensitive resin 29 is patterned so that the region on the film 21 is opened.

Next, as shown in FIG.
Is used as an etching mask to remove the top oxide film 17 in the region where the photosensitive resin 29 is not formed. afterwards,
The photosensitive resin 29 on the top oxide film 17 used as the etching mask is removed.

As a result, the MOS gate insulating film 23 including the silicon oxide film 21 and the silicon nitride film 15 is formed in the MOS transistor formation region, and the tunnel oxide film 13, the silicon nitride film 15 and the top oxide film are formed in the memory transistor formation region. The memory gate insulating film 19 composed of 17 and 17 can be formed. Here, the silicon nitride film 15 forming the MOS gate insulating film 23 and the memory gate insulating film 1
The silicon nitride film 15 forming 9 has substantially the same film thickness.

After that, monosilane (Si
The film thickness is 400n by the chemical vapor deposition method using H ₄ ).
A gate electrode material 25 made of a polycrystalline silicon film of m is formed on the entire surface.

After that, a photosensitive resin 29 is formed on the entire surface of the gate electrode material 25 by a spin coating method, and exposure and development processes are performed using a predetermined photomask to form a photosensitive region in the memory transistor and MOS transistor formation regions. Resin 29
Are patterned so as to form

Next, as shown in FIG. 9, the photosensitive resin 29
Is used as an etching mask to etch the gate electrode material 25 to form a gate electrode 27. Further, the silicon nitride film 1 is formed by using the photosensitive resin 29 as an etching mask.
Etch 5.

Then, the photosensitive resin 29 used as an etching mask for the gate electrode material 25 and the silicon nitride film 15 is used.
To remove.

As a result, the silicon oxide film 21 and the silicon nitride film are formed on both sides of the memory gate insulating film 19 including the tunnel oxide film 13, the silicon nitride film 15 and the top oxide film 17 in the region under the gate electrode 27. It is possible to form a MOS gate insulating film 23 composed of

After that, boron, which is an impurity having a conductivity type opposite to that of the semiconductor substrate 11, is introduced into the semiconductor substrate 11 in the region where the gate electrode 27 is aligned to form the source region 31 and the drain region 33.

Next, as shown in FIG. 10, an interlayer insulating film 39 made of a silicon oxide film containing phosphorus and boron is formed into a layer 40.
It is formed by a chemical vapor deposition method with a film thickness of about 0 nm.

After that, a photosensitive resin (not shown) is formed on the interlayer insulating film 39 by a spin coating method, and an exposure process and a development process are performed using a predetermined photomask to form an opening corresponding to the contact hole. The photosensitive resin which it has is patterned.

Thereafter, the patterned photosensitive resin is used as an etching mask to pattern the interlayer insulating film 39 to form a contact hole 41.

After that, a wiring material made of aluminum containing silicon and copper is formed by using a sputtering apparatus.
It is formed with a film thickness of about 00 nm.

Thereafter, a photosensitive resin (not shown) is formed on the wiring material by a spin coating method, and an exposure process and a development process are performed using a predetermined photomask to form a photosensitive resin having a shape corresponding to the wiring. Pattern the resin.

After that, the wiring material is patterned by using the patterned photosensitive resin as an etching mask to form the wiring 43, whereby the semiconductor nonvolatile memory device can be obtained.

As a result, it is possible to form a semiconductor nonvolatile memory device having the MOS transistors 37 on both sides of the memory transistor 35.

In the above description, the gate electrode 2
Although boron has been described as an example of impurities contained in No. 7, the means of the present invention can be applied to a semiconductor nonvolatile memory device having a gate electrode containing phosphorus or arsenic.

[0095]

As is apparent from the above description, according to the structure and the manufacturing method of the semiconductor nonvolatile memory device of the present invention,
Diffusion of impurities from the gate electrode can be suppressed by the silicon nitride film. Therefore, it is possible to suppress the fluctuation of the threshold voltage of the MOS transistor, and a highly reliable semiconductor nonvolatile memory device can be obtained.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor nonvolatile memory device according to an example of the present invention.

FIG. 2 is a cross-sectional view showing the method of manufacturing the semiconductor nonvolatile memory device according to the example of the invention.

FIG. 3 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory device in the example of the present invention.

FIG. 4 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory device in the example of the present invention.

FIG. 5 is a cross-sectional view showing the structure and manufacturing method of a semiconductor nonvolatile memory device according to an example of the present invention.

FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory device in the example of the present invention.

FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory device in the example of the present invention.

FIG. 8 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory device in the example of the present invention.

FIG. 9 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory device in the example of the present invention.

FIG. 10 is a cross-sectional view showing the structure and manufacturing method of a semiconductor nonvolatile memory device according to an example of the present invention.

FIG. 11 is a sectional view showing a structure of a semiconductor nonvolatile memory device in a conventional example.

[Explanation of symbols]

 13 tunnel oxide film 15 silicon nitride film 17 top oxide film 19 memory gate insulating film 21 silicon oxide film 23 MOS gate insulating film 27 gate electrode

Claims (6)

[Claims] 1. A memory gate insulating film made of a tunnel oxide film, a silicon nitride film, and a top oxide film provided on a semiconductor substrate, and an M made of a silicon oxide film and a silicon nitride film.
An OS gate insulating film, a gate electrode provided on the memory gate insulating film and the MOS gate insulating film, a source region drain region provided in a region where the gate electrodes are aligned, an interlayer insulating film having a contact hole, and a contact hole. A semiconductor non-volatile memory device comprising: a wiring connected to the source region and the drain region through the wiring. 2. A memory gate insulating film comprising a tunnel oxide film, a silicon nitride film and a top oxide film provided on a semiconductor substrate, and an M comprising a silicon oxide film and a silicon nitride film.
An OS gate insulating film, a gate electrode provided on the memory gate insulating film and the MOS gate insulating film, a source region drain region provided in a region where the gate electrodes are aligned, an interlayer insulating film having a contact hole, and a contact hole. A semiconductor non-volatile memory device comprising: a wiring connected to a source region and a drain region via a wiring, wherein the silicon nitride film of the memory gate insulating film and the silicon nitride film of the MOS gate insulating film have substantially the same thickness. 3. A memory gate insulating film made of a tunnel oxide film, a silicon nitride film and a top oxide film provided on a semiconductor substrate, and a MOS gate made of a silicon oxide film and a silicon nitride film provided adjacent to the memory gate insulating film. An insulating film, a gate electrode provided on the memory gate insulating film and the MOS gate insulating film, a source region drain region provided in a region where the gate electrodes are aligned, an interlayer insulating film having a contact hole, and a contact hole A semiconductor nonvolatile memory device, comprising: a wiring connected to a source region and a drain region; and a MOS transistor provided adjacent to the memory transistor. 4. A memory gate insulating film made of a tunnel oxide film, a silicon nitride film and a top oxide film provided on a semiconductor substrate, and a MOS gate insulating film made of a silicon oxide film and a silicon nitride film provided on both sides of the memory gate insulating film. A film, a gate electrode provided on the memory gate insulating film and the MOS gate insulating film, a source region and a drain region provided in a region where the gate electrodes are aligned, an interlayer insulating film having a contact hole, and a source via the contact hole. A semiconductor nonvolatile memory device, comprising: a wiring connected to a region drain region; and MOS transistors provided on both sides of the memory transistor. 5. A step of forming a silicon oxide film on a semiconductor substrate, forming a photosensitive resin on the silicon oxide film, patterning the silicon oxide film using the photosensitive resin as an etching mask, and a tunnel oxide film. A step of forming a silicon nitride film and a top oxide film, forming a photosensitive resin on the top oxide film, removing the top oxide film using the photosensitive resin as an etching mask, and forming a gate electrode material on the entire surface. , A step of forming a photosensitive resin on the gate electrode material, patterning the gate electrode material by using the photosensitive resin as an etching mask to form a gate electrode, further patterning a silicon nitride film, and then aligning the gate electrode. A step of introducing an impurity into the semiconductor substrate in the formed region to form a source region and a drain region, and forming an interlayer insulating film on the entire surface and using a photosensitive resin. And a step of forming a contact hole by patterning the interlayer insulating film and forming a wiring, the method for manufacturing a semiconductor nonvolatile memory device. 6. A step of forming a silicon oxide film on a semiconductor substrate, forming a photosensitive resin on the silicon oxide film, patterning the silicon oxide film using the photosensitive resin as an etching mask, and a tunnel oxide film. A step of forming a silicon nitride film and a top oxide film, forming a photosensitive resin on the top oxide film, and using the photosensitive resin as an etching mask to remove the top oxide film in a region on the silicon oxide film;
A step of forming a gate electrode material on the entire surface and forming a photosensitive resin on the gate electrode material, and patterning the gate electrode material using the photosensitive resin as an etching mask to form a gate electrode, and further forming a silicon nitride film. After patterning, a step of forming a source region and a drain region by introducing an impurity of a conductivity type opposite to that of the semiconductor substrate into the semiconductor substrate in a region where the gate electrodes are aligned, and forming an interlayer insulating film on the entire surface. And a step of forming a contact hole by patterning an interlayer insulating film using a photosensitive resin and forming a wiring, the method for manufacturing a semiconductor nonvolatile memory device.